Texas Instruments C28 Series User manual

TI
C28x DSP Design Workshop
Student Guide
Technical Training
Organization
C28x
Revision 5.0
February 2004

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Revision History
October 2001 – Revision 1.0
January 2002 – Revision 2.0
May 2002 – Revision 3.0
June 2002 – Revision 3.1
October 2002 – Revision 4.0
December 2002 – Revision 4.1
July 2003 – Revision 4.2
August 2003 – Revision 4.21
February 2004 – Revision 5.0
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ii C28x - Introduction

C28x Workshop
C28x Workshop
C28x DSP Design Workshop
C28x DSP Design Workshop
Texas Instruments
Texas Instruments
Technical Training
Technical Training
Copyright © 2004 Texas Instruments. All rights reserved.
Copyright © 2004 Texas Instruments. All rights reserved.
Technical Training
Technical Training
Organization
Organization
T
TTO TO
eZdsp™ F2812 Starter Kit
eZdsp
eZdsp is a trademark of Spectrum Digital, Inc. is a trademark of Spectrum Digital, Inc.
Introductions
Introductions
Introductions

Name
Name

Company
Company

Project Responsibilities
Project Responsibilities

DSP / Microcontroller Experience
DSP / Microcontroller Experience

TMS320 DSP Experience
TMS320 DSP Experience

Hardware / Software
Hardware / Software - -Assembly / C Assembly / C

Interests
Interests
C28x - Introduction iii

C28x Workshop
iv C28x - Introduction
C28x Workshop Outline
C28x Workshop Outline
C28x Workshop Outline
1.
1. Architecture Overview Architecture Overview
2.
2. Programming Development Environment Programming Development Environment
3.
3. Peripheral Register Header Files Peripheral Register Header Files
4.
4. Reset and Interrupts Reset and Interrupts
5.
5. System Initialization System Initialization
6.
6. Analog Analog- -to to- -Digital Converter Digital Converter
7.
7. Event Manager Event Manager
8.
8. Numerical Concepts and IQ Math Numerical Concepts and IQ Math
9.
9. Using DSP/BIOS Using DSP/BIOS
10.
10. System Design System Design
11.
11. Communications Communications
12.
12. Support Resources Support Resources
eZdsp™ F2812 Hardware
eZdsp
eZdsp™ F2812 Hardware ™ F2812 Hardware
Parallel Port/
Parallel Port/
JTAG
JTAG
Controller
Controller
Interface (P3)
Interface (P3)
I/O Interface (P4/P8/P7)
I/O Interface (P4/P8/P7)
ANALOG
ANALOG
Interface (P5/P9)
Interface (P5/P9)
SRAM
SRAM
64K x 16
64K x 16
JTAG Interface (P1)
JTAG Interface (P1) EXPANSION EXPANSION
Data & Address (P2)
Data & Address (P2)
Power
Power
Connector (P6)
Connector (P6)
+5V
+5V
TMS320F2812
TMS320F2812 - -DSP DSP

Architecture Overview
Introduction
This architecture overview introduces the basic architecture of the TMS320C28x (C28x) series of
Digital Signal Processors from Texas Instruments. The C28x series adds a new level of general
purpose processing ability unseen in any previous DSP chips. The C28x is ideal for applications
combining DSP, standard microcontroller processing, efficient C code execution, or operating
system tasks.
Learning Objectives
When this module is complete, you should have a basic understanding of the C28x architecture
and how all of its components work together to create a high-end, uniprocessor control system.
Learning Objectives
Learning Objectives

Identify the three main components
Identify the three main components
of the C28x
of the C28x

List the key features of the C28x
List the key features of the C28x
CPU
CPU

Identify the memory capabilities of
Identify the memory capabilities of
the C28x
the C28x

Identify the peripherals available on
Identify the peripherals available on
the C28x
the C28x
C28x - Architecture Overview 1 - 1

Module Topics
Module Topics
Architecture Overview.............................................................................................................................. 1-1
Module Topics......................................................................................................................................... 1-2
What is the TMS320C28x?...................................................................................................................... 1-3
C28x CPU ............................................................................................................................................... 1-4
Multiplier, ALU, and Shifters............................................................................................................. 1-5
TMS320C28x Internal Bussing .......................................................................................................... 1-6
Special Instructions............................................................................................................................. 1-7
Pipeline Advantage............................................................................................................................. 1-8
Memory ................................................................................................................................................... 1-9
Memory Map ...................................................................................................................................... 1-9
Code Security Module (CSM)...........................................................................................................1-10
Peripherals .........................................................................................................................................1-10
Fast Interrupt Response.........................................................................................................................1-11
C28 Mode...............................................................................................................................................1-12
Reset.......................................................................................................................................................1-13
Summary ................................................................................................................................................1-14
1 - 2 C28x - Architecture Overview

What is the TMS320C28x?
What is the TMS320C28x?
The TMS320C28x is a 32-bit fixed point DSP that specializes in high performance control
applications such as, robotics, industrial automation, mass storage devices, lighting, optical
networking, power supplies, and other control applications needing a single processor to solve a
high performance application.
C28x Block Diagram
C28x Block Diagram
32x32 bit
Multiplier
32x32 bit
32x32 bit
Multiplier
Multiplier
Sectored
Flash
Sectored
Sectored
Flash
Flash
A(18
A(18- -0) 0)
D(15
D(15- -0) 0)
Program Bus
Program Bus
Data Bus
Data Bus
RAM
RAM
RAM
Boot
ROM
Boot
Boot
ROM
ROM
22
22
32-bit
Auxiliary
Registers
32
32- -bit bit
Auxiliary
Auxiliary
Registers
Registers
3
32 bit
Timers
3
3
32 bit
32 bit
Timers
Timers
Realtime
JTAG
Realtime
Realtime
JTAG
JTAG CPU
CPU
Register Bus
Register Bus
R-M-W
Atomic
ALU
R
R- -M M- -W W
Atomic
Atomic
ALU
ALU
PIE
PIE
Interrupt
Interrupt
Manager
Manager
32
32
32
32
32
32
Event
Manager A
Event
Event
Manager A
Manager A
Event
Manager B
Event
Event
Manager B
Manager B
12-bit ADC
12
12- -bit ADC bit ADC
Watchdog
Watchdog
Watchdog
McBSP
McBSP
McBSP
CAN2.0B
CAN2.0B
CAN2.0B
SCI-A
SCI
SCI- -A A
SCI-B
SCI
SCI- -B B
SPI
SPI
SPI
GPIO
GPIO
GPIO
The C28x architecture can be divided into 3 functional blocks:
• CPU and busing
• Memory
• Peripherals
C28x - Architecture Overview 1 - 3

C28x CPU
C28x CPU
The C28x is a highly integrated, high performance solution for demanding control applications.
The C28x is a cross between a general microcontroller and a digital signal processor, balancing
the code density of a RISC chip and the execution speed of a DSP with the architecture,
firmware, and development tools of a microcontroller.
The DSP features include a modified Harvard architecture and circular addressing. The RISC
features are single-cycle instruction execution, register-to-register operations, and modified
Harvard architecture. The microcontroller features include ease of use through an intuitive
instruction set, byte packing and unpacking, and bit manipulation.
C28x CPU
C28x CPU

32
32- -bit fixed bit fixed- -point DSP point DSP

32 x 32 bit fixed
32 x 32 bit fixed- -point MAC point MAC

Dual 16 x 16 single
Dual 16 x 16 single- -cycle fixed cycle fixed- -
point MAC (DMAC)
point MAC (DMAC)

32
32- -/64 /64- -bit saturation bit saturation

64/32 and 32/32 modulus division
64/32 and 32/32 modulus division

Fast interrupt service time
Fast interrupt service time

Single cycle read
Single cycle read- -modify modify- -write write
instructions
instructions

Unique real
Unique real- -time debugging time debugging
capabilities
capabilities

Upward code compatibility
Upward code compatibility
Data Bus
Data Bus
32-bit
Auxiliary
Registers
32
32- -bit bit
Auxiliary
Auxiliary
Registers
Registers
3
32 bit
Timers
3
3
32 bit
32 bit
Timers
Timers
Realtime
JTAG
Realtime
Realtime
JTAG
JTAG CPU
CPU
Register Bus
Register Bus
R-M-W
Atomic
ALU
R
R- -M M- -W W
Atomic
Atomic
ALU
ALU
Program Bus
Program Bus

MCU/DSP balancing code density
MCU/DSP balancing code density
& execution time.
& execution time.

Supports 32
Supports 32- -bit instructions bit instructions
for improved execution time;
for improved execution time;

Supports 16
Supports 16- -bit instructions bit instructions
for improved code efficiency
for improved code efficiency
PIE
PIE
Interrupt
Interrupt
Manager
Manager
32x32 bit
Multiplier
32x32 bit
32x32 bit
Multiplier
Multiplier
The C28x design supports an efficient C engine with hardware that allows the C compiler to
generate compact code. Multiple busses and an internal register bus allow an efficient and
flexible way to operate on the data. The architecture is also supported by powerful addressing
modes, which allow the compiler as well as the assembly programmer to generate compact code
that is almost one to one corresponded to the C code.
The C28x is as efficient in DSP math tasks as it is in system control tasks that typically are
handled by microcontroller devices. This efficiency removes the need for a second processor in
many systems.
The C28x is one of several members of the fixed-point generations of digital signal processors
(DSPs) in the TMS320 family. The C28x is source-code and object-code compatible with the
C27x. In addition, the C28x is source code compatible with the 24x/240x DSP and previously
written code can be reassembled to run on a C28x device. This allows for migration of existing
code onto the C28x.
1 - 4 C28x - Architecture Overview

C28x CPU
Multiplier, ALU, and Shifters
XT (32) or T/TL
XT (32) or T/TL
MULTIPLIER
MULTIPLIER
32 x 32 or
32 x 32 or
Dual 16 x 16
Dual 16 x 16
P (32) or PH/PL
P (32) or PH/PL
AH (16)
AH (16)
C28x Multiplier and ALU / Shifters
C28x Multiplier and ALU / Shifters
Data Bus
Data Bus
Data Bus
Data Bus
Program Bus
Program Bus
ALU (32)
ALU (32)
32
32
32
32
32
32
32
32
32
32
AL (16)
AL (16)
32
32
32
32
•
•
16/32
16/32
8/16
8/16
Shift R/L (0
Shift R/L (0- -16) 16)
ACC (32)
ACC (32)
AH.MSB AH.LSB
AH.MSB AH.LSB AL.MSB AL.LSB AL.MSB AL.LSB
32
32
Shift R/L (0
Shift R/L (0- -16) 16)
•
•
32
32
Shift R/L (0
Shift R/L (0- -16) 16)
32
32
16
16
The 32 x 32-bit MAC capabilities of the C28x and its 64-bit processing capabilities, enable the
C28x to efficiently handle higher numerical resolution problems that would otherwise demand a
more expensive floating-point processor solution. Along with this is the capability to perform
two 16 x 16-bit multiply accumulate instructions simultaneously or Dual MACs (DMAC).
C28x
C28x XARn XARn, DP and Memory , DP and Memory
XAR0
XAR0
XAR1
XAR1
XAR2
XAR2
XAR3
XAR3
XAR4
XAR4
XAR5
XAR5
XAR6
XAR6
XAR7
XAR7
ARAU
ARAU
MUX
MUX
Data Memory
Data Memory
MUX
MUX
DP (16)
DP (16)
Data Bus
Data Bus
Program Bus
Program Bus
6 LSB
6 LSB
from IR
from IR
XARn
XARn → →32 32- -bits bits
ARn
ARn → →16 16- -bits bits
22
22
32
32
C28x - Architecture Overview 1 - 5

C28x CPU
TMS320C28x Internal Bussing
As with many DSP type devices, multiple busses are used to move data between the memories
and peripherals and the CPU. The C28x memory bus architecture contains:
• A program read bus (22 bit address line and 32 bit data line)
• A data read bus (32 bit address line and 32 bit data line)
• A data write bus (32 bit address line and 32 bit data line)
C28x Internal Bus Structure
C28x Internal Bus Structure
Data
Data- -write Address Bus (32) write Address Bus (32)
Program Address Bus (22)
Program Address Bus (22)
Execution
Execution
R
R- -M M- -W W
Atomic
Atomic
ALU
ALU
Real
Real- -Time Time
Emulation
Emulation
&
&
Test
Test
Engine
Engine
Program
Program- -read Data Bus (32) read Data Bus (32)
JTAG
JTAG
Program
Program
Decoder
Decoder
PC
PC
XAR0
XAR0
to
to
XAR7
XAR7
SP
SP
DP
DP @X @X
ARAU
ARAU MPY32x32
MPY32x32
XT
XT
P
P
ACC
ACC
ALU
ALU
Registers
Registers Debug
Debug
Register Bus / Result Bus
Register Bus / Result Bus
Data/Program
Data/Program- -write Data Bus (32) write Data Bus (32)
Data
Data- -read Address Bus (32) read Address Bus (32)
Data
Data- -read Data Bus (32) read Data Bus (32)
Memory
Memory
Data
Data
(4G * 16)
(4G * 16)
Program
Program
(4M* 16)
(4M* 16)
Standard
Standard
Peripherals
Peripherals
External
External
Interfaces
Interfaces
The 32-bit-wide data busses enable single cycle 32-bit operations. This multiple bus architecture,
known as a Harvard Bus Architecture enables the C28x to fetch an instruction, read a data value
and write a data value in a single cycle. All peripherals and memories are attached to the memory
bus and will prioritize memory accesses.
1 - 6 C28x - Architecture Overview

C28x CPU
Special Instructions
C28x Atomic Read/Modify/Write
C28x Atomic Read/Modify/Write
Registers
Registers ALU / MPY
ALU / MPY
LOAD
LOAD
STORE
STORE
WRITE
WRITE
READ
READ
CPU
CPU Mem
Mem

Atomic Instructions Benefits:
Atomic Instructions Benefits:
¾
¾Simpler programming
Simpler programming
¾
¾Smaller, faster code Smaller, faster code
¾
¾Uninterruptible (Atomic)
Uninterruptible (Atomic)
¾
¾More efficient compiler More efficient compiler
AND *XAR2,#1234h
AND *XAR2,#1234h
2 words / 1 cycles
2 words / 1 cycles
Atomic Read/Modify/Write
Atomic Read/Modify/Write
MOV
MOV AL,*XAR2 AL,*XAR2
AND
AND AL,#1234h AL,#1234h
MOV
MOV *XAR2,AL *XAR2,AL
DINT
DINT
EINT
EINT
6 words / 6 cycles
6 words / 6 cycles
Standard Load/Store
Standard Load/Store
Atomics are small common instructions that are non-interuptable. The atomic ALU capability
supports instructions and code that manages tasks and processes. These instructions usually
execute several cycles faster than traditional coding.
C28x - Architecture Overview 1 - 7

C28x CPU
Pipeline Advantage
F
F1
1 F
F2
2 D
D1
1 D
D2
2 R
R1
1 R
R2
2 X
X
C28x Pipeline
C28x Pipeline
Protected Pipeline
Protected Pipeline
¾
¾Order of results are as written in
Order of results are as written in
source code
source code
¾
¾Programmer need not worry about
Programmer need not worry about
the pipeline
the pipeline
8
8- -stage pipeline stage pipeline
F
F1
1 F
F2
2 D
D1
1 D
D2
2 R
R1
1 R
R2
2 X
X
F
F1
1 F
F2
2 D
D1
1 D
D2
2 R
R1
1 R
R2
2 X
X
F
F1
1 F
F2
2 D
D1
1 D
D2
2 R
R1
1 R
R2
2 X
X
F
F1
1 F
F2
2 D
D1
1 D
D2
2 R
R1
1 R
R2
2 X
X
F
F1
1 F
F2
2 D
D1
1 D
D2
2 R
R1
1 R
R2
2 X
X
F
F1
1 F
F2
2 D
D1
1 D
D2
2 R
R1
1 R
R2
2 X
X
F
F1
1 F
F2
2 D
D1
1 D
D2
2 R
R1
1 R
R2
2 X
X
A
A
B
B
C
C
D
D
E
E
F
F
G
G
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
E & G Access
E & G Access
same address
same address
R
R1
1 R
R2
2 X
XW W
D
D2
2 R
R1
1 R
R2
2 X W
X W
F1: Instruction Address
F1: Instruction Address
F2: Instruction Content
F2: Instruction Content
D1: Decode Instruction
D1: Decode Instruction
D2: Resolve Operand Addr
D2: Resolve Operand Addr
R1: Operand Address
R1: Operand Address
R2: Get Operand
R2: Get Operand
X: CPU doing “real” work
X: CPU doing “real” work
W: store content to memory
W: store content to memory
H
H
The C28x uses a special 8-stage protected pipeline to maximize the throughput. This protected
pipeline prevents a write to and a read from the same location from occurring out of order.
This pipelining also enables the C28x to execute at high speeds without resorting to expensive
high-speed memories. Special branch-look-ahead hardware minimizes the latency for conditional
discontinuities. Special store conditional operations further improve performance.
1 - 8 C28x - Architecture Overview

Memory
Memory
The memory space on the C28x is divided into program and data space. There are several
different types of memory available that can be used as both program or data space. They include
the flash memory, single access RAM (SARAM), expanded SARAM, and Boot ROM which is
factory programmed with boot software routines or standard tables used in math related
algorithms.
Memory Map
The C28x CPU contains no memory, but can access memory both on and off the chip. The C28x
uses 32-bit data addresses and 22-bit program addresses. This allows for a total address reach of
4G words (1 word = 16 bits) in data space and 4M words in program space. Memory blocks on
all C28x designs are uniformly mapped to both program and data space.
This memory map shows the different blocks of memory available to the program and data space.
TMS320F2812 Memory Map
TMS320F2812 Memory Map
MO SARAM (1K)
MO SARAM (1K)
M1 SARAM (1K)
M1 SARAM (1K)
LO SARAM (4K)
LO SARAM (4K)
L1 SARAM (4K)
L1 SARAM (4K)
HO SARAM (8K)
HO SARAM (8K)
Boot ROM (4K)
Boot ROM (4K)
MP/MC=0
MP/MC=0
BROM vector (32)
BROM vector (32)
MP/MC=0 ENPIE=0
MP/MC=0 ENPIE=0
OTP (1K)
OTP (1K)
FLASH (128K)
FLASH (128K)
reserved
reserved
reserved
PF 0 (2K)
PF 0 (2K)
reserved
reserved
PF 1 (4K)
PF 1 (4K)
reserved
PF 2 (4K)
PF 2 (4K)
reserved
PIE vector
PIE vector
(256)
(256)
ENPIE=1
ENPIE=1 XINT Zone 0 (8K)
XINT Zone 1 (8K)
XINT Zone 2 (0.5M)
XINT Zone 6 (0.5M)
XINT Zone 7 (16K)
MP/MC=1
XINT Vector-RAM (32)
MP/MC=1 ENPIE=0
reserved
reserved
reserved
Data
Data | Program | Program
0x00 0000
0x00 0000
0x00 0400
0x00 0400
0x00 0800
0x00 0800
0x00 0D00
0x00 0D00
0x00 1000
0x00 1000
0x00 6000
0x00 6000
0x00 7000
0x00 7000
0x00 8000
0x00 8000
0x00 9000
0x00 9000
0x00 A000
0x00 A000
0x3D 7800
0x3D 7800
0x3D 8000
0x3D 8000
0x3F 8000
0x3F 8000
0x3F A000
0x3F A000
0x3F F000
0x3F F000
0x3F FFC0
0x3F FFC0
0x3F C000
0x3F C000
0x18 0000
0x18 0000
0x10 0000
0x10 0000
0x08 0000
0x08 0000
0x00 4000
0x00 4000
0x00 2000
0x00 2000
Data
Data | Program | Program
128
128- -Bit Password Bit Password
CSM: LO, L1
CSM: LO, L1
OTP, FLASH
OTP, FLASH
reserved
0x3D 7C00
0x3D 7C00
C28x - Architecture Overview 1 - 9

Memory
Code Security Module (CSM)
Code Security Module
Code Security Module

Prevents reverse engineering and
Prevents reverse engineering and
protects valuable intellectual property
protects valuable intellectual property

128 128- -bit user defined password is stored in Flash bit user defined password is stored in Flash

128
128- -bits = 2 bits = 2128
128 = 3.4 x 10
= 3.4 x 1038
38 possible passwords
possible passwords

To try 1 password every 2 cycles at 150 MHz, it To try 1 password every 2 cycles at 150 MHz, it
would take at least 1.4 x 10
would take at least 1.4 x 1023
23 years to try all
years to try all
possible combinations!
possible combinations!
LO SARAM (4K)
LO SARAM (4K)
L1 SARAM (4K)
L1 SARAM (4K)
OTP (1K)
OTP (1K)
FLASH (128K)
FLASH (128K)
reserved
0x00 8000
0x00 8000
0x00 9000
0x00 9000
0x00 A000
0x00 A000
0x3D 7800
0x3D 7800
0x3D 8000
0x3D 8000
128
128- -Bit Password Bit Password
reserved
0x3D 7C00
0x3D 7C00
Peripherals
The C28x comes with many built in peripherals optimized to support control applications. These
peripherals vary depending on which C28x device you choose.
• Event Manager
• Analog-to-Digital Converter
• Watchdog Timer
• SPI
• SCI
• CAN
• McBSP
• GPIO
1 - 10 C28x - Architecture Overview

Fast Interrupt Response
Fast Interrupt Response
The fast interrupt response, with automatic context save of critical registers, resulting in a device
that is capable of servicing many asynchronous events with minimal latency. C28x implements a
zero cycle penalty to do 14 registers context saved and restored during an interrupt. This feature
helps reduces the interrupt service routine overheads.
C28x Fast Interrupt Response Manager
C28x Fast Interrupt Response Manager
¾
¾96 dedicated PIE
96 dedicated PIE
vectors
vectors
¾
¾No software decision
No software decision
making required
making required
¾
¾Direct access to RAM
Direct access to RAM
vectors
vectors
¾
¾Auto flags update
Auto flags update
¾
¾Concurrent auto
Concurrent auto
context save
context save
28x CPU Interrupt logic
28x CPU Interrupt logic
28x
28x
CPU
CPU
INTM
INTM
IFR
IFR IER
IER
96
96
Peripheral Interrupts 12x8 = 96
Peripheral Interrupts 12x8 = 96
12 interrupts
12 interrupts
INT1 to
INT1 to
INT12
INT12
PIE
PIE
Register
Register
Map
Map
PIE module
PIE module
For 96
For 96
interrupts
interrupts
T
TST0 ST0
AH
AH AL AL
PH
PH PL PL
AR1 (L)
AR1 (L) AR0 (L) AR0 (L)
DP
DP ST1 ST1
DBSTAT
DBSTAT IER IER
PC(msw)
PC(msw) PC(lsw) PC(lsw)
Auto Context Save
Auto Context Save
C28x - Architecture Overview 1 - 11

C28 Mode
C28 Mode
The C28x is one of several members of the fixed-point generations of digital signal processors
(DSPs) in the TMS320 family. The C28x is source-code and object-code compatible with the
C27x. In addition, the C28x is source code compatable with the 24x/240x DSP and previously
written code can be reassembled to run on a C28x device. This allows for migration of existing
code onto the C28x.
C28x / C24x Modes
C28x / C24x Modes
C24x Mode
C24x Mode 1 1 1 1
C28x Mode
C28x Mode 1 1 0 0
Test Mode (default)
Test Mode (default) 0 0 0 0
Reserved
Reserved 0 0 1 1
OBJMODE AMODE
OBJMODE AMODE
Mode Bits
Mode Bits Compiler Compiler
Option
Option
Mode Type
Mode Type
¾
¾C24x source
C24x source- -compatible mode: compatible mode:
¾
¾Allows you to run C24x source code which has been reassembled
Allows you to run C24x source code which has been reassembled
using the C28x code generation tools (need new vectors)
using the C28x code generation tools (need new vectors)
¾
¾C28x mode:
C28x mode:
¾
¾Can take advantage of all the C28x native features
Can take advantage of all the C28x native features
-
-v28 v28
-
-v28 v28 - -m20 m20
-
-v27 v27
(workshop)
(workshop)
1 - 12 C28x - Architecture Overview

Reset
Reset
Reset
Reset – –Bootloader Bootloader
Reset
Reset
OBJMODE=0 AMODE=0
OBJMODE=0 AMODE=0
ENPIE=0 VMAP=1
ENPIE=0 VMAP=1
Boot determined by
Boot determined by
state of GPIO pins
state of GPIO pins
Reset vector fetched
Reset vector fetched
from boot ROM
from boot ROM
0x3F FFC0
0x3F FFC0
XMPNMC=0
XMPNMC=0
(microcomputer mode)
(microcomputer mode)
Execution
Execution
Entry Point
Entry Point
H0 SARAM
H0 SARAM
Note:
Note:
Details of the various boot options will be
Details of the various boot options will be
discussed in the Reset and Interrupts module
discussed in the Reset and Interrupts module
Bootloader
Bootloader sets sets
OBJMODE = 1
OBJMODE = 1
AMODE = 0
AMODE = 0
C28x - Architecture Overview 1 - 13

Summary
1 - 14 C28x - Architecture Overview
Summary
Summary
Summary

High performance 32
High performance 32- -bit DSP bit DSP

32 x 32 bit or dual 16 x 16 bit MAC
32 x 32 bit or dual 16 x 16 bit MAC

Atomic read
Atomic read- -modify modify- -write instructions write instructions

8
8- -stage fully protected pipeline stage fully protected pipeline

Fast interrupt response manager
Fast interrupt response manager

128Kw on
128Kw on- -chip flash memory chip flash memory

Code security module (CSM)
Code security module (CSM)

Two event managers
Two event managers

12 12- -bit ADC module bit ADC module

56 shared GPIO pins
56 shared GPIO pins

Watchdog timer
Watchdog timer

Communications peripherals
Communications peripherals

Programming Development Environment
Introduction
This module will explain how to use Code Composer Studio (CCS) integrated development
environment (IDE) tools to develop a program. Creating projects and setting building options
will be covered. Use and the purpose of the linker command file will be described. Additionally,
the DSP/BIOS Configuration Tool will be used to handle system memory and system setup.
Learning Objectives
Learning Objectives
Learning Objectives

Use Code Composer Studio to:
Use Code Composer Studio to:

Create a Create a Project Project

Set Set Build Options Build Options

Create a
Create a user user linker command file which: linker command file which:

Describes a system’s available memory
Describes a system’s available memory

Indicates where sections will be placed Indicates where sections will be placed
in memory
in memory

Use
Use DSP/BIOS Configuration Tool DSP/BIOS Configuration Tool to: to:

Handle system memory and system setup Handle system memory and system setup

Create a . Create a .cdb cdb and . and .cmd cmd file file
C28x - Programming Development Environment 2 - 1

Module Topics
Module Topics
Programming Development Environment .............................................................................................. 2-1
Module Topics......................................................................................................................................... 2-2
Code Composer Studio ........................................................................................................................... 2-3
Software Development and COFF Concepts...................................................................................... 2-3
Projects ............................................................................................................................................... 2-5
Build Options...................................................................................................................................... 2-6
Creating a Linker Command File ........................................................................................................... 2-9
Sections .............................................................................................................................................. 2-9
Linker Command Files (.cmd).........................................................................................................2-12
Memory-Map Description .................................................................................................................2-12
Section Placement..............................................................................................................................2-14
Exercise 2a.............................................................................................................................................2-15
Summary: Linker Command File ......................................................................................................2-16
Lab 2a: Linker Command File...............................................................................................................2-17
DSP/BIOS Configuration Tool...............................................................................................................2-21
Lab 2b: DSP/BIOS Configuration Tool .................................................................................................2-26
Solutions.................................................................................................................................................2-30
2 - 2 C28x - Programming Development Environment