Texas Instruments TPS65381EVM User manual

TPS65381EVM User's Guide
User's Guide
Literature Number: SLVU847
April 2013

Contents
1 Introduction ........................................................................................................................ 4
2 Background ........................................................................................................................ 5
3 Setup ................................................................................................................................. 6
3.1 I/O Connector Description ................................................................................................. 6
3.2 Supply ........................................................................................................................ 7
3.3 Jumper Setting .............................................................................................................. 7
3.4 Test Points ................................................................................................................... 8
3.5 VDD6 Voltage Regulator ................................................................................................... 8
3.6 VDD1 Voltage Regulator ................................................................................................... 8
3.7 VDD3/5 Voltage Regulator ................................................................................................. 8
3.8 VDD5 Voltage Regulator ................................................................................................... 9
3.9 VSOUT1 Voltage Regulator ............................................................................................... 9
4 TIGER GUI Software ........................................................................................................... 10
5 Go into ACTIVE Mode - Step by Step Description .................................................................. 11
6 EVM Schematic ................................................................................................................. 14
7 Board Picture .................................................................................................................... 15
7.1 Top .......................................................................................................................... 15
7.2 Bottom ...................................................................................................................... 16
8 Board Assembly ................................................................................................................ 17
9 Board Layout .................................................................................................................... 19
10 Bill of Material ................................................................................................................... 21
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List of Figures
5-1. WD Timing.................................................................................................................. 11
5-2. Start-Up Screen............................................................................................................ 11
5-3. After IGN Start, Device Has Started, Iqis About 30 mA, Device is in Diagnostic Mode ......................... 12
5-4. Clear ERR Fail and WD Fail............................................................................................. 12
5-5. Clear DIAG EXIT MASK = Device is in Active Mode................................................................. 13
5-6. Set ENDRV and Read Back Pin Level ENDRV....................................................................... 13
6-1. TPS65381EVM Schematic............................................................................................... 14
7-1. EVM Top View............................................................................................................. 15
7-2. EVM Bottom View......................................................................................................... 16
8-1. Top Assembly Layer ...................................................................................................... 17
8-2. Bottom Assembly Layer .................................................................................................. 18
9-1. Top Layer Routing......................................................................................................... 19
9-2. Layer 2 (AGND) Routing ................................................................................................. 19
9-3. Layer 3 Routing............................................................................................................ 20
9-4. Layer 4 Routing............................................................................................................ 20
List of Tables
1-1. Device and Package Configurations ..................................................................................... 4
3-1. EVM Connectors............................................................................................................ 6
3-2. EVM Voltages ............................................................................................................... 7
3-3. EVM Jumper................................................................................................................. 7
3-4. EVM Test Points ............................................................................................................ 8
3
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Chapter 1
SLVU847–April 2013
Introduction
The Texas Instruments TPS65381EVM evaluation module (EVM) helps engineers evaluate the operation
and performance of the TPS65381-Q1 power supply IC for safety applications. The device offers
configurability through a serial peripheral interface (SPI).
The EVM contains the TPS65381-Q1 device and some circuitry for basic operation. It has a connection for
a optional TIGER board (not included) to configure the TPS65381-Q1 device through the SPI but can also
run without or with different SPIs, for example, from a microcontroller (MCU) supplied by the EVM.
Table 1-1. Device and Package Configurations
CONVERTER IC PACKAGE
IC1 TPS65381QDAPRQ1 DAP-32
PowerPAD is a trademark of Texas Instruments.
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Chapter 2
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Background
The TPS65381-Q1 device is a multi-rail power supply designed to supply MCUs in safety-critical
applications, such as those found in automotive. The devices supports Texas Instruments TMS570LS
series 16 or 32-Bit RISC Flash MCU and other MCUs with dual-core lockstep (LS) or loosely coupled (LC)
architectures.
The TPS65381-Q1 device integrates multiple supply rails to power the MCU, controller area network
(CAN) or FlexRay and an external sensor. An asynchronous buck switch-mode power supply converter
with internal FET converts the input battery voltage to a 6-V pre-regulator output. This 6 V is used to
supply the other regulators.
A fixed 5V linear regulator with internal field effect transistor (FET) is integrated to be used as, for
example, CAN supply. A second linear regulator with also internal FET regulates the 6 V to a selectable 5-
V or 3.3-V MCU input/output (IO) voltage.
The TPS65381-Q1 device comprises a linear regulator controller with external FET and resistor divider,
regulating the 6 V to an externally adjustable core voltage between 0.8 V and 3.3 V.
The device comprises a sensor supply with short-to-ground and short-to-battery protection. This supply
can therefore be used to power a sensor outside the electronic control unit (ECU).
The device has an integrated charge pump to provide overdrive voltage for the internal regulators. A
reverse battery protection can be obtained by using the charge pump output to control an external N-
channel metal oxide semiconductor (NMOS) transistor. This solution allows for a lower minimum battery
voltage operation compared to a traditional reverse battery blocking diode.
The device monitors under- and overvoltage on all regulator outputs, battery voltage and internal supply
rails. A second bandgap reference, independent from the main bandgap reference, is used for the under-
and overvoltage monitoring to prevent any drifts in the main bandgap reference from going undetected. In
addition, regulator current limits and temperature protections are implemented.
The TPS65381-Q1 device functional safety architecture features a question-answer watchdog (WD), an
MCU error signal monitor, clock monitoring on internal oscillators, self-check on clock monitor, cyclic
redundancy check (CRC) on non-volatile memory, and a reset circuit for the MCU. A build-in self-test
(BIST) allows for monitoring the device functionality at start up. A dedicated DIAGNOSTIC-state allows the
MCU to check TPS65381-Q1 device safety functions.
5
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Chapter 3
SLVU847–April 2013
Setup
This section describes the jumpers and connectors on the EVM and how to properly connect, set up and
use the TPS65381EVM.
3.1 I/O Connector Description
Three connectors are placed to supply the device under test (DUT) to get access to different signals for
programming or to measure.
CON1 is the supply connector to provide the battery voltage and offer a connection to SPI.
CON2 is the output connector to deliver the output voltage of the different regulators.
CON3 is a connector to either the SPI of an application circuit, or the optional TIGER board which
provides a universal serial bus (USB) to SPI connection.
Table 3-1. EVM Connectors
CON1 CON2 CON3
PIN NO. SIGNALS PIN NO. SIGNALS PIN NO. SIGNALS
1 VBAT_SAFING 1 GND 1 SDO
2 GND 2 ENDRV 2 GND
3 VBATP 3 GND 3 SCLK
4 GND 4 IGN 4 GND
5 VCP 5 GND 5 NCS
6 GND 6 VBATP 6 GND
7 VDD5 7 GND 7 SDI
8 GND 8 VDD6 8 GND
9 VDD3/5 9 GND 9 Open
10 GND 10 VDD6 10 Open
11 VDD1 11 GND 11 ENDRV
12 GND 12 VDD3/5 12 RES
13 RES 13 GND 13 CANWU
14 GND 14 VDD3/5 14 ERROR
15 DIAG_OUT 15 GND 15 DIAGOUT
16 GND 16 VDD5 16 IGN
17 NCS 17 GND 17 Open
18 GND 18 VDD5 18 Open
19 SDI 19 GND 19 VDDIO
20 GND 20 VDD1 20 Open
21 SDO 21 GND 21 Open
22 GND 22 VDD1 22 Open
23 SCLK 23 GND 23 Open
24 GND 24 VBATP 24 Open
25 VDDIO 25 GND 25 Open
26 GND 26 VSIN 26 Open
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Table 3-1. EVM Connectors (continued)
CON1 CON2 CON3
27 ERROR 27 GND 27 Open
28 GND 28 VDD6 28 Open
29 CANWU 29 GND 29 Open
30 GND 30 VSOUT1 30 Open
3.2 Supply
The input voltage range for the converter is VBATP = VBAT_SAFING = 5.8 volts to 36 volts. It should be
supplied to CON1, pin 1 (VBAT_SAFING) and 3 (VBATP) with respect to pin 2 and 4 (GND).
Table 3-2. EVM Voltages
PARAMETER TEST CONDITIONS CONNECTOR PIN MIN TYP MAX UNIT
VBATP Can be connected to VBAT_SAFING 1 3 5.8 14 36 V
by placing J1
VBAT_SAFIN Can be connected to VBAT_P by 1 1 5.8 14 36 V
G placing J1
VDD6 2 8, 10 5.4 6 6.6 V
VDD1 2 20, 22 0.8 1.2 3.3 V
VDD3/5 2 12, 14 3.23 / 4.9 3 / 5 3.36 / 5.1 V
VDD5 2 16, 18 4.9 5 5.1 V
VSOUT1 2 30 3.3 5 9.5 V
VDDIO 1 25 3.3 5 V
3.3 Jumper Setting
For proper operation of the TPS65381-Q1 device, the jumper should be properly configured. The
recommended setting is shown in the table below.
Table 3-3. EVM Jumper(1)
J NO. DESCRIPTION OPTION STANDARD
J1 Connect VBAF_SAFING to VBATP. Open and supply VBAT_SAFING with separate Set
supply voltage.
J2 Use VSOUT1 as follower or with gain. Open VSOUT1 has gain defined by R11 and R12. Set Open
is VSOUT1 is follower.
J3 Select the tracking input. Open for non-tracking mode or connect to VDD3/5 or Open
VDD5 for tracking mode.
J4 Select the VDDIO voltage. Connect to VDD3/5 or VDD5. VDD5
J5 Select output voltage VDD3/5. Open VDD3/5 = 3.3 V. Set VDD3/5 = 5 V. Set
J6 IGN supported by TIGER board and SPI Open is not supported by SPI. Closed can be Open
connector CON3. supported by SPI.
CON2, pin 4 Connector 2 (pin 4) is the IGN pin; must be Remove the jumper to use the EVM together with Set
connected to CON2, pin 4 to turn the DUT TIGER board.
on.
(1) For start-up without using the TIGER board or external IGN signal, IGN (pin 4 of CON2) can be connected to VBATP (pin 6 of
CON2) by setting a jumper to start up the device.
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3.4 Test Points
Test points are placed to measure different nodes on the board.
Table 3-4. EVM Test Points
NO. TEST POINT
1 VBAT_SAFING
2 RES
3 DIAG_OUT
4 NCS
5 SDI
6 SDO
7 SCLK
8 ERROR
9 CANWU
10 VSOUT1
11 VSIN
12 VSOUT1
13 VTRACK1
14 VDD5
15 VDD3/5
16 VDD1_SENSE
17 VDD6
18 VDD1_G
19 VBATP
20 IGN
21 SEL_VDD3/5
22 ENDRV
3.5 VDD6 Voltage Regulator
The VDD6 voltage regulator is supplied by VBATP. Several blocking capacitors C8, C9 and C10 are
connected from VBATP to GND, helping stabilize the supply voltage. For long supply cables, additional
bigger capacitors could be helpful. The node SDN6 is the switching node of the buck converter. L1 is the
inductor connected to SDN6 and VDD6. The freewheeling diode D1 allows current flow when the device
internal high-side transistor is turned off. C11 and C12 are the output capacitors of the VDD6 regulator.
R16 is the ESR of C12 for better stability. The VDD6 pin is the feedback line to close the control loop of
the VDD6 regulator, and is also the supply node for the VDD3/5 and VDD5 regulators. The output voltage
VDD6 is available at CON2, pins 8 and 10.
3.6 VDD1 Voltage Regulator
The VDD1 regulator has a device internal control amplifier and an external NMOS power transistor. The
regulator is supplied by VDD6. C14 stabilizes the input voltage of the VDD1 regulator. The voltage
dividers R13 and R14 define the output voltage and close the control loop to VDD1_SENSE. Additionally,
a minimum required current flows though both resistors. The output capacitors C15 and C16 are needed
to stabilize the control loop. The output voltage VDD1 is available at CON1, pin 11, and CON2, pins 20
and 22.
3.7 VDD3/5 Voltage Regulator
The VDD3/5 regulator is supplied internally by VDD6. SEL_VDD3/5 can select the output voltage. If the
pin is open, 3.3 V is selected. If the pin is shorted to GND, 5 V is selected. The output capacitor C6 is
needed to stabilize the output voltage. The output voltage VDD3/5 is available at CON1, pin 9, and CON2,
pins 12 and 14.
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www.ti.com VDD5 Voltage Regulator
3.8 VDD5 Voltage Regulator
The VDD5 regulator is supplied internally by VDD6. The output capacitor C5 is needed to stabilize the
output voltage. The output voltage VDD5 is available at CON1, pin 7, and CON2, pins 16 and 18.
3.9 VSOUT1 Voltage Regulator
VSIN is the supply pin of VSOUT1 voltage regulator. If VSIN is connected to VDD6, lower power
dissipation can be achieved by placing a jumper to short between pin 26 and 28 of CON2. If VSIN is
connected to VBATP, higher power dissipation can be achieved by placing a jumper to short between pin
24 and 26 of CON2. The capacitor C3 stabilizes the input voltage. The voltage regulator can be used in
tracking or non-tracking mode. Additionally, the voltage dividers R1_4 and R1_5 can be used to define the
output voltage. The capacitor C4 is needed for stable operation. The output voltage VSOUT1 is available
at CON2, pin 30.
9
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Chapter 4
SLVU847–April 2013
TIGER GUI Software
The graphical user interface (GUI) software is intended to support a quick start of the TPS65381-Q1
evaluation. As the USB to SPI connection, a TIGER board is needed to run the software. It can be
connected directly to CON3.
After first starting the software, the installation of a .net environment might be needed. It can be
downloaded at microsoft.com.
The software provides the user a GUI for easy set-up and control of the TPS65381-Q1 device.
10 TIGER GUI Software SLVU847–April 2013
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WD
Tt = 74msT
t = 1%
Chapter 5
SLVU847–April 2013
Go into ACTIVE Mode - Step by Step Description
To go into active mode several steps are needed, please refer to the data sheet SLVSBC4.
1. Install the GUI software on a Windows PC.
2. Connect the EVM with the TIGER board, and the TIGER board to a PC USB connector.
3. Start the GUI software.
4. Power up the EVM by connecting VBATP and VBAT to, for example, a 14-V power supply. Observe
the quiescent current.
5. Drive the WD with T = 74 ms, t(high) = 1%, (standard setting), values can be changed
(see SLVSBC4).
Figure 5-1. WD Timing
6. Set AutoSet DIAG EXIT MASK.
Figure 5-2. Start-Up Screen
7. After setting the DIAG EXIT MASK, press the IGN button.
11
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Figure 5-3. After IGN Start, Device Has Started, Iqis About 30 mA, Device is in Diagnostic Mode
8. Press the Clr button below ERR Fail and WD Fail.
Figure 5-4. Clear ERR Fail and WD Fail
9. Reset DIAG EXIT MASK.
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Figure 5-5. Clear DIAG EXIT MASK = Device is in Active Mode
10. Set ENDRV pin level. ENDRV reports a high level at pin ENDRV.
Figure 5-6. Set ENDRV and Read Back Pin Level ENDRV
Now the device is in active mode and the ENDRV signal enables the power stages in a real safety
application.
For details regarding the flags and register setting, please refer to the data sheet (SLVSBC4).
13
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Q1
R14 R13
C16
C6
C5
C4
D1
C2
C17
C9
L1
C12
R15
C3
J5
J3
CON2
CON1
J4
C8
C1
C7
J1
C14
C15
TP14
TP15
TP16
TP17
TP13
TP12
TP3 TP4 TP5 TP6
TP7
TP2
TP8 TP9
TP10
TP11
TP21
TP20
TP19
TP22
TP1
R2 R4 R5 R6 R7 R9
R10
R19
C18
C13
CON3
J2
R18
R1
J6
TP23 TP24 TP25 TP26
R3
IC1
C10
TP18
IC1
R12
R11
R8
R17
C11
R16
Chapter 6
SLVU847–April 2013
EVM Schematic
Figure 6-1. TPS65381EVM Schematic
14 EVM Schematic SLVU847–April 2013
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Chapter 7
SLVU847–April 2013
Board Picture
7.1 Top
Figure 7-1. EVM Top View
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SLVU847–April 2013 Board Picture
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7.2 Bottom
Figure 7-2. EVM Bottom View
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Chapter 8
SLVU847–April 2013
Board Assembly
Figure 6-1 shows the EVM schematic. Figure 7-1 and Figure 7-2 show photos of the EVM. Figure 8-1 and
Figure 8-2 show the board assembly layers. The EVM offers resistors, capacitors and jumpers to operate
the TPS65381-Q1 device.
The TPS65381-Q1 converter offers high efficiency, but does dissipate power. The PowerPAD™ package
offers an exposed thermal pad to enhance thermal performance which must be soldered to the copper
landing on the PCB for optimal performance. The PCB provides 2 oz. copper planes on the top and
bottom to dissipate heat.
Figure 8-1. Top Assembly Layer
17
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Figure 8-2. Bottom Assembly Layer
18 Board Assembly SLVU847–April 2013
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Chapter 9
SLVU847–April 2013
Board Layout
Figure 9-1 through Figure 9-4 show the board layout.
Figure 9-1. Top Layer Routing
Figure 9-2. Layer 2 (AGND) Routing
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Figure 9-3. Layer 3 Routing
Figure 9-4. Layer 4 Routing
20 Board Layout SLVU847–April 2013
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