
Application Note
Hardware Design Guide for AM62A7/AM62A3 Devices
ABSTRACT
This hardware design guide gives an overview of the design considerations to be followed by the board
designers using AM62A7/AM62A3 family of processors. This application note is intended to be used at different
stages of board design as a guide by the designers. The hardware design guide additionally references to
collaterals (device-specific and common) that could help the designers to optimize the efforts during the board
design.
Table of Contents
1 Introduction.............................................................................................................................................................................2
1.1 Before Getting Started....................................................................................................................................................... 2
1.2 Device (Processor) Selection.............................................................................................................................................2
1.3 Technical Documentation................................................................................................................................................... 3
1.4 Design Documentation.......................................................................................................................................................3
2 System Block Diagram...........................................................................................................................................................3
2.1 Creating the System Block Diagram.................................................................................................................................. 3
2.2 Selecting the Boot Mode.................................................................................................................................................... 3
2.3 Confirming Pin Multiplexing Compatibility.......................................................................................................................... 4
3 Power Supply.......................................................................................................................................................................... 4
3.1 Power Supply Architecture.................................................................................................................................................4
3.2 Power (Supply) Rails..........................................................................................................................................................4
3.3 Determining System Power Requirements........................................................................................................................ 6
3.4 Power Supply Filters.......................................................................................................................................................... 6
3.5 Power Supply Decoupling and Bulk Capacitors.................................................................................................................6
3.6 Power Supply Sequencing................................................................................................................................................. 6
3.7 Supply Diagnostics.............................................................................................................................................................6
3.8 Power Supply Monitoring................................................................................................................................................... 7
4 Clocking...................................................................................................................................................................................7
4.1 System Clock Inputs.......................................................................................................................................................... 7
4.2 Unused Clock Inputs.......................................................................................................................................................... 7
4.3 Clock Output...................................................................................................................................................................... 7
4.4 Single-Ended Clock Sources............................................................................................................................................. 7
4.5 Crystal Selection................................................................................................................................................................ 7
5 JTAG.........................................................................................................................................................................................7
5.1 JTAG / Emulation............................................................................................................................................................... 8
6 Device Configurations and Initialization...............................................................................................................................8
6.1 Device Reset......................................................................................................................................................................8
6.2 Latching of the Boot Modes............................................................................................................................................... 9
6.3 Watchdog Timer................................................................................................................................................................. 9
7 Peripherals.............................................................................................................................................................................. 9
7.1 Selecting Peripherals Across Functional Domains............................................................................................................ 9
7.2 Memory.............................................................................................................................................................................. 9
7.3 Media and Data Storage Interfaces................................................................................................................................. 10
7.4 Ethernet Interface Using CPSW3G Common Platform Switch 3-port Gigabit Ethernet...................................................10
7.5 Programmable Real-Time Unit Subsystem (PRUSS)...................................................................................................... 10
7.6 Universal Serial Bus (USB) Subsystem........................................................................................................................... 10
7.7 General Connectivity........................................................................................................................................................10
7.8 Display Subsystem (DSS)................................................................................................................................................ 11
7.9 Camera Subsystem (CSI).................................................................................................................................................11
7.10 Termination of Unused Peripherals and I/Os..................................................................................................................11
8 I/O Buffers and Termination................................................................................................................................................. 11
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SPRAD85 – MARCH 2023
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Hardware Design Guide for AM62A7/AM62A3 Devices 1
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