Texas Instruments TMS320C6000 DSP User manual

TMS320C6000 DSP
Designing for JTAG Emulation
Reference Guide
Literature Number: SPRU641
July 2003

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27
Designing for JTAG EmulationSPRU641
Preface
Read This First
About This Manual
This document assists you in meeting the design requirements of the
XDS510emulator with respect to JTAG designs and discusses the XDS510
cable (manufacturing part number 2617698-0001). This cable is identified by
a label on the cable pod marked JTAG 3/5 V and supports both standard 3-volt
and 5-volt target system power inputs.
The term JTAG as used in this document refers to Texas Instruments scan-
based emulation, which is based on the IEEE 1149.1 standard.
Notational Conventions
This document uses the following conventions.
-Hexadecimal numbers are shown with the suffix h. For example, the
following number is 40 hexadecimal (decimal 64): 40h.
Related Documentation From Texas Instruments
The following documents describe the C6000devices and related support
tools. Copies of these documents are available on the Internet at www.ti.com.
Tip: Enter the literature number in the search box provided at www.ti.com.
TMS320C6000 CPU and Instruction Set Reference Guide (literature
number SPRU189) describes the TMS320C6000CPU architecture,
instruction set, pipeline, and interrupts for these digital signal processors.
TMS320C6000 Peripherals Reference Guide (literature number SPRU190)
describes the peripherals available on the TMS320C6000DSPs.
TMS320C6000 Technical Brief (literature number SPRU197) gives an
introduction to the TMS320C62xand TMS320C67xDSPs, develop-
ment tools, and third-party support.
TMS320C64x Technical Overview (SPRU395) gives an introduction to the
TMS320C64xDSP and discusses the application areas that are
enhanced by the TMS320C64x VelociTI.

Trademarks
28 Designing for JTAG Emulation SPRU641
TMS320C6000 Programmer’s Guide (literature number SPRU198)
describes ways to optimize C and assembly code for the
TMS320C6000DSPs and includes application program examples.
TMS320C6000 Code Composer Studio Tutorial (literature number
SPRU301) introduces the Code Composer Studiointegrated develop-
ment environment and software tools.
Code Composer Studio Application Programming Interface Reference
Guide (literature number SPRU321) describes the Code Composer
Studioapplication programming interface (API), which allows you to
program custom plug-ins for Code Composer.
TMS320C6x Peripheral Support Library Programmer’s Reference
(literature number SPRU273) describes the contents of the
TMS320C6000peripheral support library of functions and macros. It
lists functions and macros both by header file and alphabetically,
provides a complete description of each, and gives code examples to
show how they are used.
TMS320C6000 Chip Support Library API Reference Guide (literature
number SPRU401) describes a set of application programming interfaces
(APIs) used to configure and control the on-chip peripherals.
Trademarks
Code Composer Studio, C6000, C62x, C64x, C67x, TMS320C6000,
TMS320C62x, TMS320C64x, TMS320C67x, VelociTI, and XDS510 are
trademarks of Texas Instruments.
PALis a registered trademark of Advanced Micro Devices, Inc.
Related Documentation From Texas Instruments / Trademarks

Contents
29
Designing for JTAG EmulationSPRU641
Contents
1 Designing Your Target System’s Emulator Connector (14-Pin Header) 7. . . . . . . . . . . . . . . . .
2 Bus Protocol 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 IEEE 1149.1 Standard 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 JTAG Emulator Cable Pod Logic 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 JTAG Emulator Cable Pod Signal Timing 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 Emulation Timing Calculations 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7 Connections Between the Emulator and the Target System 14. . . . . . . . . . . . . . . . . . . . . . . . . .
7.1 Buffering Signals 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2 Using a Target-System Clock 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3 Configuring Multiple Processors 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8 Mechanical Dimensions for the 14-Pin Emulator Connector 18. . . . . . . . . . . . . . . . . . . . . . . . .
9 Emulation Design Considerations 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.1 Using Scan Path Linkers 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.2 Emulation Timing Calculations for SPL 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.3 Using Emulation Pins 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4 Performing Diagnostic Applications 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figures
30 Designing for JTAG Emulation SPRU641
Figures
1 14-Pin Header Signals and Header Dimensions 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 JTAG Emulator Cable Pod Interface 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 JTAG Emulator Cable Pod Timing Diagram 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Target-System-Generated Test Clock 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Multiprocessor Connections 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 Pod/Connector Dimensions 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7 14-Pin Connector Dimensions 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8 Connecting a Secondary JTAG Scan Path to an SPL 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9 EMU0/1 Configuration 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10 EMU0/1 Configuration With Additional AND Gate to Meet Timing Requirements 27. . . . . . . .
11 Suggested Timings for the EMU0 and EMU1 Signals 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12 EMU0/1 Configuration Without Global Stop 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13 TBC Emulation Connections for n JTAG Scan Paths 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tables
1 14-Pin Header Signal Descriptions 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Emulator Cable Pod Timing Parameters 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3
Designing for JTAG EmulationSPRU641
Designing for JTAG Emulation
This document assists you in meeting the design requirements of the
XDS510emulator with respect to JTAG designs and discusses the XDS510
cable (manufacturing part number 2617698-0001). This cable is identified by
a label on the cable pod marked JTAG 3/5 V and supports both standard 3-volt
and 5-volt target system power inputs.
The term JTAG as used in this document refers to Texas Instruments scan-
based emulation, which is based on the IEEE 1149.1 standard.
1 Designing Your Target System’s Emulator Connector (14-Pin Header)
JTAG target devices support emulation through a dedicated emulation port.
This port is a superset of the IEEE 1149.1 standard and is accessed by the
emulator. To communicate with the emulator, your target system must have
a 14-pin header (two rows of seven pins) with the connections that are shown
in Figure 1. Table 1 describes the emulation signals.
Figure 1. 14-Pin Header Signals and Header Dimensions
TDO 7 8 GND
TMS 1 2 TRST
TDI 3 4 GND
TCK_RET 9 10 GND
TCK 11 12 GND
Header Dimensions:
Pin-to-pin spacing, 0.100 in. (X,Y
)
Pin width, 0.025-in. square post
Pin length, 0.235-in. nominal
PD (VCC)5 6no pin (key)†
EMU0 13 14 EMU1
†While the corresponding female position on the cable connector is plugged to prevent improper connection, the cable lead for
pin 6 is present in the cable and is grounded, as shown in the schematics and wiring diagrams in this document.

Designing Your Target System’s Emulator Connector (14-Pin Header)
Designing for JTAG Emulation
4SPRU641
Table 1. 14-Pin Header Signal Descriptions
Signal Description Emulator† State Target† State
TMS Test mode select O I
TDI Test data input O I
TDO Test data output I O
TCK Test clock. TCK is a 10.368-MHz clock source from the emulation cable
pod. This signal can be used to drive the system test clock OI
TRST‡Test reset O I
EMU0 Emulation pin 0 I I/O
EMU1 Emulation pin 1 I I/O
PD(VCC) Presence detect. Indicates that the emulation cable is connected and
that the target is powered up. PD should be tied to VCC in the target sys-
tem.
IO
TCK_RET Test clock return. Test clock input to the emulator. May be a buffered or
unbuffered version of TCK. IO
GND Ground
†I = input; O = output
‡Do not use pullup resistors on TRST: it has an internal pulldown device. In a low-noise environment, TRST can be left floating.
In a high-noise environment, an additional pulldown resistor may be needed. (The size of this resistor should be based on
electrical current considerations.)
Although you can use other headers, recommended parts include:
straight header, unshrouded DuPont Connector Systems
part numbers: 65610−114
65611−114
67996−114
67997−114

Designing Your Target System’s Emulator Connector (14-Pin Header)
5
Designing for JTAG EmulationSPRU641
2 Bus Protocol
The IEEE 1149.1 specification covers the requirements for the test access port
(TAP) bus slave devices and provides certain rules, summarized as follows:
-The TMS/TDI inputs are sampled on the rising edge of the TCK signal of
the device.
-The TDO output is clocked from the falling edge of the TCK signal of the
device.
When these devices are daisy-chained together, the TDO of one device has
approximately a half TCK cycle setup to the next device’s TDI signal. This type
of timing scheme minimizes race conditions that would occur if both TDO and
TDI were timed from the same TCK edge. The penalty for this timing scheme
is a reduced TCK frequency.
The IEEE 1149.1 specification does not provide rules for bus master (emula-
tor) devices. Instead, it states that it expects a bus master to provide bus slave
compatible timings. The XDS510 provides timings that meet the bus slave
rules.
3 IEEE 1149.1 Standard
For more information concerning the IEEE 1149.1 standard, contact IEEE
Customer Service:
Address:
IEEE Customer Service
445 Hoes Lane, PO Box 1331
Piscataway, NJ 08855-1331
Phone:
in the US and Canada: (800) 678−IEEE
outside the US and Canada: (908) 981−1393
FAX: (908) 981−9667
Telex: 833233
Bus Protocol / IEEE 1149.1 Standard

JTAG Emulator Cable Pod Logic
Designing for JTAG Emulation
6SPRU641
4 JTAG Emulator Cable Pod Logic
Figure 2 shows a portion of the emulator cable pod. These are the functional
features of the pod:
-Signals TDO and TCK_RET can be parallel-terminated inside the pod if
required by the application. By default, these signals are not terminated.
-Signal TCK is driven with a 74LVT240 device. Because of the high-current
drive (32 mA IOL/IOH), this signal can be parallel-terminated. If TCK is tied
to TCK_RET, then you can use the parallel terminator in the pod.
-Signals TMS and TDI can be generated from the falling edge of TCK_RET,
according to the IEEE 1149.1 bus slave device timing rules.
-Signals TMS and TDI are series-terminated to reduce signal reflections.
-A 10.368-MHz test clock source is provided. You may also provide your
own test clock for greater flexibility.
Figure 2. JTAG Emulator Cable Pod Interface
100 Ω
TL7705A
RESIN
270 Ω
JP2
180 Ω
TCK_RET (Pin 9){
EMU1 (Pin 14)
EMU0 (Pin 13) 74AS1034
GND (Pins 4,6,8,10,12)
TRST (Pin 2)
TCK (Pin 11){
10.368 MHz
33 Ω
33 Ω
TDI (Pin 3)
TMS (Pin 1)
TDO (Pin 7)
74LVT240
180 Ω
JP1
270 Ω74F175
Q
Q
D
PD(VCC) (Pin 5)
+5 V
+5 V
74AS1004
Y
Y
Y
Y
A
†The emulator pod uses TCK_RET as its clock source for internal synchronization. TCK is provided as an optional target system
test clock source.

JTAG Emulator Cable Pod Signal Timing
7
Designing for JTAG EmulationSPRU641
5 JTAG Emulator Cable Pod Signal Timing
Figure 3 shows the signal timings for the emulator cable pod. Table 2 defines
the timing parameters. These timing parameters are calculated from values
specified in the standard data sheets for the emulator and cable pod and are
for reference only. Texas Instruments does not test or guarantee these timings.
The emulator pod uses TCK_RET as its clock source for internal synchroni-
zation. TCK is provided as an optional target system test clock source.
Figure 3. JTAG Emulator Cable Pod Timing Diagram
TDO
TMS/TDI
TCK_RET
6
5
4
3
2
1
1.5 V
Table 2. Emulator Cable Pod Timing Parameters
No. Reference Description Min Max Units
1 tc(TCK) TCK_RET period 35 200 ns
2t
w(TCKH) TCK_RET high-pulse duration 15 ns
3t
w(TCKL) TCK_RET low-pulse duration 15 ns
4t
d(TMS) Delay time, TMS/TDI valid from TCK_RET low 6 20 ns
5t
su(TDO) TDO setup time to TCK_RET high 3 ns
6th(TDO) TDO hold time from TCK_RET high 12 ns

Emulation Timing Calculations
Designing for JTAG Emulation
8SPRU641
6 Emulation Timing Calculations
The following examples help you calculate emulation timings in your system.
For actual target timing parameters, see the appropriate device data sheets.
Assumptions:
tsu(TTMS) Target TMS/TDI setup to TCK high 10 ns
td(TTDO) Target TDO delay from TCK low 15 ns
td(bufmax) Target buffer delay, maximum 10 ns
td(bufmin) Target buffer delay, minimum 1 ns
t(bufskew) Target buffer skew between two devices
in the same package:
[td(bufmax) − td(bufmin)] ×0.15
1.35 ns
t(TCKfactor) Assume a 40/60 duty cycle clock 0.4
(40%)
Given in Table 2 (on page 7):
td(TMSmax) Emulator TMS/TDI delay from TCK_RET
low, maximum 20 ns
tsu(TDOmin) TDO setup time to emulator TCK_RET
high, minimum 3 ns
There are two key timing paths to consider in the emulation design:
-The TCK_RET-to-TMS/TDI path, called tpd(TCK_RET−TMS/TDI), and
-The TCK_RET-to-TDO path, called tpd(TCK_RET−TDO).
Of the following two cases, the worst-case path delay is calculated to deter-
mine the maximum system test clock frequency.
Case 1: Single processor, direct connection, TMS/TDI timed from TCK_RET low.
tpdǒTCK_RET–TMSńTDIǓ+ƪtdǒTMSmaxǓ)tsuǒTTMSǓƫ
tǒTCKfactorǓ
+[20ns )10ns]
0.4
+75ns (13.3 MHz)
tpdǒTCK_RET–TDOǓ+ƪtdǒTTDOǓ)tsu ǒTDOminǓƫ
tǒTCKfactorǓ
+[15ns )3ns]
0.4
+45ns (22.2 MHz)
In this case, the TCK_RET-to-TMS/TDI path is the limiting factor.

Emulation Timing Calculations
9
Designing for JTAG EmulationSPRU641
Case 2: Single/multiprocessor, TMS/TDI/TCK buffered input, TDO buffered output,
TMS/TDI timed from TCK_RET low.
tpd(TCK_RET–TMSńTDI) +
ƪ
td(TMSmax))tsu(TTMS))t(bufskew)
ƫ
tǒTCKfactorǓ
+ƪ20ns )10ns )1.35nsƫ
0.4
+78.4ns (12.7 MHz)
tpd(TCK_RET–TDO) +ƪtd(TTDO))tsu (TDOmin) )td (bufmax)ƫ
tǒTCKfactorǓ
+70ns (14.3 MHz)
+[15ns )3ns )10ns]
0.4
In this case, the TCK_RET-to-TMS/TDI path is the limiting factor.
In a multiprocessor application, it is necessary to ensure that the EMU0−1 lines
can go from a logic low level to a logic high level in less than 10 µs. This can be
calculated as follows:
tr= 5(Rpullup ×Ndevices ×Cload_per_device)
= 5(4.7 kW×16 ×15 pF)
= 5.64 µs
Refer to the device datasheet for the actual Rpullup value.

Connections Between the Emulator and the Target System
Designing for JTAG Emulation
10 SPRU641
7 Connections Between the Emulator and the Target System
It is extremely important to provide high-quality signals between the emulator
and the JTAG target system. Depending upon the situation, you must supply
the correct signal buffering, test clock inputs, and multiple processor intercon-
nections to ensure proper emulator and target system operation.
Signals applied to the EMU0 and EMU1 pins on the JTAG target device can
be either input or output (I/O). In general, these two pins are used as both input
and output in multiprocessor systems to handle global run/stop operations.
EMU0 and EMU1 signals are applied only as inputs to the XDS510 emulator
header.
7.1 Buffering Signals
If the distance between the emulation header and the JTAG target device is
greater than 6 inches, the emulation signals must be buffered. If the distance
is less than 6 inches, no buffering is necessary. The following illustrations
depict these two situations.
-No signal buffering. In this situation, the distance between the header
and the JTAG target device should be no more than 6 inches.
VCC
Emulator Header VCC
GND
12
10
8
6
4
5
GND
GND
GND
GND
GND
PD
TCK_RET
TCK
TDO
TDI
TMS
TRST
EMU1
EMU0
9
11
7
3
1
2
14
13
JTAG Device
TCK
TDO
TDI
TMS
TRST
EMU1
EMU0
6 Inches or Less
The EMU0 and EMU1 signals must have pullup resistors connected toVCC to
provide a signal rise time of less than 10 µs. Refer to the device datasheet for
the recommended resistor value.

Connections Between the Emulator and the Target System
11
Designing for JTAG EmulationSPRU641
-Buffered transmission signals. In this situation, the distance between
the emulation header and the processor is greater than 6 inches. Emula-
tion signals TMS, TDI, TDO, and TCK_RET are buffered through the same
package.
VCC
Emulator Header VCC
GND
12
10
8
6
4
5
GND
GND
GND
GND
GND
PD
TCK_RET
TCK
TDO
TDI
TMS
TRST
EMU1
EMU0
9
11
7
3
1
2
14
13
JTAG Device
TCK
TDO
TDI
TMS
TRST
EMU1
EMU0
Greater Than
6 Inches
JThe EMU0 and EMU1 signals must have pullup resistors connected to
VCC to provide a signal rise time of less than 10 µs. Refer to the device
datasheet for the recommended resistor value.
JThe input buffers for TMS and TDI should have pullup resistors con-
nected toVCC to hold these signals at a known value when the emula-
tor is not connected. Refer to the device datasheet for the recom-
mended resistor value.
JTo have high-quality signals (especially the processor TCK and the
emulator TCK_RET signals), you may have to employ special care
when routing the PWB trace. You also may have to use termination
resistors to match the trace impedance. The emulator pod provides
optional internal parallel terminators on the TCK_RET and TDO. TMS
and TDI provide fixed series termination.
JSince TRST is an asynchronous signal, it should be buffered as
needed to insure sufficient current to all target devices.

Connections Between the Emulator and the Target System
Designing for JTAG Emulation
12 SPRU641
7.2 Using a Target-System Clock
Figure 4 shows an application with the system test clock generated in the
target system. In this application, the TCK signal is left unconnected.
Figure 4. Target-System-Generated Test Clock
NC
System Test Clock
VCC
Emulator Header
GND
12
10
8
6
4
5
GND
GND
GND
GND
GND
PD
TCK_RET
TCK
TDO
TDI
TMS
TRST
EMU1
EMU0
9
11
7
3
1
2
14
13
JTAG Device
TCK
TDO
TDI
TMS
TRST
EMU1
EMU0
Greater Than
6 Inches
VCC
Note: When the TMS/TDI lines are buffered, pullup resistors should be used to hold the buffer inputs at a known level when the
emulator cable is not connected.
There are two benefits to having the target system generate the test clock:
-The emulator provides only a single 10.368-MHz test clock. If you allow
the target system to generate your test clock, you can set the frequency
to match your system requirements.
-In some cases, you may have other devices in your system that require
a test clock when the emulator is not connected. The system test clock
also serves this purpose.

Connections Between the Emulator and the Target System
13
Designing for JTAG EmulationSPRU641
7.3 Configuring Multiple Processors
Figure 5 shows a typical daisy-chained multiprocessor configuration, which
meets the minimum requirements of the IEEE 1149.1 specification. The emu-
lation signals in this example are buffered to isolate the processors from the
emulator and provide adequate signal drive for the target system. One of the
benefits of this type of interface is that you can generally slow down the test
clock to eliminate timing problems. You should follow these guidelines for
multiprocessor support:
-The processor TMS, TDI, TDO, and TCK signals should be buffered
through the same physical package for better control of timing skew.
-The input buffers for TMS, TDI, and TCK should have pullup resistors con-
nected to VCC to hold these signals at a known value when the emulator
is not connected. Refer to the device datasheet for the recommended re-
sistor value.
-Buffering EMU0 and EMU1 is optional but highly recommended to provide
isolation. These are not critical signals and do not have to be buffered
through the same physical package as TMS, TCK, TDI, and TDO. Unbuf-
fered and buffered signals are shown in section 7.1.
Figure 5. Multiprocessor Connections
TDITDI TDOTDO
JTAG DeviceJTAG Device
VCC
Emulator Header
GND
12
10
8
6
4
5
GND
GND
GND
GND
GND
PD
TCK_RET
TCK
TDO
TDI
TMS
TRST
EMU1
EMU0
9
11
7
3
1
2
14
13
TMS
TCK
TRST
EMU0 EMU1
TMS
TCK
TRST
EMU0 EMU1
VCC

Mechanical Dimensions for the 14-Pin Emulator Connector
Designing for JTAG Emulation
14 SPRU641
8 Mechanical Dimensions for the 14-Pin Emulator Connector
The JTAG emulator target cable consists of a 3-foot section of jacketed cable,
an active cable pod, and a short section of jacketed cable that connects to the
target system. The overall cable length is approximately 3 feet 10 inches.
Figure 6 and Figure 7 show the mechanical dimensions for the target cable
pod and short cable. Note that the pin-to-pin spacing on the connector is
0.100 inches in both the X and Y planes. The cable pod box is nonconductive
plastic with four recessed metal screws.
Figure 6. Pod/Connector Dimensions
0.90
2.70
4.50
9.50
Refer to Figure 7.
Emulator Cable Pod
Short, Jacketed Cable
Connector
Note: All dimensions are in inches and are nominal dimensions, unless otherwise specified.

Mechanical Dimensions for the 14-Pin Emulator Connector
15
Designing for JTAG EmulationSPRU641
Figure 7. 14-Pin Connector Dimensions
0.100 Key, Pin 6
0.100
0.87
0.66
0.20
Pins 2, 4, 6, 8, 10, 12, 14
Pins 1, 3, 5, 7, 9, 11, 13
Cable
Connector, Side View
Connector, Front View
Cable
Note: All dimensions are in inches and are nominal dimensions, unless otherwise specified.

Emulation Design Considerations
Designing for JTAG Emulation
16 SPRU641
9 Emulation Design Considerations
This section describes the use and application of the scan path linker (SPL),
which can simultaneously add all four secondary JTAG scan paths to the main
scan path. It also describes the use of the emulation pins and the configuration
of multiple processors.
9.1 Using Scan Path Linkers
You can use the TI ACT8997 scan path linker (SPL) to divide the JTAG emula-
tion scan path into smaller, logically connected groups of 4 to 16 devices. As
described in theAdvanced Logic and Bus Interface Logic Data Book (literature
number SCYD001), the SPL is compatible with the JTAG emulation scanning.
The SPL is capable of adding any combination of its four secondary scan paths
into the main scan path.
A system of multiple, secondary JTAG scan paths has better fault tolerance
and isolation than a single scan path. Since an SPL has the capability of adding
all secondary scan paths to the main scan path simultaneously, it can support
global emulation operations, such as starting or stopping a selected group of
processors.
TI emulators do not support the nesting of SPLs (for example, an SPL
connected to the secondary scan path of another SPL). However, you can
have multiple SPLs on the main scan path.
Although the ACT8999 scan path selector is similar to the SPL, it can add only
one of its secondary scan paths at a time to the main JTAG scan path. Thus,
global emulation operations are not assured with the scan path selector. For
this reason, scan path selectors are not supported.
You can insert an SPL on a backplane so that you can add up to four device
boards to the system without the jumper wiring required with nonbackplane
devices. You connect an SPL to the main JTAG scan path in the same way you
connect any other device. Figure 8 shows you how to connect a secondary
scan path to an SPL.