Texas Instruments Concerto F28M35 Series Product manual

Concerto F28M35x
Technical Reference Manual
Literature Number: SPRUH22I
April 2012–Revised November 2019

2SPRUH22I–April 2012–Revised November 2019
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Contents
Contents
Preface....................................................................................................................................... 78
1 System Control and Interrupts............................................................................................. 79
1.1 Signal Description.......................................................................................................... 80
1.2 System Control Functional Description.................................................................................. 81
1.2.1 Device Identification............................................................................................... 81
1.2.2 Device Configuration Registers ................................................................................. 82
1.3 Reset Control ............................................................................................................... 82
1.3.1 Device Level Reset Sources..................................................................................... 82
1.3.2 Handling of Resets at System Level............................................................................ 89
1.4 WIR Mode................................................................................................................... 92
1.4.1 Entering WIR Mode ............................................................................................... 93
1.4.2 Exiting WIR Mode................................................................................................. 94
1.5 Exceptions and Interrupts Control........................................................................................ 95
1.5.1 Master Subsystem Nested Vectored Interrupt Controller.................................................... 95
1.5.2 Master Subsystem Exceptions Handling....................................................................... 96
1.5.3 Master Subsystem Non-Maskable Interrupt (MNMI) Module................................................ 97
1.5.4 Control Subsystem PIE ......................................................................................... 100
1.5.5 Control Subsystem Exceptions Handling..................................................................... 116
1.5.6 Control Subsystem NMI (CNMI) Module...................................................................... 116
1.6 Safety Features ........................................................................................................... 119
1.6.1 Write Protection on Registers.................................................................................. 119
1.6.2 Missing Clock Detection Logic ................................................................................. 120
1.6.3 PLLSLIP Detection .............................................................................................. 123
1.6.4 Control Subsystem PIE Vector Address Validity Check.................................................... 123
1.6.5 NMIWDs .......................................................................................................... 124
1.6.6 Watchdog Timers................................................................................................ 124
1.6.7 ECC and Parity Enabled RAMs, Shared RAMs Protection ................................................ 124
1.6.8 ECC Enabled Flash Memory................................................................................... 125
1.7 Power Control ............................................................................................................. 125
1.8 Clock Control.............................................................................................................. 125
1.8.1 Clock Sources.................................................................................................... 126
1.8.2 PLLs ............................................................................................................... 126
1.8.3 Master Subsystem Clocking.................................................................................... 127
1.8.4 Control Subsystem Clocking ................................................................................... 130
1.8.5 Clocking Control Semaphore Functionality................................................................... 134
1.8.6 ACIB and Analog Peripherals Clocking....................................................................... 135
1.8.7 Configuring XCLKOUT.......................................................................................... 135
1.8.8 32-Bit CPU Timers 0/1/2........................................................................................ 136
1.9 Low Power Modes........................................................................................................ 140
1.9.1 Low-Power Modes............................................................................................... 140
1.10 Code Security Module (CSM)........................................................................................... 144
1.10.1 Functional Description ......................................................................................... 144
1.10.2 CSM Impact on Other On-Chip Resources ................................................................. 147
1.10.3 Incorporating Code Security in User Applications.......................................................... 147
1.10.4 Do's and Don'ts to Protect Security Logic................................................................... 155

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1.11 µCRC Module ............................................................................................................. 155
1.11.1 Functional Description ......................................................................................... 155
1.11.2 CRC Polynomials............................................................................................... 156
1.11.3 CRC Calculation Procedure................................................................................... 156
1.11.4 CRC Calculation For Data Stored In Secure Memory ..................................................... 156
1.12 Inter Processor Communications (IPC)................................................................................ 156
1.12.1 MSGRAMs....................................................................................................... 157
1.12.2 IPC Flags and Interrupts....................................................................................... 157
1.12.3 MTOCIPC Communication ................................................................................... 158
1.12.4 CTOMIPC Communication .................................................................................... 159
1.12.5 Examples for Software IPC Procedure ...................................................................... 160
1.12.6 IPC Message Registers........................................................................................ 160
1.12.7 Flash Pump Semaphore....................................................................................... 161
1.12.8 Clock Configuration Semaphore.............................................................................. 162
1.12.9 Free Running Counter ......................................................................................... 164
1.13 System Control Registers................................................................................................ 165
1.13.1 System Control, Configuration Register Map ............................................................... 165
1.13.2 Device Identification and Device Configuration............................................................. 173
1.13.3 Reset Control and Status Registers.......................................................................... 188
1.13.4 WIRMODE Registers........................................................................................... 197
1.13.5 Exception and Interrupts....................................................................................... 198
1.13.6 Safety Control Registers....................................................................................... 218
1.13.7 Clocking Control Registers .................................................................................... 222
1.13.8 Master Subsystem Code Security Module (CSM) Registers.............................................. 248
1.13.9 Control Subsystem Code Security Module (CSM) Registers............................................. 264
1.13.10 µCRC Register Description .................................................................................. 268
1.13.11 Master Subsystem IPC Registers........................................................................... 270
1.13.12 Control Subsystem IPC Registers .......................................................................... 281
1.13.13 Master and Control Subsystem IPC Registers............................................................ 293
2 M3 General-Purpose Timers............................................................................................... 298
2.1 GPTM Features........................................................................................................... 299
2.2 Block Diagram............................................................................................................. 299
2.3 Functional Description.................................................................................................... 300
2.3.1 GPTM Reset Conditions........................................................................................ 300
2.3.2 Timer Modes ..................................................................................................... 301
2.3.3 DMA Operation................................................................................................... 305
2.3.4 Accessing Concatenated Register Values ................................................................... 306
2.4 Initialization and Configuration.......................................................................................... 306
2.4.1 One-Shot/Periodic Timer Mode................................................................................ 306
2.4.2 Real-Time Clock (RTC) Mode.................................................................................. 307
2.4.3 Input Edge-Count Mode......................................................................................... 307
2.4.4 Input Edge Timing Mode........................................................................................ 307
2.4.5 16-Bit PWM Mode ............................................................................................... 308
2.5 Register Map .............................................................................................................. 308
2.6 Register Descriptions..................................................................................................... 309
2.6.1 GPTM Configuration (GPTMCFG) Register, offset 0x000 ................................................. 309
2.6.2 GPTM Timer A Mode (GPTMTAMR) Register, offset 0x004 .............................................. 309
2.6.3 GPTM Timer B Mode (GPTMTBMR) Register, offset 0x008 .............................................. 311
2.6.4 GPTM Control (GPTMCTL) Register, offset 0x00C......................................................... 312
2.6.5 GPTM Interrupt Mask (GPTMIMR) Register, offset 0x018................................................. 313
2.6.6 GPTM Raw Interrupt Status (GPTMRIS) Register, offset 0x01C ......................................... 314
2.6.7 GPTM Masked Interrupt Status (GPTMMIS) Register, offset 0x020...................................... 315
2.6.8 GPTM Interrupt Clear (GPTMICR) Register, offset 0x024 ................................................. 316

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2.6.9 GPTM Timer A Interval Load (GPTMTAILR) Register, offset 0x028 ..................................... 317
2.6.10 GPTM Timer B Interval Load (GPTMTBILR) Register, offset 0x02C.................................... 318
2.6.11 GPTM Timer A Match (GPTMTAMATCHR) Register, offset 0x030 ..................................... 318
2.6.12 GPTM Timer B Match (GPTMTBMATCHR) Register, offset 0x034 ..................................... 319
2.6.13 GPTM Timer A Prescale (GPTMTAPR) Register, offset 0x038.......................................... 319
2.6.14 GPTM Timer B Prescale (GPTMTBPR) Register, offset 0x03C.......................................... 320
2.6.15 GPTM Timer A Prescale Match (GPTMTAPMR) Register, offset 0x040................................ 320
2.6.16 GPTM Timer B Prescale Match (GPTMTBPMR) Register, offset 0x044................................ 320
2.6.17 GPTM Timer A (GPTMTAR) Register, offset 0x048 ....................................................... 321
2.6.18 GPTM Timer B (GPTMTBR) Register, offset 0x04C....................................................... 321
2.6.19 GPTM Timer A Value (GPTMTAV) Register, offset 0x050................................................ 322
2.6.20 GPTM Timer B Value (GPTMTBV) Register, offset 0x054................................................ 322
3 M3 Watchdog Timers ........................................................................................................ 324
3.1 Introduction ................................................................................................................ 325
3.1.1 Block Diagram.................................................................................................... 325
3.1.2 Functional Description........................................................................................... 326
3.1.3 Initialization and Configuration................................................................................. 326
3.2 Register Map .............................................................................................................. 326
3.3 Register Descriptions..................................................................................................... 327
3.3.1 Watchdog Load (WDTLOAD) Register, offset 0x000....................................................... 327
3.3.2 Watchdog Value (WDTVALUE) Register, offset 0x004..................................................... 328
3.3.3 Watchdog Control (WDTCTL) Register, offset 0x008....................................................... 329
3.3.4 Watchdog Interrupt Clear (WDTICR) Register, offset 0x00C.............................................. 329
3.3.5 Watchdog Raw Interrupt Status (WDTRIS) Register, offset 0x010 ....................................... 330
3.3.6 Watchdog Masked Interrupt Status (WDTMIS) Register, offset 0x014................................... 330
3.3.7 Watchdog Test (WDTTEST) Register, offset 0x418 ........................................................ 331
3.3.8 Watchdog Lock (WDTLOCK) Register, offset 0xC00....................................................... 331
3.3.9 Watchdog Peripheral Identification 4 (WDTPeriphID4) Register, offset 0xFD0 ......................... 332
3.3.10 Watchdog Peripheral Identification 5 (WDTPeriphID5) Register, offset 0xFD4 ........................ 332
3.3.11 Watchdog Peripheral Identification 6 (WDTPeriphID6) Register, offset 0xFD8 ........................ 332
3.3.12 Watchdog Peripheral Identification 7 (WDTPeriphID7) Register, offset 0xFDC........................ 333
3.3.13 Watchdog Peripheral Identification 0 (WDTPeriphID0) Register, offset 0xFE0 ........................ 333
3.3.14 Watchdog Peripheral Identification 1 (WDTPeriphID1) Register, offset 0xFE4 ........................ 333
3.3.15 Watchdog Peripheral Identification 2 (WDTPeriphID2) Register, offset 0xFE8 ........................ 334
3.3.16 Watchdog Peripheral Identification 3 (WDTPeriphID3) Register, offset 0xFEC........................ 334
3.3.17 Watchdog PrimeCell Identification 0 (WDTPCellID0) Register, offset 0xFF0 .......................... 334
3.3.18 Watchdog PrimeCell Identification 1 (WDTPCellID1) Register, offset 0xFF4 .......................... 335
3.3.19 Watchdog PrimeCell Identification 2 (WDTPCellID2) Register, offset 0xFF8 .......................... 335
3.3.20 Watchdog PrimeCell Identification 3 (WDTPCellID3) Register, offset 0xFFC.......................... 335
4 General-Purpose Input/Output (GPIO) ................................................................................. 336
4.1 General-Purpose Input/Output (GPIO)................................................................................. 337
4.1.1 Introduction ....................................................................................................... 337
4.1.2 Signal Description ............................................................................................... 337
4.1.3 Functional Description........................................................................................... 341
4.1.4 Initialization and Configuration................................................................................. 345
4.1.5 Register Map ..................................................................................................... 346
4.1.6 Register Descriptions............................................................................................ 348
4.2 C28 General-Purpose Input/Output (GPIO)........................................................................... 369
4.2.1 Introduction ....................................................................................................... 369
4.2.2 GPIO Module Overview......................................................................................... 369
4.2.3 Configuration Overview ......................................................................................... 375
4.2.4 Digital General Purpose I/O Control........................................................................... 378
4.2.5 Input Qualification................................................................................................ 380

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4.2.6 GPIO and Peripheral Multiplexing (MUX) .................................................................... 384
4.2.7 Register Bit Definitions.......................................................................................... 391
5 Internal Memory................................................................................................................ 425
5.1 RAM Control Module ..................................................................................................... 426
5.1.1 Functional Description........................................................................................... 426
5.2 RAM Control Module Registers......................................................................................... 434
5.2.1 M3 RAM Configuration Registers.............................................................................. 437
5.2.2 M3 RAM Error Registers........................................................................................ 452
5.2.3 C28x RAM Configuration Registers ........................................................................... 465
5.2.4 C28x RAM Error Registers ..................................................................................... 480
5.3 Flash Controller Memory Module....................................................................................... 493
5.3.1 Features........................................................................................................... 493
5.3.2 Flash Tools ....................................................................................................... 493
5.3.3 Default Flash Configuration .................................................................................... 494
5.3.4 Flash Bank, OTP and Pump ................................................................................... 494
5.3.5 Flash Module Controller (FMC)................................................................................ 495
5.3.6 Flash and OTP Automatic Power-Down Modes............................................................. 496
5.3.7 Flash and OTP Performance................................................................................... 497
5.3.8 Flash Read Interface ............................................................................................ 497
5.3.9 Erase/Program Flash............................................................................................ 502
5.3.10 Error Correction Code (ECC) Protection .................................................................... 503
5.3.11 Reserved Locations Within Flash and OTP................................................................. 506
5.3.12 Procedure to Change the Flash Control Registers......................................................... 507
5.4 Flash Registers ........................................................................................................... 508
5.4.1 Master Subsystem Flash Control Registers.................................................................. 512
5.4.2 Master Subsystem Flash ECC/Error Log Registers......................................................... 518
5.4.3 Control Subsystem Flash Control Registers ................................................................. 525
5.4.4 Control Subsystem Flash ECC/Error Log Registers ........................................................ 529
6 ROM Code and Peripheral Booting ..................................................................................... 536
6.1 Introduction ................................................................................................................ 537
6.2 Device Boot Sequence................................................................................................... 537
6.3 Device Boot Modes....................................................................................................... 538
6.3.1 Configuring Alternate Boot Mode Pins........................................................................ 538
6.4 Device Boot Flow Diagram .............................................................................................. 540
6.5 M-Boot ROM Description ................................................................................................ 541
6.5.1 M-Boot ROM Memory Map..................................................................................... 541
6.5.2 M-Boot ROM Vector Table ..................................................................................... 541
6.5.3 M-Boot ROM Version and Checksum Information .......................................................... 542
6.5.4 M-Boot ROM RAM Initialization................................................................................ 542
6.5.5 M-Boot ROM RAM Usage...................................................................................... 543
6.5.6 M-Boot ROM User OTP......................................................................................... 543
6.5.7 M-Boot ROM Entry Points...................................................................................... 544
6.5.8 M-Boot ROM Clock Initialization............................................................................... 546
6.5.9 M-Boot ROM GPIO Assignments for Each Boot Mode..................................................... 546
6.5.10 M-Boot ROM Functional Flow................................................................................. 547
6.5.11 M-Boot ROM Flow Diagram................................................................................... 549
6.5.12 M-Boot ROM Boot Status in RAM for Applications......................................................... 552
6.5.13 M-Boot ROM Reset Cause Handling ........................................................................ 553
6.5.14 M-Boot ROM Exceptions Handling........................................................................... 553
6.5.15 M-Boot ROM Boot Modes ..................................................................................... 554
6.6 C-Boot ROM Description ................................................................................................ 570
6.6.1 C-Boot ROM Memory Map ..................................................................................... 570
6.6.2 C-Boot ROM RAM Initialization................................................................................ 577

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6.6.3 C-Boot ROM RAM Usage ...................................................................................... 577
6.6.4 C-Boot ROM Boot Modes....................................................................................... 578
6.6.5 C-Boot ROM Entry Points ...................................................................................... 579
6.6.6 C-Boot ROM GPIO Assignment for Boot Modes............................................................ 580
6.6.7 C-Boot ROM Clock Initializations.............................................................................. 581
6.6.8 C-Boot ROM Functional Flow.................................................................................. 581
6.6.9 C-Boot ROM MTOC IPC Commands ......................................................................... 584
6.6.10 C-Boot ROM Health Status.................................................................................... 590
6.6.11 C-Boot ROM Boot Status...................................................................................... 591
6.6.12 C-Boot ROM CTOM IPC Messages.......................................................................... 592
6.6.13 C-Boot ROM Handling of Exceptions and PIE Interrupts.................................................. 593
6.6.14 C-Boot ROM Bootloader Functionality ...................................................................... 594
6.7 Guidelines for Boot ROM Application Writers......................................................................... 614
6.7.1 Master Subsystem Application Procedure to Start C-Boot ROM Bootloaders........................... 614
6.7.2 Master Subsystem Application Procedure to Initialize the Control Subsystem RAM Using IPC...... 616
6.8 Application Notes to Use Boot ROM ................................................................................... 619
6.8.1 How to Send Boot Data to M-Boot ROM ..................................................................... 619
6.8.2 C-Boot ROM: Building the Boot Table ........................................................................ 625
7 C28 Enhanced Pulse Width Modulator (ePWM) Module ......................................................... 630
7.1 Introduction ................................................................................................................ 631
7.1.1 Submodule Overview............................................................................................ 632
7.1.2 Register Mapping................................................................................................ 636
7.2 ePWM Submodules ...................................................................................................... 641
7.2.1 Overview.......................................................................................................... 641
7.2.2 Time-Base (TB) Submodule.................................................................................... 643
7.2.3 Counter-Compare (CC) Submodule........................................................................... 653
7.2.4 Action-Qualifier (AQ) Submodule.............................................................................. 660
7.2.5 Dead-Band Generator (DB) Submodule...................................................................... 676
7.2.6 PWM-Chopper (PC) Submodule............................................................................... 683
7.2.7 Trip-Zone (TZ) Submodule ..................................................................................... 687
7.2.8 Event-Trigger (ET) Submodule ................................................................................ 692
7.2.9 Digital Compare (DC) Submodule............................................................................. 699
7.3 Applications to Power Topologies ...................................................................................... 707
7.3.1 Overview of Multiple Modules ................................................................................. 707
7.3.2 Key Configuration Capabilities................................................................................. 707
7.3.3 Controlling Multiple Buck Converters With Independent Frequencies.................................... 708
7.3.4 Controlling Multiple Buck Converters With Same Frequencies............................................ 712
7.3.5 Controlling Multiple Half H-Bridge (HHB) Converters....................................................... 715
7.3.6 Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM).......................................... 717
7.3.7 Practical Applications Using Phase Control Between PWM Modules .................................... 721
7.3.8 Controlling a 3-Phase Interleaved DC/DC Converter....................................................... 722
7.3.9 Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter....................................... 726
7.3.10 Controlling a Peak Current Mode Controlled Buck Module ............................................... 728
7.3.11 Controlling H-Bridge LLC Resonant Converter............................................................. 730
7.4 Registers................................................................................................................... 733
7.4.1 Time-Base Submodule Registers.............................................................................. 733
7.4.2 Counter-Compare Submodule Registers..................................................................... 742
7.4.3 Action-Qualifier Submodule Registers ........................................................................ 749
7.4.4 Dead-Band Submodule Registers............................................................................. 754
7.4.5 PWM-Chopper Submodule Control Register................................................................. 758
7.4.6 Trip-Zone Submodule Control and Status Registers........................................................ 760
7.4.7 Digital Compare Submodule Registers ....................................................................... 767
7.4.8 GPTRIP Input Select Registers................................................................................ 778

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7.4.9 Event-Trigger Submodule Registers .......................................................................... 780
7.4.10 Proper Interrupt Initialization Procedure..................................................................... 789
8 C28 Enhanced Capture (eCAP) Module................................................................................ 790
8.1 Introduction ................................................................................................................ 791
8.2 Description................................................................................................................. 791
8.3 Capture and APWM Operating Mode.................................................................................. 792
8.4 Capture Mode Description............................................................................................... 793
8.4.1 Event Prescaler .................................................................................................. 794
8.4.2 Edge Polarity Select and Qualifier............................................................................. 795
8.4.3 Continuous/One-Shot Control.................................................................................. 795
8.4.4 32-Bit Counter and Phase Control............................................................................. 796
8.4.5 CAP1-CAP4 Registers.......................................................................................... 797
8.4.6 Interrupt Control.................................................................................................. 797
8.4.7 Shadow Load and Lockout Control............................................................................ 798
8.4.8 APWM Mode Operation......................................................................................... 799
8.5 Capture Module - Control and Status Registers...................................................................... 801
8.6 Register Mapping......................................................................................................... 809
8.7 Application of the ECAP Module ....................................................................................... 809
8.7.1 Example 1 - Absolute Time-Stamp Operation Rising Edge Trigger....................................... 810
8.7.2 Example 2 - Absolute Time-Stamp Operation Rising and Falling Edge Trigger ........................ 812
8.7.3 Example 3 - Time Difference (Delta) Operation Rising Edge Trigger..................................... 814
8.7.4 Example 4 - Time Difference (Delta) Operation Rising and Falling Edge Trigger ...................... 816
8.8 Application of the APWM Mode......................................................................................... 818
8.8.1 Example 1 - Simple PWM Generation (Independent Channel/s).......................................... 818
9 C28 Enhanced QEP (eQEP) Module..................................................................................... 820
9.1 Introduction ................................................................................................................ 821
9.2 Description................................................................................................................. 823
9.2.1 EQEP Inputs...................................................................................................... 823
9.2.2 Functional Description........................................................................................... 824
9.2.3 eQEP Memory Map ............................................................................................. 824
9.3 Quadrature Decoder Unit (QDU) ....................................................................................... 826
9.3.1 Position Counter Input Modes.................................................................................. 826
9.3.2 eQEP Input Polarity Selection.................................................................................. 829
9.3.3 Position-Compare Sync Output................................................................................ 829
9.4 Position Counter and Control Unit (PCCU)............................................................................ 829
9.4.1 Position Counter Operating Modes............................................................................ 829
9.4.2 Position Counter Latch.......................................................................................... 831
9.4.3 Position Counter Initialization .................................................................................. 833
9.4.4 eQEP Position-compare Unit................................................................................... 834
9.5 eQEP Edge Capture Unit................................................................................................ 835
9.6 eQEP Watchdog .......................................................................................................... 839
9.7 Unit Timer Base........................................................................................................... 839
9.8 eQEP Interrupt Structure ................................................................................................ 840
9.9 eQEP Registers........................................................................................................... 840
10 Analog Subsystem............................................................................................................ 854
10.1 Overview................................................................................................................... 855
10.2 Analog Common Interface Bus (ACIB) ................................................................................ 855
10.3 Analog-to-Digital Converter (ADC) ..................................................................................... 859
10.3.1 Features.......................................................................................................... 859
10.3.2 Block Diagram................................................................................................... 860
10.3.3 SOC Principle of Operation ................................................................................... 860
10.3.4 ONESHOT Single Conversion Support...................................................................... 864
10.3.5 ADC Conversion Priority....................................................................................... 865

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10.3.6 Simultaneous Sampling Mode ................................................................................ 868
10.3.7 EOC and Interrupt Operation.................................................................................. 868
10.3.8 Power Up Sequence ........................................................................................... 869
10.3.9 ADC Calibration................................................................................................. 869
10.3.10 Internal/External Reference Voltage Selection............................................................ 871
10.3.11 ADC Registers................................................................................................. 872
10.3.12 Analog Subsystem Control Registers ...................................................................... 889
10.3.13 ADC Timings................................................................................................... 898
10.4 Comparator Block......................................................................................................... 901
10.4.1 Features......................................................................................................... 901
10.4.2 Comparator Block Diagram.................................................................................... 902
10.4.3 Comparator Function........................................................................................... 902
10.4.4 DAC Reference ................................................................................................. 902
10.4.5 Initialization ...................................................................................................... 903
10.4.6 Digital Domain Manipulation .................................................................................. 903
10.4.7 Comparator Registers.......................................................................................... 904
10.5 Analog Subsystem Software ............................................................................................ 906
10.5.1 C28 Analog Subsystem Functions ........................................................................... 906
10.5.2 C28 Analog Subsystem Software Example ................................................................. 908
10.5.3 M3 Analog Subsystem Functions............................................................................. 908
10.5.4 M3 Analog Subsystem Software Example .................................................................. 909
11 C28 Direct Memory Access (DMA) Module .......................................................................... 911
11.1 Introduction ................................................................................................................ 912
11.2 Architecture................................................................................................................ 912
11.2.1 Block Diagram................................................................................................... 912
11.2.2 Peripheral Interrupt Event Trigger Sources ................................................................. 913
11.2.3 DMA Bus......................................................................................................... 915
11.3 Pipeline Timing and Throughput........................................................................................ 916
11.3.1 DMA Read Access of ADC Registers........................................................................ 917
11.4 CPU Arbitration ........................................................................................................... 917
11.4.1 Arbitration when Accessing the Analog Subsystem........................................................ 918
11.5 Channel Priority........................................................................................................... 918
11.5.1 Round-Robin Mode............................................................................................. 918
11.5.2 Channel 1 High Priority Mode................................................................................. 919
11.6 Address Pointer and Transfer Control ................................................................................. 920
11.7 Overrun Detection Feature .............................................................................................. 924
11.8 Register Descriptions..................................................................................................... 926
11.8.1 DMA Control Register (DMACTRL) — EALLOW Protected .............................................. 927
11.8.2 Debug Control Register (DEBUGCTRL) — EALLOW Protected......................................... 929
11.8.3 Revision Register (REVISION) ............................................................................... 929
11.8.4 Priority Control Register 1 (PRIORITYCTRL1) — EALLOW Protected ................................. 930
11.8.5 Priority Status Register (PRIORITYSTAT) .................................................................. 931
11.8.6 Mode Register (MODE) — EALLOW Protected............................................................ 932
11.8.7 Control Register (CONTROL) — EALLOW Protected..................................................... 934
11.8.8 Burst Size Register (BURST_SIZE) — EALLOW Protected.............................................. 936
11.8.9 BURST_COUNT Register ..................................................................................... 936
11.8.10 Source Burst Step Register Size (SRC_BURST_STEP) — EALLOW Protected .................... 937
11.8.11 Destination Burst Step Register Size (DST_BURST_STEP) — EALLOW Protected................ 938
11.8.12 Transfer Size Register (TRANSFER_SIZE) — EALLOW Protected ................................... 938
11.8.13 Transfer Count Register (TRANSFER_COUNT) ......................................................... 939
11.8.14 Source Transfer Step Size Register (SRC_TRANSFER_STEP) — EALLOW Protected ........... 939
11.8.15 Destination Transfer Step Size Register (DST_TRANSFER_STEP) — EALLOW Protected....... 940
11.8.16 Source/Destination Wrap Size Register (SRC/DST_WRAP_SIZE) — EALLOW protected)........ 940

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11.8.17 Source/Destination Wrap Count Register (SCR/DST_WRAP_COUNT) .............................. 941
11.8.18 Source/Destination Wrap Step Size Registers (SRC/DST_WRAP_STEP) — EALLOW Protected 941
11.8.19 Shadow Source Begin and Current Address Pointer Registers
(SRC_BEG_ADDR_SHADOW/DST_BEG_ADDR_SHADOW) — All EALLOW Protected............ 942
11.8.20 Active Source Begin and Current Address Pointer Registers
(SRC_BEG_ADDR/DST_BEG_ADDR)....................................................................... 942
11.8.21 Shadow Destination Begin and Current Address Pointer Registers
(SRC_ADDR_SHADOW/DST_ADDR_SHADOW) — All EALLOW Protected .......................... 943
11.8.22 Active Destination Begin and Current Address Pointer Registers (SRC_ADDR/DST_ADDR) ..... 943
12 C28 Serial Peripheral Interface (SPI).................................................................................... 944
12.1 Enhanced SPI Module Overview ....................................................................................... 945
12.1.1 SPI Block Diagram ............................................................................................. 946
12.1.2 SPI Module Signal Summary.................................................................................. 948
12.1.3 Overview of SPI Module Registers........................................................................... 948
12.1.4 SPI Operation ................................................................................................... 949
12.1.5 SPI Interrupts.................................................................................................... 951
12.1.6 SPI FIFO Description........................................................................................... 956
12.1.7 SPI 3-Wire Mode Description ................................................................................. 958
12.1.8 SPI STEINV Bit in Digital Audio Transfers .................................................................. 960
12.2 C28 SPI-A to M3 SSI3 Internal Loopback............................................................................. 961
12.2.1 Loopback Initialization and Configuration ................................................................... 962
12.3 SPI Registers and Waveforms.......................................................................................... 964
12.3.1 SPI Control Registers .......................................................................................... 964
12.3.2 SPI Example Waveforms...................................................................................... 973
13 C28 Serial Communications Interface (SCI).......................................................................... 979
13.1 Enhanced SCI Module Overview ....................................................................................... 980
13.1.1 Architecture...................................................................................................... 982
13.2 C28 SCI-A to M3 UART4 Internal Loopback.......................................................................... 992
13.2.1 Loopback Initialization and Configuration ................................................................... 993
13.3 SCI Registers.............................................................................................................. 994
13.3.1 SCI Module Register Summary............................................................................... 994
13.3.2 SCI Communication Control Register (SCICCR)........................................................... 995
13.3.3 SCI Control Register 1 (SCICTL1) ........................................................................... 996
13.3.4 SCI Baud-Select Registers (SCIHBAUD, SCILBAUD) .................................................... 998
13.3.5 SCI Control Register 2 (SCICTL2) ........................................................................... 999
13.3.6 SCI Receiver Status Register (SCIRXST)................................................................... 999
13.3.7 Receiver Data Buffer Registers (SCIRXEMU, SCIRXBUF) ............................................. 1001
13.3.8 SCI Transmit Data Buffer Register (SCITXBUF).......................................................... 1002
13.3.9 SCI FIFO Registers (SCIFFTX, SCIFFRX, SCIFFCT) ................................................... 1002
13.3.10 Priority Control Register (SCIPRI)......................................................................... 1006
14 C28 Inter-Integrated Circuit Module................................................................................... 1007
14.1 Introduction to the I2C Module ........................................................................................ 1008
14.1.1 Features........................................................................................................ 1009
14.1.2 Features Not Supported...................................................................................... 1009
14.1.3 Functional Overview .......................................................................................... 1009
14.1.4 Clock Generation.............................................................................................. 1010
14.2 I2C Module Operational Details ....................................................................................... 1011
14.2.1 Input and Output Voltage Levels............................................................................ 1011
14.2.2 Data Validity ................................................................................................... 1011
14.2.3 Operating Modes.............................................................................................. 1012
14.2.4 I2C Module START and STOP Conditions ................................................................ 1013
14.2.5 Serial Data Formats........................................................................................... 1013
14.2.6 NACK Bit Generation......................................................................................... 1015

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14.2.7 Clock Synchronization........................................................................................ 1016
14.2.8 Arbitration ...................................................................................................... 1016
14.3 Interrupt Requests Generated by the I2C Module.................................................................. 1017
14.3.1 Basic I2C Interrupt Requests................................................................................ 1017
14.3.2 I2C FIFO Interrupts ........................................................................................... 1018
14.4 Resetting/Disabling the I2C Module .................................................................................. 1018
14.5 I2C Module Registers................................................................................................... 1019
14.5.1 I2C Mode Register (I2CMDR) ............................................................................... 1020
14.5.2 I2C Extended Mode Register (I2CEMDR) ................................................................. 1023
14.5.3 I2C Interrupt Enable Register (I2CIER) .................................................................... 1025
14.5.4 I2C Status Register (I2CSTR)............................................................................... 1025
14.5.5 I2C Interrupt Source Register (I2CISRC) .................................................................. 1028
14.5.6 I2C Prescaler Register (I2CPSC)........................................................................... 1029
14.5.7 I2C Clock Divider Registers (I2CCLKL and I2CCLKH) .................................................. 1029
14.5.8 I2C Slave Address Register (I2CSAR)..................................................................... 1031
14.5.9 I2C Own Address Register (I2COAR)...................................................................... 1031
14.5.10 I2C Data Count Register (I2CCNT) ....................................................................... 1032
14.5.11 I2C Data Receive Register (I2CDRR) .................................................................... 1032
14.5.12 I2C Data Transmit Register (I2CDXR).................................................................... 1032
14.5.13 I2C Transmit FIFO Register (I2CFFTX) .................................................................. 1033
14.5.14 I2C Receive FIFO Register (I2CFFRX)................................................................... 1034
15 C28 Multichannel Buffered Serial Port (McBSP).................................................................. 1036
15.1 Overview.................................................................................................................. 1037
15.1.1 Features of the McBSP....................................................................................... 1037
15.1.2 McBSP Pins/Signals.......................................................................................... 1038
15.1.3 McBSP Operation............................................................................................. 1039
15.1.4 Data Transfer Process of McBSP........................................................................... 1040
15.1.5 Companding (Compressing and Expanding) Data........................................................ 1040
15.2 Clocking and Framing Data............................................................................................ 1042
15.2.1 Clocking ........................................................................................................ 1042
15.2.2 Serial Words ................................................................................................... 1042
15.2.3 Frames and Frame Synchronization........................................................................ 1043
15.2.4 Generating Transmit and Receive Interrupts.............................................................. 1043
15.2.5 Ignoring Frame-Synchronization Pulses ................................................................... 1043
15.2.6 Frame Frequency ............................................................................................. 1044
15.2.7 Maximum Frame Frequency................................................................................. 1044
15.3 Frame Phases ........................................................................................................... 1044
15.3.1 Number of Phases, Words, and Bits Per Frame.......................................................... 1045
15.3.2 Single-Phase Frame Example............................................................................... 1045
15.3.3 Dual-Phase Frame Example................................................................................. 1045
15.3.4 Implementing the AC97 Standard With a Dual-Phase Frame........................................... 1046
15.3.5 McBSP Reception............................................................................................. 1046
15.3.6 McBSP Transmission......................................................................................... 1048
15.3.7 Interrupts and DMA Events Generated by a McBSP..................................................... 1049
15.4 McBSP Sample Rate Generator ...................................................................................... 1049
15.4.1 Block Diagram................................................................................................. 1050
15.4.2 Frame Synchronization Generation in the Sample Rate Generator.................................... 1053
15.4.3 Synchronizing Sample Rate Generator Outputs to an External Clock................................. 1053
15.4.4 Reset and Initialization Procedure for the Sample Rate Generator .................................... 1055
15.5 McBSP Exception/Error Conditions................................................................................... 1056
15.5.1 Types of Errors ................................................................................................ 1056
15.5.2 Overrun in the Receiver...................................................................................... 1056
15.5.3 Unexpected Receive Frame-Synchronization Pulse ..................................................... 1058

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15.5.4 Overwrite in the Transmitter ................................................................................. 1060
15.5.5 Unexpected Transmit Frame-Synchronization Pulse..................................................... 1062
15.6 Multichannel Selection Modes......................................................................................... 1064
15.6.1 Channels, Blocks, and Partitions............................................................................ 1064
15.6.2 Multichannel Selection........................................................................................ 1065
15.6.3 Configuring a Frame for Multichannel Selection .......................................................... 1065
15.6.4 Using Two Partitions.......................................................................................... 1065
15.6.5 Using Eight Partitions......................................................................................... 1067
15.6.6 Receive Multichannel Selection Mode...................................................................... 1068
15.6.7 Transmit Multichannel Selection Modes ................................................................... 1068
15.7 SPI Operation Using the Clock Stop Mode.......................................................................... 1071
15.7.1 SPI Protocol.................................................................................................... 1071
15.7.2 Clock Stop Mode.............................................................................................. 1072
15.7.3 Bits Used to Enable and Configure the Clock Stop Mode............................................... 1072
15.7.4 Clock Stop Mode Timing Diagrams......................................................................... 1073
15.7.5 Procedure for Configuring a McBSP for SPI Operation.................................................. 1075
15.7.6 McBSP as the SPI Master ................................................................................... 1075
15.7.7 McBSP as an SPI Slave...................................................................................... 1077
15.8 Receiver Configuration ................................................................................................. 1078
15.8.1 Programming the McBSP Registers for the Desired Receiver Operation ............................. 1078
15.8.2 Resetting and Enabling the Receiver....................................................................... 1079
15.8.3 Set the Receiver Pins to Operate as McBSP Pins ....................................................... 1079
15.8.4 Enable/Disable the Digital Loopback Mode................................................................ 1080
15.8.5 Enable/Disable the Clock Stop Mode....................................................................... 1080
15.8.6 Enable/Disable the Receive Multichannel Selection Mode.............................................. 1081
15.8.7 Choose One or Two Phases for the Receive Frame..................................................... 1081
15.8.8 Set the Receive Word Length(s)............................................................................ 1082
15.8.9 Set the Receive Frame Length.............................................................................. 1082
15.8.10 Enable/Disable the Receive Frame-Synchronization Ignore Function................................ 1083
15.8.11 Set the Receive Companding Mode ...................................................................... 1084
15.8.12 Set the Receive Data Delay................................................................................ 1085
15.8.13 Set the Receive Sign-Extension and Justification Mode ............................................... 1087
15.8.14 Set the Receive Interrupt Mode............................................................................ 1088
15.8.15 Set the Receive Frame-Synchronization Mode.......................................................... 1088
15.8.16 Set the Receive Frame-Synchronization Polarity........................................................ 1090
15.8.17 Set the Receive Clock Mode............................................................................... 1092
15.8.18 Set the Receive Clock Polarity............................................................................. 1093
15.8.19 Set the SRG Clock Divide-Down Value................................................................... 1095
15.8.20 Set the SRG Clock Synchronization Mode............................................................... 1095
15.8.21 Set the SRG Clock Mode (Choose an Input Clock)..................................................... 1095
15.8.22 Set the SRG Input Clock Polarity.......................................................................... 1097
15.9 Transmitter Configuration .............................................................................................. 1097
15.9.1 Programming the McBSP Registers for the Desired Transmitter Operation .......................... 1097
15.9.2 Resetting and Enabling the Transmitter.................................................................... 1098
15.9.3 Set the Transmitter Pins to Operate as McBSP Pins .................................................... 1099
15.9.4 Enable/Disable the Digital Loopback Mode................................................................ 1099
15.9.5 Enable/Disable the Clock Stop Mode....................................................................... 1099
15.9.6 Enable/Disable Transmit Multichannel Selection ......................................................... 1101
15.9.7 Choose One or Two Phases for the Transmit Frame .................................................... 1101
15.9.8 Set the Transmit Word Length(s) ........................................................................... 1101
15.9.9 Set the Transmit Frame Length ............................................................................. 1103
15.9.10 Enable/Disable the Transmit Frame-Synchronization Ignore Function............................... 1104
15.9.11 Set the Transmit Companding Mode...................................................................... 1105

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15.9.12 Set the Transmit Data Delay............................................................................... 1106
15.9.13 Set the Transmit DXENA Mode............................................................................ 1108
15.9.14 Set the Transmit Interrupt Mode........................................................................... 1108
15.9.15 Set the Transmit Frame-Synchronization Mode......................................................... 1109
15.9.16 Set the Transmit Frame-Synchronization Polarity....................................................... 1110
15.9.17 Set the SRG Frame-Synchronization Period and Pulse Width........................................ 1111
15.9.18 Set the Transmit Clock Mode .............................................................................. 1112
15.9.19 Set the Transmit Clock Polarity............................................................................ 1112
15.10 Emulation and Reset Considerations ................................................................................ 1114
15.10.1 McBSP Emulation Mode.................................................................................... 1114
15.10.2 Resetting and Initializing McBSP.......................................................................... 1114
15.11 Data Packing Examples................................................................................................ 1116
15.11.1 Data Packing Using Frame Length and Word Length.................................................. 1116
15.11.2 Data Packing Using Word Length and the Frame-Synchronization Ignore Function............... 1118
15.12 McBSP Registers ....................................................................................................... 1118
15.12.1 Register Summary........................................................................................... 1119
15.12.2 Data Receive Registers (DRR[1,2])....................................................................... 1119
15.12.3 Data Transmit Registers (DXR[1,2]) ...................................................................... 1120
15.12.4 Serial Port Control Registers (SPCR[1,2]) ............................................................... 1121
15.12.5 Receive Control Registers (RCR[1, 2]) .................................................................. 1126
15.12.6 Transmit Control Registers (XCR1 and XCR2).......................................................... 1128
15.12.7 Sample Rate Generator Registers (SRGR1 and SRGR2) ............................................. 1131
15.12.8 Multichannel Control Registers (MCR[1,2]) .............................................................. 1133
15.12.9 Pin Control Register (PCR)................................................................................. 1138
15.12.10 Receive Channel Enable Registers (RCERA, RCERB, RCERC, RCERD, RCERE, RCERF,
RCERG, RCERH).............................................................................................. 1140
15.12.11 Transmit Channel Enable Registers (XCERA, XCERB, XCERC, XCERD, XCERE, XCERF,
XCERG, XCERH) .............................................................................................. 1142
15.12.12 Interrupt Generation ....................................................................................... 1144
16 M3 Micro Direct Memory Access ( µDMA)........................................................................... 1148
16.1 Overview.................................................................................................................. 1149
16.2 Block Diagram ........................................................................................................... 1149
16.3 Functional Description.................................................................................................. 1150
16.3.1 Channel Assignments ........................................................................................ 1151
16.3.2 Priority .......................................................................................................... 1152
16.3.3 Arbitration Size ................................................................................................ 1152
16.3.4 Request Types ................................................................................................ 1152
16.3.5 Channel Configuration........................................................................................ 1153
16.3.6 Transfer Modes................................................................................................ 1154
16.3.7 Transfer Size and Increment ................................................................................ 1163
16.3.8 Peripheral Interface........................................................................................... 1163
16.3.9 Software Request ............................................................................................. 1163
16.3.10 Interrupts and Errors ........................................................................................ 1164
16.4 Initialization and Configuration......................................................................................... 1164
16.4.1 Module Initialization........................................................................................... 1164
16.4.2 Configuring a Memory-to-Memory Transfer ............................................................... 1164
16.4.3 Configuring a Peripheral for Simple Transmit ............................................................. 1165
16.4.4 Configuring a Peripheral for Ping-Pong Receive.......................................................... 1167
16.5 Register Map............................................................................................................. 1169
16.6 µDMA Channel Control Structure ..................................................................................... 1171
16.6.1 DMA Channel Source Address End Pointer (DMASRCENDP), offset 0x000......................... 1171
16.6.2 DMA Channel Destination Address End Pointer (DMADSTENDP), offset 0x004.................... 1171
16.6.3 DMA Channel Control Word (DMACHCTL), offset 0x008 ............................................... 1172
16.7 µDMA Register Descriptions........................................................................................... 1175

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16.7.1 DMA Status (DMASTAT), offset 0x000 .................................................................... 1175
16.7.2 DMA Configuration (DMACFG), offset 0x004 ............................................................. 1176
16.7.3 DMA Channel Control Base Pointer (DMACTLBASE), offset 0x008................................... 1176
16.7.4 DMA Alternate Channel Control Base Pointer (DMAALTBASE), offset 0x00C....................... 1177
16.7.5 DMA Channel Wait-on-Request Status (DMAWAITSTAT), offset 0x010.............................. 1177
16.7.6 DMA Channel Software Request (DMASWREQ), offset 0x014 ........................................ 1177
16.7.7 DMA Channel Useburst Set (DMAUSEBURSTSET), offset 0x018..................................... 1178
16.7.8 DMA Channel Useburst Clear (DMAUSEBURSTCLR), offset 0x01C.................................. 1178
16.7.9 DMA Channel Request Mask Set (DMAREQMASKSET), offset 0x020 ............................... 1179
16.7.10 DMA Channel Request Mask Clear (DMAREQMASKCLR), offset 0x024 ........................... 1179
16.7.11 DMA Channel Enable Set (DMAENASET), offset 0x028............................................... 1179
16.7.12 DMA Channel Enable Clear (DMAENACLR), offset 0x02C............................................ 1180
16.7.13 DMA Channel Primary Alternate Set (DMAALTSET), offset 0x030................................... 1180
16.7.14 DMA Channel Primary Alternate Clear (DMAALTCLR), offset 0x034 ................................ 1181
16.7.15 DMA Channel Priority Set (DMAPRIOSET), offset 0x038.............................................. 1181
16.7.16 DMA Channel Priority Clear (DMAPRIOCLR), offset 0x03C........................................... 1181
16.7.17 DMA Bus Error Clear (DMAERRCLR), offset 0x04C ................................................... 1182
16.7.18 DMA Channel Assignment (DMACHALT), offset 0x500................................................ 1182
16.7.19 DMA Channel Map Assignment (DMACHMAP0) Register, offset 0x510 ............................ 1182
16.7.20 DMA Channel Map Assignment (DMACHMAP1) Register, offset 0x514 ............................ 1183
16.7.21 DMA Channel Map Assignment (DMACHMAP2) Register, offset 0x518 ............................ 1184
16.7.22 DMA Channel Map Assignment (DMACHMAP3) Register, offset 0x51C............................ 1185
16.7.23 DMA Peripheral Identification 0 (DMAPeriphID0), offset 0xFE0 ...................................... 1186
16.7.24 DMA Peripheral Identification 1 (DMAPeriphID1), offset 0xFE4 ...................................... 1187
16.7.25 DMA Peripheral Identification 2 (DMAPeriphID2), offset 0xFE8 ...................................... 1187
16.7.26 DMA Peripheral Identification 3 (DMAPeriphID3), offset 0xFEC...................................... 1187
16.7.27 DMA Peripheral Identification 4 (DMAPeriphID4), offset 0xFD0 ...................................... 1188
16.7.28 DMA PrimeCell Identification 0 (DMAPCellID0), offset 0xFF0......................................... 1188
16.7.29 DMA PrimeCell Identification 1 (DMAPCellID1), offset 0xFF4......................................... 1188
16.7.30 DMA PrimeCell Identification 2 (DMAPCellID2), offset 0xFF8......................................... 1189
16.7.31 DMA PrimeCell Identification 3 (DMAPCellID3), offset 0xFFC ........................................ 1189
17 External Peripheral Interface (EPI)..................................................................................... 1190
17.1 Introduction............................................................................................................... 1191
17.2 EPI Block Diagram...................................................................................................... 1192
17.3 Functional Description.................................................................................................. 1192
17.3.1 Non-Blocking Reads.......................................................................................... 1193
17.4 DMA Operation ......................................................................................................... 1194
17.5 Initialization and Configuration......................................................................................... 1194
17.6 SDRAM Mode ........................................................................................................... 1195
17.6.1 External Signal Connections................................................................................. 1196
17.6.2 Refresh Configuration ........................................................................................ 1196
17.6.3 Bus Interface Speed .......................................................................................... 1197
17.6.4 Non-Blocking Read Cycle.................................................................................... 1197
17.6.5 Normal Read Cycle ........................................................................................... 1197
17.6.6 Write Cycle..................................................................................................... 1198
17.7 Host Bus Mode .......................................................................................................... 1199
17.7.1 Control Pins.................................................................................................... 1199
17.7.2 Speed of Transactions........................................................................................ 1210
17.7.3 Sub-Modes of Host Bus 8/16................................................................................ 1211
17.7.4 Host Bus Operation........................................................................................... 1212
17.8 General-Purpose Mode................................................................................................. 1215
17.8.1 General Purpose Bus Operation ............................................................................ 1218
17.9 C28x Access to EPI..................................................................................................... 1223

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17.9.1 Real-Time Window (RTW) ................................................................................... 1224
17.9.2 Memory Protection............................................................................................ 1224
17.10 Register Map ............................................................................................................ 1225
17.11 Register Descriptions .................................................................................................. 1228
17.11.1 EPI Configuration Register (EPICFG), offset 0x000 .................................................... 1228
17.11.2 EPI Main Baud Rate (EPIBAUD) Register, offset 0x004............................................... 1229
17.11.3 EPI Main Baud Rate (EPIBAUD2) Register, offset 0x008 ............................................. 1230
17.11.4 EPI SDRAM Configuration (EPISDRAMCFG) Register, offset 0x010................................ 1231
17.11.5 EPI Host-Bus 8 Configuration (EPIHB8CFG) Register, offset 0x010................................. 1232
17.11.6 EPI Host-Bus 16 Configuration (EPIHB16CFG) Register. offset 0x010.............................. 1235
17.11.7 EPI General-Purpose Configuration (EPIGPCFG) Register, offset 0x010........................... 1238
17.11.8 EPI Host-Bus 8 Configuration 2 (EPIHB8CFG2) Register, Offset 0x014 ............................ 1241
17.11.9 EPI Host-Bus 16 Configuration 2 (EPIHB16CFG2) Register, offset 0x014.......................... 1244
17.11.10 EPI General-Purpose Configuration 2 (EPIGPCFG2) Register, offset 0x014...................... 1247
17.11.11 EPI Address Map (EPIADDRMAP) Register, offset 0x01C........................................... 1248
17.11.12 EPI Read Size 0 (EPIRSIZE0) Register and EPI Read Size 1 (EPIRSIZE1) Register, offset
0x020 and 0x030............................................................................................... 1249
17.11.13 EPI Read Address 0 (EPIRADDR0) Register and EPI Read Address 1 (EPIRADDR1)
Register, offset 0x024 and 0x034............................................................................ 1251
17.11.14 EPI Non-Blocking Read Data 0 (EPIRPSTD0) Register and EPI Non-Blocking Read Data 1
(EPIRPSTD1) Register, offset 0x028 and 0x038 .......................................................... 1251
17.11.15 EPI Status (EPISTAT) Register, offset 0x060.......................................................... 1253
17.11.16 EPI Read FIFO Count (EPIRFIFOCNT) Register, offset 0x06C..................................... 1254
17.11.17 EPI Read FIFO (EPIREADFIFO) Register and EPI Read FIFO Alias 1-7 (EPIREADFIFO1-7)
Registers, offset 0x070 and 0x08C .......................................................................... 1255
17.11.18 EPI FIFO Level Selects (EPIFIFOLVL) Register, 0x200.............................................. 1255
17.11.19 EPI Write FIFO Count (EPIWFIFOCNT) Register, offset 0x204..................................... 1257
17.11.20 EPI DMA Transmit Count (EPIDMATXCNT) Register, offset 0x208 ................................ 1258
17.11.21 EPI Interrupt Mask (EPIIM) Register, 0x210............................................................ 1258
17.11.22 EPI Raw Interrupt Status (EPIRIS) Register, offset 0x214 ........................................... 1259
17.11.23 EPI Masked Interrupt Status (EPIMIS) Register, offset 0x218....................................... 1260
17.11.24 EPI Error Interrupt Status and Clear (EPIEISC) Register, offset 0x21C............................ 1262
17.11.25 EPI Host-Bus 8 Configuration 3 (EPIHB8CFG3), offset 0x308 ...................................... 1263
17.11.26 EPI Host-Bus 16 Configuration 3 (EPIHB16CFG3), offset 0x308 ................................... 1264
17.11.27 EPI Host-Bus 8 Configuration 4 (EPIHB8CFG4), offset 0x30C...................................... 1265
17.11.28 EPI Host-Bus 16 Configuration 4 (EPIHB16CFG4), offset 0x30C................................... 1267
17.11.29 EPI Host-Bus 8 Timing Extension (EPIHB8TIME), offset 0x310..................................... 1268
17.11.30 EPI Host-Bus 16 Timing Extension (EPIHB16TIME), offset 0x310.................................. 1269
17.11.31 EPI Host-Bus 8 Timing Extension (EPIHB8TIME2), offset 0x314 ................................... 1270
17.11.32 EPI Host-Bus 16 Timing Extension (EPIHB16TIME2), offset 0x314 ................................ 1271
17.11.33 EPI Host-Bus 8 Timing Extension (EPIHB8TIME3), offset 0x318 ................................... 1272
17.11.34 EPI Host-Bus 16 Timing Extension (EPIHB16TIME3) Register, offset 0x318 ..................... 1273
17.11.35 EPI Host-Bus 8 Timing Extension (EPIHB8TIME4) Register, offset 0x31C........................ 1274
17.11.36 EPI Host-Bus 16 Timing Extension (EPIHB16TIME4) Register, 0x31C ............................ 1275
17.11.37 CEPIRTWCFG Register................................................................................... 1276
17.11.38 CEPIRTWCNT Register................................................................................... 1276
17.11.39 CEPIRTWPRD Register................................................................................... 1277
17.11.40 CEPISTATUS Register.................................................................................... 1277
17.11.41 MEMPROT Register ...................................................................................... 1277
18 M3 Universal Serial Bus (USB) Controller .......................................................................... 1279
18.1 Introduction............................................................................................................... 1280
18.1.1 Block Diagram................................................................................................. 1280
18.2 Functional Description.................................................................................................. 1280
18.2.1 Operation as a Device........................................................................................ 1281

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18.2.2 Operation as a Host........................................................................................... 1285
18.2.3 OTG Mode ..................................................................................................... 1288
18.2.4 DMA Operation................................................................................................ 1290
18.3 Initialization and Configuration......................................................................................... 1291
18.3.1 Pin Configuration.............................................................................................. 1291
18.3.2 Endpoint Configuration ....................................................................................... 1291
18.4 Register Map............................................................................................................. 1292
18.5 Register Descriptions................................................................................................... 1300
18.5.1 USB Device Functional Address Register (USBFADDR), offset 0x000................................ 1300
18.5.2 USB Power Management Register (USBPOWER), offset 0x001....................................... 1301
18.5.3 USB Transmit Interrupt Status Register (USBTXIS), offset 0x002 ..................................... 1303
18.5.4 USB Receive Interrupt Status Register (USBRXIS), offset 0x004...................................... 1305
18.5.5 USB Transmit Interrupt Enable Register (USBTXIE), offset 0x006 .................................... 1307
18.5.6 USB Receive Interrupt Enable Register (USBRXIE), offset 0x008..................................... 1309
18.5.7 USB General Interrupt Status Register (USBIS), offset 0x00A ......................................... 1311
18.5.8 USB Interrupt Enable Register (USBIE), offset 0x00B................................................... 1313
18.5.9 USB Frame Value Register (USBFRAME), offset 0x00C................................................ 1315
18.5.10 USB Endpoint Index Register (USBEPIDX), offset 0x00E............................................. 1315
18.5.11 USB Test Mode Register (USBTEST), offset 0x00F.................................................... 1316
18.5.12 USB FIFO Endpoint n Register (USBFIFO[0]-USBFIFO[15]).......................................... 1318
18.5.13 USB Device Control Register (USBDEVCTL), offset 0x060 ........................................... 1319
18.5.14 USB Transmit Dynamic FIFO Sizing Register (USBTXFIFOSZ), offset 0x062...................... 1321
18.5.15 USB Receive Dynamic FIFO Sizing Register (USBRXFIFOSZ), offset 0x063...................... 1322
18.5.16 USB Transmit FIFO Start Address Register (USBTXFIFOADD), offset 0x064...................... 1323
18.5.17 USB Receive FIFO Start Address Register (USBRXFIFOADD), offset 0x066...................... 1324
18.5.18 USB Connect Timing Register (USBCONTIM), offset 0x07A.......................................... 1325
18.5.19 USB OTG VBUS Pulse Timing Register (USBVPLEN), offset 0x07B................................ 1325
18.5.20 USB Full-Speed Last Transaction to End of Frame Timing Register (USBFSEOF), offset
0x07D............................................................................................................ 1326
18.5.21 USB Low-Speed Last Transaction to End of Frame Timing Register (USBLSEOF), offset
0x07E ............................................................................................................ 1326
18.5.22 USB Transmit Functional Address Endpoint n Registers (USBTXFUNCADDR[0]-
USBTXFUNCADDR[15]) ...................................................................................... 1327
18.5.23 USB Transmit Hub Address Endpoint n Registers (USBTXHUBADDR[0]-
USBTXHUBADDR[15])........................................................................................ 1328
18.5.24 USB Transmit Hub Port Endpoint n Registers (USBTXHUBPORT[0]-USBTXHUBPORT[15]) ... 1329
18.5.25 USB Receive Functional Address Endpoint n Registers (USBRXFUNCADDR[1]-
USBRXFUNCADDR[15])...................................................................................... 1330
18.5.26 USB Receive Hub Address Endpoint n Registers (USBRXHUBADDR[1]-
USBRXHUBADDR[15])........................................................................................ 1331
18.5.27 USB Receive Hub Port Endpoint n Registers (USBRXHUBPORT[1]-USBRXHUBPORT[15]).... 1332
18.5.28 USB Maximum Transmit Data Endpoint n Registers (USBTXMAXP[1]-USBTXMAXP[15]) ....... 1333
18.5.29 USB Control and Status Endpoint 0 Low Register (USBCSRL0), offset 0x102..................... 1334
18.5.30 USB Control and Status Endpoint 0 High Register (USBCSRH0), offset 0x103.................... 1336
18.5.31 USB Receive Byte Count Endpoint 0 Register (USBCOUNT0), offset 0x108....................... 1337
18.5.32 USB Type Endpoint 0 Register (USBTYPE0), offset 0x10A........................................... 1337
18.5.33 USB NAK Limit Register (USBNAKLMT), offset 0x10B ................................................ 1338
18.5.34 USB Transmit Control and Status Endpoint n Low Register (USBTXCSRL[1]-
USBTXCSRL[15]) .............................................................................................. 1339
18.5.35 USB Transmit Control and Status Endpoint n High Register (USBTXCSRH[1]-
USBTXCSRH[15]).............................................................................................. 1342
18.5.36 USB Maximum Receive Data Endpoint n Registers (USBRXMAXP[1]-USBRXMAXP[15]) ....... 1344
18.5.37 USB Receive Control and Status Endpoint n Low Register (USBRXCSRL[1]-
USBRXCSRL[15]).............................................................................................. 1345
18.5.38 USB Receive Control and Status Endpoint n High Register (USBRXCSRH[1]-

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USBRXCSRH[15]) ............................................................................................. 1348
18.5.39 USB Receive Byte Count Endpoint n Registers (USBRXCOUNT[1]-USBRXCOUNT[15]) ........ 1350
18.5.40 USB Host Transmit Configure Type Endpoint n Register (USBTXTYPE[1]-USBTXTYPE[15])... 1351
18.5.41 USB Host Transmit Interval Endpoint n Register (USBTXINTERVAL[1]USBTXINTERVAL[15]) .1352
18.5.42 USB Host Configure Receive Type Endpoint n Register (USBRXTYPE[1]-USBRXTYPE[15]) ... 1353
18.5.43 USB Host Receive Polling Interval Endpoint n Register
(USBRXINTERVAL[1]USBRXINTERVAL[15]).............................................................. 1354
18.5.44 USB Request Packet Count in Block Transfer Endpoint n Registers
(USBRQPKTCOUNT[1]USBRQPKTCOUNT[15]).......................................................... 1355
18.5.45 USB Receive Double Packet Buffer Disable Register (USBRXDPKTBUFDIS), offset 0x340..... 1356
18.5.46 USB Transmit Double Packet Buffer Disable Register (USBTXDPKTBUFDIS), offset 0x342 .... 1358
18.5.47 USB External Power Control Register (USBEPC), offset 0x400 ...................................... 1360
18.5.48 USB External Power Control Raw Interrupt Status Register (USBEPCRIS), offset 0x404........ 1362
18.5.49 USB External Power Control Interrupt Mask Register (USBEPCIM), offset 0x408................. 1363
18.5.50 USB External Power Control Interrupt Status and Clear Register (USBEPCISC), offset 0x40C .1364
18.5.51 USB Device RESUME Raw Interrupt Status Register (USBDRRIS), offset 0x410................. 1365
18.5.52 USB Device RESUME Raw Interrupt Mask Register (USBDRIM), offset 0x414.................... 1366
18.5.53 USB Device RESUME Interrupt Status and Clear Register (USBDRISC), offset 0x418........... 1367
18.5.54 USB General-Purpose Control and Status Register (USBGPCS), offset 0x41C.................... 1368
18.5.55 USB VBUS Droop Control Register (USBVDC), offset 0x430......................................... 1369
18.5.56 USB VBUS Droop Control Raw Interrupt Status Register (USBVDCRIS), offset 0x434........... 1370
18.5.57 USB VBUS Droop Control Interrupt Mask Register (USBVDCIM), offset 0x438.................... 1371
18.5.58 USB VBUS Droop Control Interrupt Status and Clear Register (USBVDCISC), offset 0x43C.... 1372
18.5.59 USB ID Valid Detect Raw Interrupt Status Register (USBIDVRIS), offset 0x444................... 1373
18.5.60 USB ID Valid Detect Interrupt Mask Register (USBIDVIM), offset 0x448............................ 1374
18.5.61 USB ID Valid Detect Interrupt Status and Clear Register (USBIDVISC), offset 0x44C............ 1375
18.5.62 USB DMA Select Register (USBDMASEL), offset 0x450 .............................................. 1376
19 M3 Ethernet Media Access Controller (EMAC) .................................................................... 1380
19.1 Introduction............................................................................................................... 1381
19.2 EMAC Block Diagram................................................................................................... 1381
19.3 Functional Description.................................................................................................. 1382
19.3.1 MAC Operation................................................................................................ 1382
19.3.2 Internal MII Operation ........................................................................................ 1385
19.3.3 Interrupts ....................................................................................................... 1385
19.3.4 DMA Operation................................................................................................ 1386
19.4 Initialization and Configuration......................................................................................... 1386
19.4.1 Software Configuration ....................................................................................... 1386
19.5 Register Map............................................................................................................. 1387
19.6 Ethernet MAC Register Descriptions ................................................................................. 1388
19.6.1 Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK) Register, offset 0x000.. 1388
19.6.2 Ethernet MAC Interrupt Mask (MACIM) Register, offset 0x004......................................... 1389
19.6.3 Ethernet MAC Receive Control (MACRCTL) Register, offset 0x008................................... 1390
19.6.4 Ethernet MAC Transmit Control (MACTCTL) Register, offset 0x00C.................................. 1391
19.6.5 Ethernet MAC Data (MACDATA) Register, offset 0x010 ................................................ 1393
19.6.6 Ethernet MAC Individual Address 0 (MACIA0) Register, offset 0x014................................. 1394
19.6.7 Ethernet MAC Individual Address 1 (MACIA1) Register, offset 0x018................................. 1395
19.6.8 Ethernet MAC Threshold (MACTHR) Register, offset 0x01C ........................................... 1396
19.6.9 Ethernet MAC Management Control (MACMCTL) Register, offset 0x020............................. 1397
19.6.10 Ethernet MAC Management Divider (MACMDV) Register, offset 0x024............................. 1398
19.6.11 Ethernet MAC Management Address Register (MACMAR), offset 0x028 ........................... 1398
19.6.12 Ethernet MAC Management Transmit Data (MACMTXD) Register, offset 0x02C.................. 1398
19.6.13 Ethernet MAC Management Receive Data (MACMRXD) Register, offset 0x030................... 1400
19.6.14 Ethernet MAC Number of Packets (MACNP) Register, offset 0x034................................. 1400
19.6.15 Ethernet MAC Transmission Request (MACTR) Register, offset 0x038 ............................. 1401

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19.6.16 Ethernet MAC Timer Support (MACTS) Register, offset 0x03C....................................... 1401
19.7 MII Management Register Descriptions.............................................................................. 1402
19.7.1 Ethernet PHY Management Register 0 – Control (MR0) Register, address 0x00.................... 1402
19.7.2 Ethernet PHY Management Register 1 – Status (MR1) Register, address 0x01..................... 1404
19.7.3 Ethernet PHY Management Register 2 – PHY Identifier 1 (MR2) Register , address 0x02......... 1405
19.7.4 Ethernet PHY Management Register 3 – PHY Identifier 2 (MR3) Register, address 0x03 ......... 1405
19.7.5 Ethernet PHY Management Register 4 – Auto-Negotiation Advertisement (MR4) Register,
address 0x04.................................................................................................... 1406
19.7.6 Ethernet PHY Management Register 5 – Auto-Negotiation Link Partner Base Page Ability (MR5)
Register, address 0x05........................................................................................ 1407
19.7.7 Ethernet PHY Management Register 6 – Auto-Negotiation Expansion (MR6) Register, address
0x06.............................................................................................................. 1408
20 M3 Synchronous Serial Interface (SSI)............................................................................... 1409
20.1 Introduction............................................................................................................... 1410
20.2 Features .................................................................................................................. 1410
20.2.1 SSI Block Diagram............................................................................................ 1410
20.3 Functional Description.................................................................................................. 1411
20.3.1 Bit Rate Generation........................................................................................... 1412
20.3.2 FIFO Operation................................................................................................ 1412
20.3.3 Interrupts ....................................................................................................... 1412
20.3.4 Frame Formats ................................................................................................ 1413
20.3.5 DMA Operation................................................................................................ 1417
20.4 Initialization and Configuration......................................................................................... 1418
20.5 SSI Registers ............................................................................................................ 1419
20.5.1 SSI Base Addresses.......................................................................................... 1419
20.5.2 SSI_REGS Registers......................................................................................... 1420
21 M3 Universal Asynchronous Receivers/Transmitters (UARTs).............................................. 1451
21.1 Introduction............................................................................................................... 1452
21.2 Block Diagram ........................................................................................................... 1452
21.3 Functional Description.................................................................................................. 1453
21.3.1 Transmit/Receive Logic ...................................................................................... 1453
21.3.2 Baud-Rate Generation........................................................................................ 1454
21.3.3 Data Transmission ............................................................................................ 1454
21.3.4 Serial IR (SIR) ................................................................................................. 1455
21.3.5 ISO 7816 Support............................................................................................. 1456
21.3.6 LIN Support .................................................................................................... 1456
21.3.7 FIFO Operation................................................................................................ 1457
21.3.8 Interrupts ....................................................................................................... 1457
21.3.9 Loopback Operation .......................................................................................... 1458
21.3.10 DMA Operation............................................................................................... 1458
21.4 M3 UART4 to C28 SCI-A Internal Loopback ........................................................................ 1458
21.4.1 Loopback Initialization and Configuration.................................................................. 1459
21.5 Initialization and Configuration......................................................................................... 1459
21.6 Register Map............................................................................................................. 1460
21.7 Register Descriptions................................................................................................... 1461
21.7.1 UART Data Register (UARTDR), offset 0x000............................................................ 1461
21.7.2 UART Receive Status/Error Clear Register (UARTRSR/UARTECR), offset 0x004.................. 1462
21.7.3 UART Flag Register (UARTFR), offset 0x018............................................................. 1464
21.7.4 UART IrDA Low-Power Register (UARTILPR), offset 0x020............................................ 1466
21.7.5 UART Integer Baud-Rate Divisor Register (UARTIBRD), offset 0x024................................ 1466
21.7.6 UART Fractional Baud-Rate Divisor Register (UARTFBRD), offset 0x028 ........................... 1467
21.7.7 UART Line Control Register (UARTLCRH), offset 0x02C............................................... 1467
21.7.8 UART Control Register (UARTCTL), offset 0x030........................................................ 1468

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21.7.9 UART Interrupt FIFO Level Select (UARTIFLS) Register, offset 0x034 ............................... 1470
21.7.10 UART Interrupt Mask (UARTIM) Register, offset 0x038................................................ 1471
21.7.11 UART Raw Interrupt Status (UARTRIS), offset 0x03C ................................................. 1473
21.7.12 UART Masked Interrupt Status (UARTMIS), offset 0x040 ............................................. 1475
21.7.13 UART Interrupt Clear (UARTICR), offset 0x044......................................................... 1477
21.7.14 UART DMA Control (UARTDMACTL), offset 0x048 .................................................... 1478
21.7.15 UART LIN Control (UARTLCTL), offset 0x090 .......................................................... 1478
21.7.16 UART LIN Snap Shot (UARTLSS), offset 0x094........................................................ 1479
21.7.17 UART LIN Timer (UARTLTIM), offset 0x098............................................................. 1479
21.7.18 UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0.................................... 1480
21.7.19 UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4.................................... 1480
21.7.20 UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8.................................... 1480
21.7.21 UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ................................... 1481
21.7.22 UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0.................................... 1481
21.7.23 UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4.................................... 1481
21.7.24 UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8.................................... 1482
21.7.25 UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ................................... 1482
21.7.26 UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0...................................... 1482
21.7.27 UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4...................................... 1483
21.7.28 UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8...................................... 1483
21.7.29 UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ..................................... 1483
22 M3 Inter-Integrated Circuit (I2C) Interface........................................................................... 1484
22.1 Introduction............................................................................................................... 1485
22.2 I2C Block Diagram ...................................................................................................... 1485
22.3 Functional Description.................................................................................................. 1485
22.3.1 I2C Bus Functional Overview................................................................................ 1486
22.3.2 Available Speed Modes ...................................................................................... 1487
22.3.3 Interrupts ....................................................................................................... 1489
22.3.4 Loopback Operation .......................................................................................... 1490
22.3.5 Command Sequence Flow Charts.......................................................................... 1490
22.4 Initialization and Configuration......................................................................................... 1497
22.5 Register Map............................................................................................................. 1498
22.6 Register Descriptions................................................................................................... 1499
22.6.1 I2C Master Slave Address (I2CMSA), offset 0x000 ...................................................... 1499
22.6.2 I2C Master Control/Status (I2CMCS), offset 0x004 ...................................................... 1500
22.6.3 I2C Master Data (I2CMDR), offset 0x008.................................................................. 1504
22.6.4 I2C Master Timer Period (I2CMTPR), offset 0x00C...................................................... 1504
22.6.5 I2C Master Interrupt Mask (I2CMIMR), offset 0x010..................................................... 1505
22.6.6 I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014.............................................. 1505
22.6.7 I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018.......................................... 1506
22.6.8 I2C Master Interrupt Clear (I2CMICR), offset 0x01C..................................................... 1506
22.6.9 I2C Master Configuration (I2CMCR), offset 0x020 ....................................................... 1507
22.7 Register Descriptions (I2C Slave)..................................................................................... 1508
22.7.1 I2C Slave Own Address (I2CSOAR), offset 0x800 ....................................................... 1508
22.7.2 I2C Slave Control/Status (I2CSCSR), offset 0x804 ...................................................... 1508
22.7.3 I2C Slave Data (I2CSDR), offset 0x808.................................................................... 1509
22.7.4 I2C Slave Interrupt Mask (I2CSIMR), offset 0x80C....................................................... 1509
22.7.5 I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x810................................................ 1510
22.7.6 I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x814............................................ 1510
22.7.7 I2C Slave Interrupt Clear (I2CSICR), offset 0x818 ....................................................... 1511
23 M3 Controller Area Network (CAN).................................................................................... 1512
23.1 Overview ................................................................................................................. 1513
23.1.1 Features ....................................................................................................... 1513

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23.1.2 Functional Description ....................................................................................... 1513
23.1.3 Block Diagram ................................................................................................ 1514
23.2 Operating Modes........................................................................................................ 1515
23.2.1 Initialization .................................................................................................... 1515
23.2.2 CAN Message Transfer (Normal Operation) .............................................................. 1515
23.2.3 Test Modes .................................................................................................... 1516
23.3 Multiple Clock Source .................................................................................................. 1520
23.4 Interrupt Functionality .................................................................................................. 1520
23.4.1 Message Object Interrupts .................................................................................. 1520
23.4.2 Status Change Interrupts .................................................................................... 1520
23.4.3 Error Interrupts ................................................................................................ 1521
23.5 Global Power-down Mode ............................................................................................. 1521
23.5.1 Entering Global Power-down Mode ........................................................................ 1521
23.5.2 Wakeup from Global Power-down Mode .................................................................. 1521
23.6 Local Power-down Mode .............................................................................................. 1521
23.6.1 Entering Local Power-down Mode ......................................................................... 1521
23.6.2 Wakeup from Local Power-down Mode ................................................................... 1521
23.7 Parity Check Mechanism .............................................................................................. 1522
23.7.1 Behavior on Parity Error ..................................................................................... 1522
23.8 Debug Mode ............................................................................................................ 1522
23.9 Module Initialization .................................................................................................... 1523
23.10 Configuration of Message Objects ................................................................................... 1523
23.10.1 Configuration of a Transmit Object for Data Frames ................................................... 1523
23.10.2 Configuration of a Transmit Object for Remote Frames ............................................... 1524
23.10.3 Configuration of a Single Receive Object for Data Frames ........................................... 1524
23.10.4 Configuration of a Single Receive Object for Remote Frames ....................................... 1524
23.10.5 Configuration of a FIFO Buffer ............................................................................ 1525
23.11 Message Handling ..................................................................................................... 1525
23.11.1 Message Handler Overview ............................................................................... 1525
23.11.2 Receive/Transmit Priority .................................................................................. 1526
23.11.3 Transmission of Messages in Event Driven CAN Communication ................................... 1526
23.11.4 Updating a Transmit Object ............................................................................... 1526
23.11.5 Changing a Transmit Object ............................................................................... 1527
23.11.6 Acceptance Filtering of Received Messages ............................................................ 1527
23.11.7 Reception of Data Frames ................................................................................. 1527
23.11.8 Reception of Remote Frames ............................................................................. 1527
23.11.9 Reading Received Messages ............................................................................. 1528
23.11.10 Requesting New Data for a Receive Object ........................................................... 1528
23.11.11 Storing Received Messages in FIFO Buffers .......................................................... 1528
23.11.12 Reading from a FIFO Buffer ............................................................................. 1528
23.12 CAN Bit Timing ......................................................................................................... 1529
23.12.1 Bit Time and Bit Rate ....................................................................................... 1530
23.12.2 Configuration of the CAN Bit Timing ..................................................................... 1535
23.13 Message Interface Register Sets .................................................................................... 1537
23.13.1 Message Interface Register Sets 1 and 2 ............................................................... 1538
23.13.2 IF3 Register Set ............................................................................................. 1539
23.14 Message RAM .......................................................................................................... 1539
23.14.1 Structure of Message Objects ............................................................................. 1540
23.14.2 Addressing Message Objects in RAM ................................................................... 1542
23.14.3 Message RAM Representation in Debug Mode ........................................................ 1543
23.15 CAN Control Registers................................................................................................. 1543
23.15.1 CAN Control Register (CAN CTL)......................................................................... 1544
23.15.2 Error and Status Register (CAN ES)...................................................................... 1546

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23.15.3 Error Counter Register (CAN ERRC) ..................................................................... 1548
23.15.4 Bit Timing Register (CAN BTR)............................................................................ 1548
23.15.5 Interrupt Register (CAN INT)............................................................................... 1549
23.15.6 Test Register (CAN TEST) ................................................................................. 1550
23.15.7 Parity Error Code Register (CAN PERR) ................................................................ 1551
23.15.8 Auto-Bus-On Time Register (CAN ABOTR) ............................................................. 1551
23.15.9 Transmission Request Registers (CAN TXRQ) ......................................................... 1552
23.15.10 New Data Registers (CAN NWDAT)..................................................................... 1553
23.15.11 Interrupt Pending Registers (CAN INTPND)............................................................ 1553
23.15.12 Message Valid Registers (CAN MSGVAL) ............................................................. 1554
23.15.13 Interrupt Multiplexer Registers (CAN INTMUX) ........................................................ 1554
23.15.14 IF1 and IF2 Command Registers (CAN IF1CMD, CAN IF2CMD)................................... 1555
23.15.15 IF1 and IF2 Mask Registers (CAN IF1MSK, CAN IF2MSK).......................................... 1557
23.15.16 IF1 and F2 Arbitration Registers (CAN IF1ARB, CAN IF2ARB) ..................................... 1558
23.15.17 IF1 and IF2 Message Control Registers (CAN IF1MCTL, CAN IF2MCTL)......................... 1559
23.15.18 IF1 and IF2 Data A and Data B Registers (CAN IF1DATA/DATB, CAN IF2DATA/DATB) ..... 1561
23.15.19 IF3 Observation Register (CAN IF3OBS)............................................................... 1562
23.15.20 IF3 Mask Register (CAN IF3MSK)....................................................................... 1563
23.15.21 IF3 Arbitration Register (CAN IF3ARB) ................................................................. 1563
23.15.22 IF3 Message Control Register (CAN IF3MCTL) ....................................................... 1564
23.15.23 IF3 Data A and Data B Registers (CAN IF3DATA/DATB)............................................ 1565
23.15.24 IF3 Update Enable Registers (CAN IF3UPD) .......................................................... 1566
24 Cortex-M3 Processor....................................................................................................... 1567
24.1 Overview.................................................................................................................. 1568
24.2 Block Diagram ........................................................................................................... 1568
24.3 Overview.................................................................................................................. 1569
24.3.1 System-Level Interface....................................................................................... 1569
24.3.2 System Component Details.................................................................................. 1569
24.4 Programming Model .................................................................................................... 1570
24.4.1 Processor Mode and Privilege Levels for Software Execution.......................................... 1570
24.4.2 Stacks........................................................................................................... 1570
24.4.3 Register Map................................................................................................... 1570
24.4.4 Register Descriptions......................................................................................... 1572
24.4.5 Exceptions and Interrupts.................................................................................... 1578
24.4.6 Data Types..................................................................................................... 1578
24.5 Memory Model........................................................................................................... 1578
24.6 Memory Regions, Types and Attributes.............................................................................. 1579
24.6.1 Memory System Ordering of Memory Accesses.......................................................... 1579
24.6.2 Behavior of Memory Accesses.............................................................................. 1579
24.6.3 Software Ordering of Memory Accesses................................................................... 1580
24.6.4 Bit-Banding..................................................................................................... 1581
24.6.5 Data Storage................................................................................................... 1582
24.6.6 Synchronization Primitives................................................................................... 1583
24.7 Exception Model......................................................................................................... 1584
24.7.1 Exception States .............................................................................................. 1584
24.7.2 Exception Types............................................................................................... 1584
24.7.3 Exception Handlers ........................................................................................... 1588
24.7.4 Vector Table ................................................................................................... 1588
24.7.5 Exception Priorities............................................................................................ 1589
24.7.6 Interrupt Priority Grouping.................................................................................... 1590
24.7.7 Exception Entry and Return.................................................................................. 1590
24.8 Fault Handling ........................................................................................................... 1592
24.8.1 Fault Types..................................................................................................... 1592