Texas Instruments Concerto F28M35 Series Product manual

Concerto F28M35x
Technical Reference Manual
Literature Number: SPRUH22I
April 2012–Revised November 2019

2SPRUH22I–April 2012–Revised November 2019
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Contents
Contents
Preface....................................................................................................................................... 78
1 System Control and Interrupts............................................................................................. 79
1.1 Signal Description.......................................................................................................... 80
1.2 System Control Functional Description.................................................................................. 81
1.2.1 Device Identification............................................................................................... 81
1.2.2 Device Configuration Registers ................................................................................. 82
1.3 Reset Control ............................................................................................................... 82
1.3.1 Device Level Reset Sources..................................................................................... 82
1.3.2 Handling of Resets at System Level............................................................................ 89
1.4 WIR Mode................................................................................................................... 92
1.4.1 Entering WIR Mode ............................................................................................... 93
1.4.2 Exiting WIR Mode................................................................................................. 94
1.5 Exceptions and Interrupts Control........................................................................................ 95
1.5.1 Master Subsystem Nested Vectored Interrupt Controller.................................................... 95
1.5.2 Master Subsystem Exceptions Handling....................................................................... 96
1.5.3 Master Subsystem Non-Maskable Interrupt (MNMI) Module................................................ 97
1.5.4 Control Subsystem PIE ......................................................................................... 100
1.5.5 Control Subsystem Exceptions Handling..................................................................... 116
1.5.6 Control Subsystem NMI (CNMI) Module...................................................................... 116
1.6 Safety Features ........................................................................................................... 119
1.6.1 Write Protection on Registers.................................................................................. 119
1.6.2 Missing Clock Detection Logic ................................................................................. 120
1.6.3 PLLSLIP Detection .............................................................................................. 123
1.6.4 Control Subsystem PIE Vector Address Validity Check.................................................... 123
1.6.5 NMIWDs .......................................................................................................... 124
1.6.6 Watchdog Timers................................................................................................ 124
1.6.7 ECC and Parity Enabled RAMs, Shared RAMs Protection ................................................ 124
1.6.8 ECC Enabled Flash Memory................................................................................... 125
1.7 Power Control ............................................................................................................. 125
1.8 Clock Control.............................................................................................................. 125
1.8.1 Clock Sources.................................................................................................... 126
1.8.2 PLLs ............................................................................................................... 126
1.8.3 Master Subsystem Clocking.................................................................................... 127
1.8.4 Control Subsystem Clocking ................................................................................... 130
1.8.5 Clocking Control Semaphore Functionality................................................................... 134
1.8.6 ACIB and Analog Peripherals Clocking....................................................................... 135
1.8.7 Configuring XCLKOUT.......................................................................................... 135
1.8.8 32-Bit CPU Timers 0/1/2........................................................................................ 136
1.9 Low Power Modes........................................................................................................ 140
1.9.1 Low-Power Modes............................................................................................... 140
1.10 Code Security Module (CSM)........................................................................................... 144
1.10.1 Functional Description ......................................................................................... 144
1.10.2 CSM Impact on Other On-Chip Resources ................................................................. 147
1.10.3 Incorporating Code Security in User Applications.......................................................... 147
1.10.4 Do's and Don'ts to Protect Security Logic................................................................... 155

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1.11 µCRC Module ............................................................................................................. 155
1.11.1 Functional Description ......................................................................................... 155
1.11.2 CRC Polynomials............................................................................................... 156
1.11.3 CRC Calculation Procedure................................................................................... 156
1.11.4 CRC Calculation For Data Stored In Secure Memory ..................................................... 156
1.12 Inter Processor Communications (IPC)................................................................................ 156
1.12.1 MSGRAMs....................................................................................................... 157
1.12.2 IPC Flags and Interrupts....................................................................................... 157
1.12.3 MTOCIPC Communication ................................................................................... 158
1.12.4 CTOMIPC Communication .................................................................................... 159
1.12.5 Examples for Software IPC Procedure ...................................................................... 160
1.12.6 IPC Message Registers........................................................................................ 160
1.12.7 Flash Pump Semaphore....................................................................................... 161
1.12.8 Clock Configuration Semaphore.............................................................................. 162
1.12.9 Free Running Counter ......................................................................................... 164
1.13 System Control Registers................................................................................................ 165
1.13.1 System Control, Configuration Register Map ............................................................... 165
1.13.2 Device Identification and Device Configuration............................................................. 173
1.13.3 Reset Control and Status Registers.......................................................................... 188
1.13.4 WIRMODE Registers........................................................................................... 197
1.13.5 Exception and Interrupts....................................................................................... 198
1.13.6 Safety Control Registers....................................................................................... 218
1.13.7 Clocking Control Registers .................................................................................... 222
1.13.8 Master Subsystem Code Security Module (CSM) Registers.............................................. 248
1.13.9 Control Subsystem Code Security Module (CSM) Registers............................................. 264
1.13.10 µCRC Register Description .................................................................................. 268
1.13.11 Master Subsystem IPC Registers........................................................................... 270
1.13.12 Control Subsystem IPC Registers .......................................................................... 281
1.13.13 Master and Control Subsystem IPC Registers............................................................ 293
2 M3 General-Purpose Timers............................................................................................... 298
2.1 GPTM Features........................................................................................................... 299
2.2 Block Diagram............................................................................................................. 299
2.3 Functional Description.................................................................................................... 300
2.3.1 GPTM Reset Conditions........................................................................................ 300
2.3.2 Timer Modes ..................................................................................................... 301
2.3.3 DMA Operation................................................................................................... 305
2.3.4 Accessing Concatenated Register Values ................................................................... 306
2.4 Initialization and Configuration.......................................................................................... 306
2.4.1 One-Shot/Periodic Timer Mode................................................................................ 306
2.4.2 Real-Time Clock (RTC) Mode.................................................................................. 307
2.4.3 Input Edge-Count Mode......................................................................................... 307
2.4.4 Input Edge Timing Mode........................................................................................ 307
2.4.5 16-Bit PWM Mode ............................................................................................... 308
2.5 Register Map .............................................................................................................. 308
2.6 Register Descriptions..................................................................................................... 309
2.6.1 GPTM Configuration (GPTMCFG) Register, offset 0x000 ................................................. 309
2.6.2 GPTM Timer A Mode (GPTMTAMR) Register, offset 0x004 .............................................. 309
2.6.3 GPTM Timer B Mode (GPTMTBMR) Register, offset 0x008 .............................................. 311
2.6.4 GPTM Control (GPTMCTL) Register, offset 0x00C......................................................... 312
2.6.5 GPTM Interrupt Mask (GPTMIMR) Register, offset 0x018................................................. 313
2.6.6 GPTM Raw Interrupt Status (GPTMRIS) Register, offset 0x01C ......................................... 314
2.6.7 GPTM Masked Interrupt Status (GPTMMIS) Register, offset 0x020...................................... 315
2.6.8 GPTM Interrupt Clear (GPTMICR) Register, offset 0x024 ................................................. 316

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2.6.9 GPTM Timer A Interval Load (GPTMTAILR) Register, offset 0x028 ..................................... 317
2.6.10 GPTM Timer B Interval Load (GPTMTBILR) Register, offset 0x02C.................................... 318
2.6.11 GPTM Timer A Match (GPTMTAMATCHR) Register, offset 0x030 ..................................... 318
2.6.12 GPTM Timer B Match (GPTMTBMATCHR) Register, offset 0x034 ..................................... 319
2.6.13 GPTM Timer A Prescale (GPTMTAPR) Register, offset 0x038.......................................... 319
2.6.14 GPTM Timer B Prescale (GPTMTBPR) Register, offset 0x03C.......................................... 320
2.6.15 GPTM Timer A Prescale Match (GPTMTAPMR) Register, offset 0x040................................ 320
2.6.16 GPTM Timer B Prescale Match (GPTMTBPMR) Register, offset 0x044................................ 320
2.6.17 GPTM Timer A (GPTMTAR) Register, offset 0x048 ....................................................... 321
2.6.18 GPTM Timer B (GPTMTBR) Register, offset 0x04C....................................................... 321
2.6.19 GPTM Timer A Value (GPTMTAV) Register, offset 0x050................................................ 322
2.6.20 GPTM Timer B Value (GPTMTBV) Register, offset 0x054................................................ 322
3 M3 Watchdog Timers ........................................................................................................ 324
3.1 Introduction ................................................................................................................ 325
3.1.1 Block Diagram.................................................................................................... 325
3.1.2 Functional Description........................................................................................... 326
3.1.3 Initialization and Configuration................................................................................. 326
3.2 Register Map .............................................................................................................. 326
3.3 Register Descriptions..................................................................................................... 327
3.3.1 Watchdog Load (WDTLOAD) Register, offset 0x000....................................................... 327
3.3.2 Watchdog Value (WDTVALUE) Register, offset 0x004..................................................... 328
3.3.3 Watchdog Control (WDTCTL) Register, offset 0x008....................................................... 329
3.3.4 Watchdog Interrupt Clear (WDTICR) Register, offset 0x00C.............................................. 329
3.3.5 Watchdog Raw Interrupt Status (WDTRIS) Register, offset 0x010 ....................................... 330
3.3.6 Watchdog Masked Interrupt Status (WDTMIS) Register, offset 0x014................................... 330
3.3.7 Watchdog Test (WDTTEST) Register, offset 0x418 ........................................................ 331
3.3.8 Watchdog Lock (WDTLOCK) Register, offset 0xC00....................................................... 331
3.3.9 Watchdog Peripheral Identification 4 (WDTPeriphID4) Register, offset 0xFD0 ......................... 332
3.3.10 Watchdog Peripheral Identification 5 (WDTPeriphID5) Register, offset 0xFD4 ........................ 332
3.3.11 Watchdog Peripheral Identification 6 (WDTPeriphID6) Register, offset 0xFD8 ........................ 332
3.3.12 Watchdog Peripheral Identification 7 (WDTPeriphID7) Register, offset 0xFDC........................ 333
3.3.13 Watchdog Peripheral Identification 0 (WDTPeriphID0) Register, offset 0xFE0 ........................ 333
3.3.14 Watchdog Peripheral Identification 1 (WDTPeriphID1) Register, offset 0xFE4 ........................ 333
3.3.15 Watchdog Peripheral Identification 2 (WDTPeriphID2) Register, offset 0xFE8 ........................ 334
3.3.16 Watchdog Peripheral Identification 3 (WDTPeriphID3) Register, offset 0xFEC........................ 334
3.3.17 Watchdog PrimeCell Identification 0 (WDTPCellID0) Register, offset 0xFF0 .......................... 334
3.3.18 Watchdog PrimeCell Identification 1 (WDTPCellID1) Register, offset 0xFF4 .......................... 335
3.3.19 Watchdog PrimeCell Identification 2 (WDTPCellID2) Register, offset 0xFF8 .......................... 335
3.3.20 Watchdog PrimeCell Identification 3 (WDTPCellID3) Register, offset 0xFFC.......................... 335
4 General-Purpose Input/Output (GPIO) ................................................................................. 336
4.1 General-Purpose Input/Output (GPIO)................................................................................. 337
4.1.1 Introduction ....................................................................................................... 337
4.1.2 Signal Description ............................................................................................... 337
4.1.3 Functional Description........................................................................................... 341
4.1.4 Initialization and Configuration................................................................................. 345
4.1.5 Register Map ..................................................................................................... 346
4.1.6 Register Descriptions............................................................................................ 348
4.2 C28 General-Purpose Input/Output (GPIO)........................................................................... 369
4.2.1 Introduction ....................................................................................................... 369
4.2.2 GPIO Module Overview......................................................................................... 369
4.2.3 Configuration Overview ......................................................................................... 375
4.2.4 Digital General Purpose I/O Control........................................................................... 378
4.2.5 Input Qualification................................................................................................ 380

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4.2.6 GPIO and Peripheral Multiplexing (MUX) .................................................................... 384
4.2.7 Register Bit Definitions.......................................................................................... 391
5 Internal Memory................................................................................................................ 425
5.1 RAM Control Module ..................................................................................................... 426
5.1.1 Functional Description........................................................................................... 426
5.2 RAM Control Module Registers......................................................................................... 434
5.2.1 M3 RAM Configuration Registers.............................................................................. 437
5.2.2 M3 RAM Error Registers........................................................................................ 452
5.2.3 C28x RAM Configuration Registers ........................................................................... 465
5.2.4 C28x RAM Error Registers ..................................................................................... 480
5.3 Flash Controller Memory Module....................................................................................... 493
5.3.1 Features........................................................................................................... 493
5.3.2 Flash Tools ....................................................................................................... 493
5.3.3 Default Flash Configuration .................................................................................... 494
5.3.4 Flash Bank, OTP and Pump ................................................................................... 494
5.3.5 Flash Module Controller (FMC)................................................................................ 495
5.3.6 Flash and OTP Automatic Power-Down Modes............................................................. 496
5.3.7 Flash and OTP Performance................................................................................... 497
5.3.8 Flash Read Interface ............................................................................................ 497
5.3.9 Erase/Program Flash............................................................................................ 502
5.3.10 Error Correction Code (ECC) Protection .................................................................... 503
5.3.11 Reserved Locations Within Flash and OTP................................................................. 506
5.3.12 Procedure to Change the Flash Control Registers......................................................... 507
5.4 Flash Registers ........................................................................................................... 508
5.4.1 Master Subsystem Flash Control Registers.................................................................. 512
5.4.2 Master Subsystem Flash ECC/Error Log Registers......................................................... 518
5.4.3 Control Subsystem Flash Control Registers ................................................................. 525
5.4.4 Control Subsystem Flash ECC/Error Log Registers ........................................................ 529
6 ROM Code and Peripheral Booting ..................................................................................... 536
6.1 Introduction ................................................................................................................ 537
6.2 Device Boot Sequence................................................................................................... 537
6.3 Device Boot Modes....................................................................................................... 538
6.3.1 Configuring Alternate Boot Mode Pins........................................................................ 538
6.4 Device Boot Flow Diagram .............................................................................................. 540
6.5 M-Boot ROM Description ................................................................................................ 541
6.5.1 M-Boot ROM Memory Map..................................................................................... 541
6.5.2 M-Boot ROM Vector Table ..................................................................................... 541
6.5.3 M-Boot ROM Version and Checksum Information .......................................................... 542
6.5.4 M-Boot ROM RAM Initialization................................................................................ 542
6.5.5 M-Boot ROM RAM Usage...................................................................................... 543
6.5.6 M-Boot ROM User OTP......................................................................................... 543
6.5.7 M-Boot ROM Entry Points...................................................................................... 544
6.5.8 M-Boot ROM Clock Initialization............................................................................... 546
6.5.9 M-Boot ROM GPIO Assignments for Each Boot Mode..................................................... 546
6.5.10 M-Boot ROM Functional Flow................................................................................. 547
6.5.11 M-Boot ROM Flow Diagram................................................................................... 549
6.5.12 M-Boot ROM Boot Status in RAM for Applications......................................................... 552
6.5.13 M-Boot ROM Reset Cause Handling ........................................................................ 553
6.5.14 M-Boot ROM Exceptions Handling........................................................................... 553
6.5.15 M-Boot ROM Boot Modes ..................................................................................... 554
6.6 C-Boot ROM Description ................................................................................................ 570
6.6.1 C-Boot ROM Memory Map ..................................................................................... 570
6.6.2 C-Boot ROM RAM Initialization................................................................................ 577

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6.6.3 C-Boot ROM RAM Usage ...................................................................................... 577
6.6.4 C-Boot ROM Boot Modes....................................................................................... 578
6.6.5 C-Boot ROM Entry Points ...................................................................................... 579
6.6.6 C-Boot ROM GPIO Assignment for Boot Modes............................................................ 580
6.6.7 C-Boot ROM Clock Initializations.............................................................................. 581
6.6.8 C-Boot ROM Functional Flow.................................................................................. 581
6.6.9 C-Boot ROM MTOC IPC Commands ......................................................................... 584
6.6.10 C-Boot ROM Health Status.................................................................................... 590
6.6.11 C-Boot ROM Boot Status...................................................................................... 591
6.6.12 C-Boot ROM CTOM IPC Messages.......................................................................... 592
6.6.13 C-Boot ROM Handling of Exceptions and PIE Interrupts.................................................. 593
6.6.14 C-Boot ROM Bootloader Functionality ...................................................................... 594
6.7 Guidelines for Boot ROM Application Writers......................................................................... 614
6.7.1 Master Subsystem Application Procedure to Start C-Boot ROM Bootloaders........................... 614
6.7.2 Master Subsystem Application Procedure to Initialize the Control Subsystem RAM Using IPC...... 616
6.8 Application Notes to Use Boot ROM ................................................................................... 619
6.8.1 How to Send Boot Data to M-Boot ROM ..................................................................... 619
6.8.2 C-Boot ROM: Building the Boot Table ........................................................................ 625
7 C28 Enhanced Pulse Width Modulator (ePWM) Module ......................................................... 630
7.1 Introduction ................................................................................................................ 631
7.1.1 Submodule Overview............................................................................................ 632
7.1.2 Register Mapping................................................................................................ 636
7.2 ePWM Submodules ...................................................................................................... 641
7.2.1 Overview.......................................................................................................... 641
7.2.2 Time-Base (TB) Submodule.................................................................................... 643
7.2.3 Counter-Compare (CC) Submodule........................................................................... 653
7.2.4 Action-Qualifier (AQ) Submodule.............................................................................. 660
7.2.5 Dead-Band Generator (DB) Submodule...................................................................... 676
7.2.6 PWM-Chopper (PC) Submodule............................................................................... 683
7.2.7 Trip-Zone (TZ) Submodule ..................................................................................... 687
7.2.8 Event-Trigger (ET) Submodule ................................................................................ 692
7.2.9 Digital Compare (DC) Submodule............................................................................. 699
7.3 Applications to Power Topologies ...................................................................................... 707
7.3.1 Overview of Multiple Modules ................................................................................. 707
7.3.2 Key Configuration Capabilities................................................................................. 707
7.3.3 Controlling Multiple Buck Converters With Independent Frequencies.................................... 708
7.3.4 Controlling Multiple Buck Converters With Same Frequencies............................................ 712
7.3.5 Controlling Multiple Half H-Bridge (HHB) Converters....................................................... 715
7.3.6 Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM).......................................... 717
7.3.7 Practical Applications Using Phase Control Between PWM Modules .................................... 721
7.3.8 Controlling a 3-Phase Interleaved DC/DC Converter....................................................... 722
7.3.9 Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter....................................... 726
7.3.10 Controlling a Peak Current Mode Controlled Buck Module ............................................... 728
7.3.11 Controlling H-Bridge LLC Resonant Converter............................................................. 730
7.4 Registers................................................................................................................... 733
7.4.1 Time-Base Submodule Registers.............................................................................. 733
7.4.2 Counter-Compare Submodule Registers..................................................................... 742
7.4.3 Action-Qualifier Submodule Registers ........................................................................ 749
7.4.4 Dead-Band Submodule Registers............................................................................. 754
7.4.5 PWM-Chopper Submodule Control Register................................................................. 758
7.4.6 Trip-Zone Submodule Control and Status Registers........................................................ 760
7.4.7 Digital Compare Submodule Registers ....................................................................... 767
7.4.8 GPTRIP Input Select Registers................................................................................ 778

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7.4.9 Event-Trigger Submodule Registers .......................................................................... 780
7.4.10 Proper Interrupt Initialization Procedure..................................................................... 789
8 C28 Enhanced Capture (eCAP) Module................................................................................ 790
8.1 Introduction ................................................................................................................ 791
8.2 Description................................................................................................................. 791
8.3 Capture and APWM Operating Mode.................................................................................. 792
8.4 Capture Mode Description............................................................................................... 793
8.4.1 Event Prescaler .................................................................................................. 794
8.4.2 Edge Polarity Select and Qualifier............................................................................. 795
8.4.3 Continuous/One-Shot Control.................................................................................. 795
8.4.4 32-Bit Counter and Phase Control............................................................................. 796
8.4.5 CAP1-CAP4 Registers.......................................................................................... 797
8.4.6 Interrupt Control.................................................................................................. 797
8.4.7 Shadow Load and Lockout Control............................................................................ 798
8.4.8 APWM Mode Operation......................................................................................... 799
8.5 Capture Module - Control and Status Registers...................................................................... 801
8.6 Register Mapping......................................................................................................... 809
8.7 Application of the ECAP Module ....................................................................................... 809
8.7.1 Example 1 - Absolute Time-Stamp Operation Rising Edge Trigger....................................... 810
8.7.2 Example 2 - Absolute Time-Stamp Operation Rising and Falling Edge Trigger ........................ 812
8.7.3 Example 3 - Time Difference (Delta) Operation Rising Edge Trigger..................................... 814
8.7.4 Example 4 - Time Difference (Delta) Operation Rising and Falling Edge Trigger ...................... 816
8.8 Application of the APWM Mode......................................................................................... 818
8.8.1 Example 1 - Simple PWM Generation (Independent Channel/s).......................................... 818
9 C28 Enhanced QEP (eQEP) Module..................................................................................... 820
9.1 Introduction ................................................................................................................ 821
9.2 Description................................................................................................................. 823
9.2.1 EQEP Inputs...................................................................................................... 823
9.2.2 Functional Description........................................................................................... 824
9.2.3 eQEP Memory Map ............................................................................................. 824
9.3 Quadrature Decoder Unit (QDU) ....................................................................................... 826
9.3.1 Position Counter Input Modes.................................................................................. 826
9.3.2 eQEP Input Polarity Selection.................................................................................. 829
9.3.3 Position-Compare Sync Output................................................................................ 829
9.4 Position Counter and Control Unit (PCCU)............................................................................ 829
9.4.1 Position Counter Operating Modes............................................................................ 829
9.4.2 Position Counter Latch.......................................................................................... 831
9.4.3 Position Counter Initialization .................................................................................. 833
9.4.4 eQEP Position-compare Unit................................................................................... 834
9.5 eQEP Edge Capture Unit................................................................................................ 835
9.6 eQEP Watchdog .......................................................................................................... 839
9.7 Unit Timer Base........................................................................................................... 839
9.8 eQEP Interrupt Structure ................................................................................................ 840
9.9 eQEP Registers........................................................................................................... 840
10 Analog Subsystem............................................................................................................ 854
10.1 Overview................................................................................................................... 855
10.2 Analog Common Interface Bus (ACIB) ................................................................................ 855
10.3 Analog-to-Digital Converter (ADC) ..................................................................................... 859
10.3.1 Features.......................................................................................................... 859
10.3.2 Block Diagram................................................................................................... 860
10.3.3 SOC Principle of Operation ................................................................................... 860
10.3.4 ONESHOT Single Conversion Support...................................................................... 864
10.3.5 ADC Conversion Priority....................................................................................... 865

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10.3.6 Simultaneous Sampling Mode ................................................................................ 868
10.3.7 EOC and Interrupt Operation.................................................................................. 868
10.3.8 Power Up Sequence ........................................................................................... 869
10.3.9 ADC Calibration................................................................................................. 869
10.3.10 Internal/External Reference Voltage Selection............................................................ 871
10.3.11 ADC Registers................................................................................................. 872
10.3.12 Analog Subsystem Control Registers ...................................................................... 889
10.3.13 ADC Timings................................................................................................... 898
10.4 Comparator Block......................................................................................................... 901
10.4.1 Features......................................................................................................... 901
10.4.2 Comparator Block Diagram.................................................................................... 902
10.4.3 Comparator Function........................................................................................... 902
10.4.4 DAC Reference ................................................................................................. 902
10.4.5 Initialization ...................................................................................................... 903
10.4.6 Digital Domain Manipulation .................................................................................. 903
10.4.7 Comparator Registers.......................................................................................... 904
10.5 Analog Subsystem Software ............................................................................................ 906
10.5.1 C28 Analog Subsystem Functions ........................................................................... 906
10.5.2 C28 Analog Subsystem Software Example ................................................................. 908
10.5.3 M3 Analog Subsystem Functions............................................................................. 908
10.5.4 M3 Analog Subsystem Software Example .................................................................. 909
11 C28 Direct Memory Access (DMA) Module .......................................................................... 911
11.1 Introduction ................................................................................................................ 912
11.2 Architecture................................................................................................................ 912
11.2.1 Block Diagram................................................................................................... 912
11.2.2 Peripheral Interrupt Event Trigger Sources ................................................................. 913
11.2.3 DMA Bus......................................................................................................... 915
11.3 Pipeline Timing and Throughput........................................................................................ 916
11.3.1 DMA Read Access of ADC Registers........................................................................ 917
11.4 CPU Arbitration ........................................................................................................... 917
11.4.1 Arbitration when Accessing the Analog Subsystem........................................................ 918
11.5 Channel Priority........................................................................................................... 918
11.5.1 Round-Robin Mode............................................................................................. 918
11.5.2 Channel 1 High Priority Mode................................................................................. 919
11.6 Address Pointer and Transfer Control ................................................................................. 920
11.7 Overrun Detection Feature .............................................................................................. 924
11.8 Register Descriptions..................................................................................................... 926
11.8.1 DMA Control Register (DMACTRL) — EALLOW Protected .............................................. 927
11.8.2 Debug Control Register (DEBUGCTRL) — EALLOW Protected......................................... 929
11.8.3 Revision Register (REVISION) ............................................................................... 929
11.8.4 Priority Control Register 1 (PRIORITYCTRL1) — EALLOW Protected ................................. 930
11.8.5 Priority Status Register (PRIORITYSTAT) .................................................................. 931
11.8.6 Mode Register (MODE) — EALLOW Protected............................................................ 932
11.8.7 Control Register (CONTROL) — EALLOW Protected..................................................... 934
11.8.8 Burst Size Register (BURST_SIZE) — EALLOW Protected.............................................. 936
11.8.9 BURST_COUNT Register ..................................................................................... 936
11.8.10 Source Burst Step Register Size (SRC_BURST_STEP) — EALLOW Protected .................... 937
11.8.11 Destination Burst Step Register Size (DST_BURST_STEP) — EALLOW Protected................ 938
11.8.12 Transfer Size Register (TRANSFER_SIZE) — EALLOW Protected ................................... 938
11.8.13 Transfer Count Register (TRANSFER_COUNT) ......................................................... 939
11.8.14 Source Transfer Step Size Register (SRC_TRANSFER_STEP) — EALLOW Protected ........... 939
11.8.15 Destination Transfer Step Size Register (DST_TRANSFER_STEP) — EALLOW Protected....... 940
11.8.16 Source/Destination Wrap Size Register (SRC/DST_WRAP_SIZE) — EALLOW protected)........ 940

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11.8.17 Source/Destination Wrap Count Register (SCR/DST_WRAP_COUNT) .............................. 941
11.8.18 Source/Destination Wrap Step Size Registers (SRC/DST_WRAP_STEP) — EALLOW Protected 941
11.8.19 Shadow Source Begin and Current Address Pointer Registers
(SRC_BEG_ADDR_SHADOW/DST_BEG_ADDR_SHADOW) — All EALLOW Protected............ 942
11.8.20 Active Source Begin and Current Address Pointer Registers
(SRC_BEG_ADDR/DST_BEG_ADDR)....................................................................... 942
11.8.21 Shadow Destination Begin and Current Address Pointer Registers
(SRC_ADDR_SHADOW/DST_ADDR_SHADOW) — All EALLOW Protected .......................... 943
11.8.22 Active Destination Begin and Current Address Pointer Registers (SRC_ADDR/DST_ADDR) ..... 943
12 C28 Serial Peripheral Interface (SPI).................................................................................... 944
12.1 Enhanced SPI Module Overview ....................................................................................... 945
12.1.1 SPI Block Diagram ............................................................................................. 946
12.1.2 SPI Module Signal Summary.................................................................................. 948
12.1.3 Overview of SPI Module Registers........................................................................... 948
12.1.4 SPI Operation ................................................................................................... 949
12.1.5 SPI Interrupts.................................................................................................... 951
12.1.6 SPI FIFO Description........................................................................................... 956
12.1.7 SPI 3-Wire Mode Description ................................................................................. 958
12.1.8 SPI STEINV Bit in Digital Audio Transfers .................................................................. 960
12.2 C28 SPI-A to M3 SSI3 Internal Loopback............................................................................. 961
12.2.1 Loopback Initialization and Configuration ................................................................... 962
12.3 SPI Registers and Waveforms.......................................................................................... 964
12.3.1 SPI Control Registers .......................................................................................... 964
12.3.2 SPI Example Waveforms...................................................................................... 973
13 C28 Serial Communications Interface (SCI).......................................................................... 979
13.1 Enhanced SCI Module Overview ....................................................................................... 980
13.1.1 Architecture...................................................................................................... 982
13.2 C28 SCI-A to M3 UART4 Internal Loopback.......................................................................... 992
13.2.1 Loopback Initialization and Configuration ................................................................... 993
13.3 SCI Registers.............................................................................................................. 994
13.3.1 SCI Module Register Summary............................................................................... 994
13.3.2 SCI Communication Control Register (SCICCR)........................................................... 995
13.3.3 SCI Control Register 1 (SCICTL1) ........................................................................... 996
13.3.4 SCI Baud-Select Registers (SCIHBAUD, SCILBAUD) .................................................... 998
13.3.5 SCI Control Register 2 (SCICTL2) ........................................................................... 999
13.3.6 SCI Receiver Status Register (SCIRXST)................................................................... 999
13.3.7 Receiver Data Buffer Registers (SCIRXEMU, SCIRXBUF) ............................................. 1001
13.3.8 SCI Transmit Data Buffer Register (SCITXBUF).......................................................... 1002
13.3.9 SCI FIFO Registers (SCIFFTX, SCIFFRX, SCIFFCT) ................................................... 1002
13.3.10 Priority Control Register (SCIPRI)......................................................................... 1006
14 C28 Inter-Integrated Circuit Module................................................................................... 1007
14.1 Introduction to the I2C Module ........................................................................................ 1008
14.1.1 Features........................................................................................................ 1009
14.1.2 Features Not Supported...................................................................................... 1009
14.1.3 Functional Overview .......................................................................................... 1009
14.1.4 Clock Generation.............................................................................................. 1010
14.2 I2C Module Operational Details ....................................................................................... 1011
14.2.1 Input and Output Voltage Levels............................................................................ 1011
14.2.2 Data Validity ................................................................................................... 1011
14.2.3 Operating Modes.............................................................................................. 1012
14.2.4 I2C Module START and STOP Conditions ................................................................ 1013
14.2.5 Serial Data Formats........................................................................................... 1013
14.2.6 NACK Bit Generation......................................................................................... 1015

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10 SPRUH22I–April 2012–Revised November 2019
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Contents
14.2.7 Clock Synchronization........................................................................................ 1016
14.2.8 Arbitration ...................................................................................................... 1016
14.3 Interrupt Requests Generated by the I2C Module.................................................................. 1017
14.3.1 Basic I2C Interrupt Requests................................................................................ 1017
14.3.2 I2C FIFO Interrupts ........................................................................................... 1018
14.4 Resetting/Disabling the I2C Module .................................................................................. 1018
14.5 I2C Module Registers................................................................................................... 1019
14.5.1 I2C Mode Register (I2CMDR) ............................................................................... 1020
14.5.2 I2C Extended Mode Register (I2CEMDR) ................................................................. 1023
14.5.3 I2C Interrupt Enable Register (I2CIER) .................................................................... 1025
14.5.4 I2C Status Register (I2CSTR)............................................................................... 1025
14.5.5 I2C Interrupt Source Register (I2CISRC) .................................................................. 1028
14.5.6 I2C Prescaler Register (I2CPSC)........................................................................... 1029
14.5.7 I2C Clock Divider Registers (I2CCLKL and I2CCLKH) .................................................. 1029
14.5.8 I2C Slave Address Register (I2CSAR)..................................................................... 1031
14.5.9 I2C Own Address Register (I2COAR)...................................................................... 1031
14.5.10 I2C Data Count Register (I2CCNT) ....................................................................... 1032
14.5.11 I2C Data Receive Register (I2CDRR) .................................................................... 1032
14.5.12 I2C Data Transmit Register (I2CDXR).................................................................... 1032
14.5.13 I2C Transmit FIFO Register (I2CFFTX) .................................................................. 1033
14.5.14 I2C Receive FIFO Register (I2CFFRX)................................................................... 1034
15 C28 Multichannel Buffered Serial Port (McBSP).................................................................. 1036
15.1 Overview.................................................................................................................. 1037
15.1.1 Features of the McBSP....................................................................................... 1037
15.1.2 McBSP Pins/Signals.......................................................................................... 1038
15.1.3 McBSP Operation............................................................................................. 1039
15.1.4 Data Transfer Process of McBSP........................................................................... 1040
15.1.5 Companding (Compressing and Expanding) Data........................................................ 1040
15.2 Clocking and Framing Data............................................................................................ 1042
15.2.1 Clocking ........................................................................................................ 1042
15.2.2 Serial Words ................................................................................................... 1042
15.2.3 Frames and Frame Synchronization........................................................................ 1043
15.2.4 Generating Transmit and Receive Interrupts.............................................................. 1043
15.2.5 Ignoring Frame-Synchronization Pulses ................................................................... 1043
15.2.6 Frame Frequency ............................................................................................. 1044
15.2.7 Maximum Frame Frequency................................................................................. 1044
15.3 Frame Phases ........................................................................................................... 1044
15.3.1 Number of Phases, Words, and Bits Per Frame.......................................................... 1045
15.3.2 Single-Phase Frame Example............................................................................... 1045
15.3.3 Dual-Phase Frame Example................................................................................. 1045
15.3.4 Implementing the AC97 Standard With a Dual-Phase Frame........................................... 1046
15.3.5 McBSP Reception............................................................................................. 1046
15.3.6 McBSP Transmission......................................................................................... 1048
15.3.7 Interrupts and DMA Events Generated by a McBSP..................................................... 1049
15.4 McBSP Sample Rate Generator ...................................................................................... 1049
15.4.1 Block Diagram................................................................................................. 1050
15.4.2 Frame Synchronization Generation in the Sample Rate Generator.................................... 1053
15.4.3 Synchronizing Sample Rate Generator Outputs to an External Clock................................. 1053
15.4.4 Reset and Initialization Procedure for the Sample Rate Generator .................................... 1055
15.5 McBSP Exception/Error Conditions................................................................................... 1056
15.5.1 Types of Errors ................................................................................................ 1056
15.5.2 Overrun in the Receiver...................................................................................... 1056
15.5.3 Unexpected Receive Frame-Synchronization Pulse ..................................................... 1058