Texas Instruments LMX1906-SP User manual

EVM User's Guide: LMX1906EVM-CVAL
LMX1906-SP Evaluation Module
Description
The LMX1906-SP evaluation module (EVM) is
designed to evaluate the performance of the
LMX1906-SP, which is a four-output, ultra-low
additive jitter radio-frequency (RF) buffer, divider and
multiplier. The device can buffer RF frequencies up
to 18 GHz, multiply RF outputs up to 6.4 GHz,
and divide outputs by up to 6.4 GHz. This board
consists of an LMX1906-SP device and an integrated
USB2ANY programmer.
Features
• 300-MHz to 18-GHz output frequency
• 4 high-frequency clocks with corresponding
SYSREF outputs
– Shared divide by 2, 3, 4, 5, 6, 7 and 8
– Shared programmable multiplier ×2, ×3, and ×4
• 3.3-V supply voltage (with onboard 2.5-V LDOs) or
2.5-V supply voltage (with LDOs bypassed)
• –55ºC to +125ºC operating temperature (with
onboard MCU bypassed)
• Optional pin mode control without register
programming
Applications
• General purpose:
– Data converter clocking
– Clock distribution/multiplication/division
• Aerospace and defense:
–Radar
–Electronic warfare
–Seeker front end
– Phased array antenna/beam forming
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1 Evaluation Module Overview
1.1 Introduction
The LMX1906-SP EVM is an ultra-low additive-jitter RF buffer, divider, and multiplier, with integrated SYSREF
generation capability. A separate auxiliary clock divider can be used for FPGAs or other logic ICs. Each RF
output (and the logic clock) is paired with a complementary SYSREF output with picosecond-precision delay-
tuning capability, and can be operated as a generator (with synchronization capability across multiple devices) or
as a repeater.
The EVM can be operated with a 3.3-V supply voltage when the onboard LDOs are utilized. The LDOs can be
bypassed, in this case the supply voltage is 2.5-V.
The EVM contains LMX1906-SP, two LDOs, a microcontroller and an IO expander. LMX1906-SP and the LDOs
can support –55ºC to +125ºC operation. For high temperature evaluation, use an USB2ANY dongle to control
the EVM.
1.2 Kit Contents
Included within each evaluation kit is:
• One LMX1906-SP EVM board (DC238) with integrated USB2ANY controller
• One USB cable
1.3 Specification
Table 1-1. LMX1906-SP EVM Specification
Parameter Value Conditions
Supply voltage (VCCIN SMA) 3.1 V to 3.5 V On-board voltage regulator outputs are 2.5 V
Supply current 1.3 A max. Various configurations
CLKIN input frequency
300 MHz to 18 GHz Buffer mode
150 MHz to 6.4 GHz Divider mode
3.2 to 6.4 GHz
Multiplier mode
CLK_MULT = ×1
1.6 to 3.2 GHz CLK_MULT = ×2
1.066 to 2.133 GHz CLK_MULT = ×3
800 MHz to 1.6 GHz CLK_MULT = ×4
1.4 Device Information
The high-frequency capability and extremely low jitter of this device, makes a great design to clock precision,
high-frequency data converters without degradation to the signal-to-noise ratio. Each of the four high-frequency
clock outputs, and additional LOGICLK output with larger divider range, is paired with a SYSREF output clock
signal. The SYSREF signal for JESD interfaces can either be internally generated or passed in as an input and
re-clocked to the device clocks. For data converter clocking applications, to have the jitter of the clock be less
than the aperture jitter of the data converter is critical. In applications where more than four data converters must
be clocked, a variety of cascading architectures can be developed using multiple devices to distribute all the
high-frequency clocks and SYSREF signals required. With low jitter and noise floor, this device combined with
an ultra-low noise reference clock source is an exemplary design for clocking data converters, especially when
sampling above 3 GHz.
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2 Hardware
2.1 Setup
2.1.1 Evaluation Setup Requirement
At a minimum, evaluation of the buffer mode requires:
• A DC power supply capable of at least 3.1 V, 2 A
• A high-quality signal source, such as an SMA100B
• A spectrum analyzer or signal analyzer
• A PC with a USB port, running Windows 7 or a more recent version of Windows
• Texas Instruments Clocks and Synthesizers TICS Pro software
Full evaluation requires the following additional hardware:
• A high-speed 4-CH oscilloscope capable of resolving 5-ps step size for SYSREF delay tuning
• A 2-CH arbitrary function generator or other pulse source capable of outputting complementary LVDS pulses
and DC levels (1.25 V ± 0.2 V, differential, into 100-Ω DC load) for triggering SYSREF, SYNCing the dividers,
and determining SYSREF windowing values
• A phase noise analysis system capable of measuring at up to 18 GHz
2.1.2 Connection Diagram
50Ω
50Ω 50Ω 50Ω
Power Supply
3.3V, 2A
2-CH Arbitrary
Function Generator
1.3V ± 0.2V
High-Quality Signal
Generator
PC with TICSPro &
device profile installed
50Ω
50Ω
Balun
Signal Analyzer
50Ω
50Ω
50Ω
50Ω
4-CH
Oscilloscope
50Ω
50Ω
50Ω
50Ω
TP14
TP16
J14
TP11
TP10
TP1
TP6
TP4 TP9
TP5
TP12
TP7
J29
J28
J40
Figure 2-1. EVM Connection Diagram
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Table 2-1. SPI Test Points
Test Point Net
TP1 SDO
TP4 CSB
TP5 SCK
TP6 SDI
TP9 CE
Table 2-2. I2C Testpoints for IO Expander
Test Point Net
TP10 SDA
TP11 SCL
Table 2-3. Supply Voltage Test Points
Test Point Net
TP7 VCC01_23
TP12 VCC_CLK_LOGIC
TP14 VCC_PinM
TP16 VCC_BIAS
Table 2-4. VCC Power Jumpers
Header Net Short Position Configuration
J14 CE
1-2 (EVM default) CE pulled high via 10 kΩ resistor results in LMX1909-SP enabled
2-3 External CE signal from USB2ANY in TICSpro 'pin' tab
J28 VCC_BYPASS or 1st LDO
2-3 (EVM default) Use on-board LDOS
1-2 Direct Supply from J23 (VCCIN) SMA connector
J29 VCC_IN or VCC_BYPASS
2-3 (EVM default) Use on-board LDOS
1-2 Direct Supply from J23 (VCCIN) SMA connector
J40 VCC_IN or 2nd LDO 2-3 (EVM default) Use on-board LDOS
1-2 Direct Supply from J23 (VCCIN) SMA connector
Table 2-5. Pin Control Jumpers (IO Expander Configurable)
Jumper Short position Configuration
SYSREFEN (Acts as CE pin for
entire SYSREF sub-system)
J38-J39 (Pulled HIGH) When SYSREFEN is set to HIGH, the entire SYSREF sub-system is
enabled with register defaults set accordingly. SPI can still be used to
disable.
J37-J38 (Pulled LOW) When SYSREFEN is set to low, the entire SYSREF sub-system is
deactivated and SPI cannot re-enable.
LOGICEN (Acts as CE pin for
LOGICH)
J38-J39 (Pulled HIGH) When LOGICEN is set to HIGH, the entire SYSREF sub-system is
enabled with register defaults set accordingly. SPI can still be used to
disable.
J37-J38 (Pulled LOW) When LOGICEN is set to low, all FPGA/LOGIC circuits and the
SYSREF sub-system are deactivated and SPI cannot re-enable.
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Table 2-6. Pin State Headers (IO Expander Configurable)
Header Short Position Configuration
PWRSEL[2:0]
000 Output power configurable via SPI
001 - Lowest output power
Pin Mode (Also controllable via IO expander)⋮
111 - Highest Output Power
CLKx_EN Pulled LOW (GND) J31-J32 Disables corresponding CLKOUTx
Pulled HIGH (VCC) J32-J33 Enables corresponding CLKOUTx
CAL Transition from LOW to HIGH Calibrates the multiplier or Resets the divider
LOW Calibration & Reset controllable via SPI
WARNING
If the user wishes to use IO expander, then make sure that no shorts are present on any of the
header pins. Otherwise, the IO expander or the MCU is damaged.
The onboard TCA9535 IO expander allows the user to change pin states without the need of physical shorts on
the header pin. This allows users to toggle pin modes through the GUI as well. If the user wishes to evaluate the
LMX1906-SP without MCU control (physical pin strapping), then make sure no jumpers are present on any of the
pin state headers.
USB POWER needs to be provided if LDOs utilization is desired. VCCIN can have a 3.3 V supply connected but,
if the USB cable is disconnected, then the board is without power.
Table 2-7. Usage Modes
Usage Configuration
With USB & DUT LDOs
• Short J28, J29 and J40 jumpers to LDO
• Apply 3.3 V to VCCIN
• Apply USB connection
Without USB & DUT LDOs
• Short J28, J29 and J40 jumpers to LDO
• Apply 3.3 V to VCCIN
• Apply 5 V to VBIAS (TP16) - To avoid damage to host pc usb port, do not apply
external source to vbias unless usb is disconnected or r44 has been removed.
With USB & DUT LDOs bypassed
• Short J28, J29 and J40 jumpers to bypass
• Apply 2.5 V to VCCIN
• Apply USB connection
Without USB & DUT LDOs bypassed
• Short J28, J29 and J40 jumpers to LDO
• Apply 2.5 V to VCCIN
Note
SPI reading while using DUT LDOs: 3.3 V supply can prevent SPI read-back from functioning as
intended. Make sure the input voltage to U7 is larger than 0.7 * VCCIN and that output voltage of U7 is
greater than 2.31 V.
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2.1.2.1 How to Enable Full SPI Control
Short positions for full SPI control (not using IO expander).
Header Short Position Configuration
PWRSEL[2:0] 000 Output power configurable via SPI.
CLKx_EN Pulled HIGH (VCC) Enables corresponding CLKOUTx, SPI can still disable each output.
MUXSEL[1:0] 000 MUXSEL controlled via SPI.
DIVSEL[2:0] 000 DIVSEL controlled via SPI.
SYSREF_EN Pulled HIGH (VCC) Enables entire SYSREF system which is controlled via SPI.
LOGICEN Pulled HIGH (VCC) Enables entire LOGICLK system which is controllable via SPI.
2.1.3 Power Requirements
Apply 3.3 V to the J23 header. The acceptable supply voltage range is 3.1 V to 3.5 V, and the board can draw
up to 1.3 A during operation, so the resistance of the cable is matter. The on-board LDOs have about 40 mA
ground current for converting 3.3 V to 2.5 V supply. Furthermore, enabling or disabling various system functions
can change the board current by 50 % or more.
2.1.4 Pin Mode Strapping
Mode of Operation Jumper Position Multiplier/Divider Short
Position
Multiplier/Divider Value Short
Position
Multiplier mode Short MUXSEL[1:0] to VCC (J35-
J36)
Short DIVSEL[0] & DIVSEL[2] to
GND & short DIVSEL[1] to VCC
x2 Multiplier value
Short DIVSEL[2] to GND x3 Multiplier value
Short DIVSEL[1:0] to GND &
DIVSEL[2] to VCC
x4 Multiplier Value
Divider mode Short MUXSEL[0] to GND
Short DIVSEL[2:1] to GND Div by 2
Short DIVSEL[0] & DIVSEL[2] to
GND
Div by 3
Short DIVSEL[2] to GND Div by 4
Short DIVSEL[1:0] to GND Div by 5
Short DIVSEL[1] to GND Div by 6
Short DIVSEL[0] to GND Div by 7
DIVSEL [2:0] float Div by 8
Buffer mode Short MUXSEL[1] to GND N/A
Note
1. In multiplier mode, A LOW to HIGH transition on CAL header must be done. This is accomplished
using a short on CAL header pin (J38) to VCC.
2. Only divider values of 2/3/4 are available in pin mode. Divider values of 5 , 6 , 7 & 8 are valid
divider values only when in SPI mode.
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2.1.5 Reference Clock
Connect the CLKINP SMA connector to a high-quality signal source such as an SMA100B signal generator. Both
CLKIN inputs are terminated internally with 50 Ω to AC-GND (that is, GND connection is formed by an internal
capacitor), so no external termination is required or recommended. Input can be driven differentially, connect
both CLKINP and CLKINN SMA connectors to a balun or a differential clock source.
The default EVM profile configures the device in buffer mode. Logiclk is on by default with a predefined output
divider value of 128. The input frequency can be modified per the operating range of each functional element if
desired. This EVM setup guide and related plots assume 800-MHz input at CLKIN for buffer mode.
To evaluate SYSREF repeater mode, connect the SYSREF input SMAs to a differential output source such
as an arbitrary function generator. The EVM connections for the SYSREF input are DC-coupled and provide
internal 100-Ω termination with several biasing options. At POR, the EVM automatically applies a weak 1.3-V
common mode bias to the SYSREFREQ pins. However, the default EVM profile configures the SYSREF input
for DC-coupled input. In DC-coupled mode, the common mode bias on the SYSREFREQ pins must be between
1 V and 2 V. The input common mode requirements can be fulfilled with a standard LVDS output buffer.
For evaluating SYNC mode and SYSREF windowing, to have a SYSREFREQ input source capable of
consistently meeting setup and hold requirements for a single cycle of the input clock is critical. This can become
very challenging at higher frequencies where set up and hold requirements can be < 50 ps. Another device
capable of picosecond-precision timed pulses, such as LMX2820 or LMX2594, can be used as a reference input
to both CLKIN and SYSREF for evaluating these features.
2.1.5.1 Output Connections
All CLKOUT connections are AC-coupled at the LMX1906-SP EVM and can be connected directly to RF
instruments with 0VDC requirements; an additional DC block is not required. The unused CLKOUT SMA
connector must be terminated with a 50-Ω load, or a differential connection can be used if a balun with the
best frequency range is available.
Recommended oscilloscope connections include one CLKOUT and one SYSREF output from the same channel,
as well as the one LOGICLK and one LOGISYS output.
Other unused CLKOUT SMA connectors must be terminated with 50-Ω single-ended or 100-Ω differential load,
or alternately must be disabled in software, to minimize unterminated output effects on performance.
2.1.5.2 Header Information
The LMX1906-SP EVM can be operated in either pin mode or SPI mode. Pin mode allows basic configuration
of the LMX1906-SP device without the need of a microcontroller. SPI mode provides full customization of the
LMX1906-SP device. Mode of operation is set via on-board headers J31 to J39 which can also be controlled
via the IO expander, more information on this can be found in Section 2.1.5.7. Other headers are used to select
power supply source and set the CE pin.
2.1.5.3 Default Configuration
The LMX1906-SP EVM silicon default is buffer mode with all outputs enabled with maximum output power. SPI
is disabled in this mode assuming no jumpers are being utilized and neither the IO expander. LOGICLOCK is
also enabled in this mode with a fixed divider value of 128.
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2.1.5.4 How to Generate SYSREF
To generate a continuous SYSREF signal proceed with the following steps:
1. Set SRREQ_MODE (R14[2:1] ) = SYSREFREQ (0x1)
2. Set SYSREF_MODE (R17[1:0]) = Generator Mode Continuous (0x1)
Figure 2-2. How to Enable Continuous SYSREF and Set SYSREFREQ
3. Set SYSREFREQ_FORCE (R72[2:1]) = HIGH
Figure 2-3. SYSREFREQ_FORCE
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2.1.5.5 Multiplier Mode Example
To set LMX1906-SP to multiplier mode by using SPI, follow the steps below:
Set CLK_MUX (R25[2:0] = Multiplier (0x3).
Figure 2-4. Selecting Multiplier Mode
Set CLK_MULT (R25[5:3]) to appropriate multiplier value for respective CLKIN frequency.
Figure 2-5. Selecting Multiplier Value
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Press Calibrate Multiplier button in GUI.
Figure 2-6. Calibrate Multiplier
2.1.5.6 Divider Mode Example
To set LMX1906-SP to divider mode via SPI do the following:
Set CLK_MUX (R25[2:0] = Divider (0x2).
Refer to image above in Section 2.1.5.5.
Set CLK_DIV (R25[5:3]) to appropriate divider value for respective CLKIN frequency.
Figure 2-7. Divider Value
The CLKIN frequency divided by respective divider value at CLKOUTx is now available for viewing.
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2.1.5.7 Hybrid Mode: SPI and Pin Mode
Make sure that no shorts are connected to either GND or VCC on any of the pin mode headers. Once the
user has verified that no pins have been shorted and the threat of destroying the IO expander or MCU has
been eliminated, then provide power using any of the four scenarios described Table 2-7. Current draw must be
approximately 0.9 V after power is applied.
Next, the user must configure the IO expander. This is done by pressing the Configure Driver button in the GUI
under the light green PIN MODES section.
Figure 2-8. Config of TCA9535
Successful configuration of the IO expander results in a TCA9535 one-time configuration complete. Re-run if
USB2ANY is disconnected.
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Figure 2-9. Successful Configuration of TCA9535
The user is now able to change the states of the pin mode headers via the IO expander by pulling pins either
LOW or HIGH directly without the need of a physical short.
CLKx_EN and Device mode options.
Figure 2-10. Pin Mode Options
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Chooses RF output power for all CLKOUTx.
Figure 2-11. pinPWRSEL
Chooses the corresponding divider value when in divider mode or multiplier value in multiplier mode.
Figure 2-12. pinDIVSEL
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3 Software
3.1 Software Installation
Download and install TICS Pro software from www.ti.com/tool/ticspro-sw.
3.2 Software Description
Texas Instruments Clocks and Synthesizers (TICS) Pro software is used to program this evaluation module
(EVM) through the on-board USB2ANY interface.
3.3 USB2ANY Interface
The on-board USB2ANY interface provides a bridge between TICS Pro software and the LMX1906-SP device.
When the on-board USB2ANY controller is first connected to a PC, or if the firmware revision for the controller
does not match with the version used by TICS Pro, a firmware update to the controller is required.
1. Connect the USB cable from the PC to the EVM. The USB interface provides the necessary power to enable
the on-board USB2ANY controller.
2. After Windows has set up a USB device, run TICS Pro in the PC.
3. The next screen looks like the image below.
Figure 3-1. Firmware Update
4. Click OK, then the screen looks like the image below. Click Update Firmware.
Figure 3-2. Firmware Loader
5. Then the screen below appears.
Figure 3-3. Firmware Update Complete
6. Click the Close button to close the window.
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7. A TICS Pro default device pops up. Check to make sure that we get a green light on Connection Mode at the
bottom of the GUI.
Figure 3-4. Connection Mode
8. Go to the menu bar, click USB communications, then select Interface.
Figure 3-5. USB Communications
9. Click the Identify button, the LED in the USB2ANY interface flashes.
Figure 3-6. Identify USB2ANY Controller
10. Now, the USB2ANY is ready to use. Click the Close button to close the window.
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4 Implementation Results
4.1 Buffer, Divider, and Multiplier Modes
From the top-menu, click Default Configuration → 800 MHz Buffer Mode. This automatically loads the buffer
mode profile.
Figure 4-1. Loading the Default Configuration
If termination is not applied on all output pins, then manually disable the unused outputs using the CHx_EN
fields (to completely power down unused channels) or the CLKOUTx_EN, SYSOUTx_EN, and LOGICLK_EN/
LOGISYS_EN fields (to power down output buffers only). Powering down unused channels greatly reduces
current consumption, and for the logic clocks in particular can reduce spurious interference.
After the profile is loaded and required any changes have been made, the signal analyzer shows an 800-MHz
signal at around +6-dBm single-ended, or +9-dBm differential.
The blue trace is the reference clock from SMA100B and the yellow trace is the 800 MHz buffered output.
Figure 4-2. 800-MHz Buffer Mode Signal Analyzer Plot
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To activate the multiplier or the divider, change the CLK_MUX field to specify divider or multiplier modes, and
change the CLK_DIV and CLK_MULT fields to specify the frequency scaling factor. To make sure the device
cleanly enters each mode, first, the desired configuration must be prepared in the GUI. Then, from the User
Controls page the device must be reset by toggling the RESET field, and finally the registers must be reloaded
using the USB Communications → Write All Registers menu option, or by pressing the accelerator keys CTRL +
L.
The yellow trace is the 400 MHz divided output.
Figure 4-3. 800-MHz Divide-by-2 Mode Signal Analyzer Plot
The yellow trace is the 3200 MHz output.
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Figure 4-4. 800-MHz Multiplier x4 Mode Signal Analyzer Plot
4.2 SYSREF Generation
The SYSREF generation circuit includes a SYSREF pre-divider and post-divider, a pulser with programmable
pulse quantity, and a repeater mode bypass. The SYSREF generator modes re-time the SYSREF signal to the
output clock, verifying the SYSREF output is close to the falling edge of the clock output with default delay
settings. Repeater mode timing is solely determined by the propagation delay of the device.
To activate the SYSREF generation circuit, the following conditions must be satisfied:
• SRREQ_MODE field must be set to SYSREFREQ mode.
• SYSREF_MODE field must be set to the appropriate condition: Continuous, Pulser, or Repeater.
• In generator modes (continuous or pulser), FINTERPOLATOR % FSYSREF = 0 must be verified.
• SYSREF_DLY_BYP field must be configured appropriately for generator or repeater modes (a GUI autoset
condition normally verifies this whenever SYSREF_MODE is set).
• SRREQ_VCM field must be set to DC-coupled mode for continuous or pulsed generator output. In repeater
mode output, the SYSREF input can be AC- or DC-coupled and SRREQ_VCM must be set accordingly.
• For continuous mode, a HIGH signal must be seen on SYSREFREQ pins continuously. For pulsed generator
mode, a LOW→HIGH transition must be seen on SYSREFREQ pins to trigger the pulser. For repeater mode,
the output follows the input state.
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Figure 4-5. 800-MHz Buffer Mode With 10 MHz SYSREF
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4.3 SYSREF Delay Generators
In generator modes, the SYSREF can be delayed by picosecond-size steps to more closely meet setup and hold
requirements for high-frequency clock outputs. A delay divider, SYSREF_DLY_DIV, generates the interpolator
frequency fINTERPOLATOR, which is usually in the range of 400 MHz to 800 MHz. This interpolator frequency is
further subdivided into 512 delay codes, allowing approximately 2.5-ps to 5-ps delay steps across most of the
CLKIN frequency range.
Each channel has delay codes, which can be entered. The delay code algorithm is documented in the data
sheet. To simplify delay calculation, the GUI provides an estimated relative delay: enter the relative delay, and
the GUI calculates the correct step values to achieve the requested delay as closely as possible. Alternately, the
register-based delay fields can be stepped through or programmed to achieve the same result.
Figure 4-6. SYSREF Delay in 5-Code Steps
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