Texas Instruments TMDSCNCD263-PMIC User manual

EVM User's Guide: TMDSCNCD263-PMIC
AM263x Control Card with PMIC and Automotive Ethernet
Description
The AM263x Control Card Evaluation Module
(EVM) is an evaluation and development board for
the Texas Instruments Sitara™ AM263x series of
microcontrollers (MCUs). This EVM provides an easy
way to start developing on the AM263x MCUs with
on-board emulation for programming and debugging
as well as buttons and LEDs for a simple user
interface. This version of the AM263x Control Card
(TMDSCNCD263-PMIC) has all of the qualities of
the original AM263x Control Card (TMDSCNCD263)
while also incorporating a PMIC power solution and
replacing two of the Industrial Ethernet PHYs plus
RJ45 connectors with Automotive Ethernet PHYs plus
MATEnet connectors. The control card also enables
header pin access to key signals through the use
of a high speed edge connector (HSEC) baseboard
docking station for rapid prototyping.
Features
•Integrated power and safety monitoring
solution that is consistent with the ISO26262
ASIL-D specification
–Multirail Power Supply designed for Safety-
Relevant Applications
–Automotive, dual-channel voltage
supervisor with very-high accuracy
•Two MATEnet connectors with on-board
Automotive Ethernet PHYs
• One RJ45 ethernet port with on-board Industrial
Ethernet PHY
• PCB dimensions: 131.15 mm width by 92.81 mm
length + 6.17 mm length of HSEC interface
• Powered through 5 V, 3 A USB type-C input
• On-board XDS110 debug probe
• 180 pin HSEC interface for rapid prototyping
• Three push buttons:
– PORz
– User interrupt
– RESETz
• LEDs for:
– Power status
– User testing
– Ethernet connection
– I2C driven array
• CAN connectivity with on-board CAN transceiver
• LIN connectivity with on-board LIN transceiver
• Dedicated FSI connector
• TI Test Automation Header
• MMC interface to micro SD card connector
• On-board memory
– 128 MB QSPI Flash
– 1 MB I2C EEPROM
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1 Evaluation Module Overview
Preface: Read This First
1.1.1 Sitara™ MCU+ Academy
Texas Instruments™ offers the MCU+ Academy as a resource for designing with the MCU+ software and tools
on supported devices. The MCU+ Academy features easy-to-use training modules that range from the basics of
getting started to advanced development topics.
1.1.2 If You Need Assistance
If you have any feedback or questions, support for the Sitara™ MCUs and the AM263x Control Card
development kit is provided by the TI Product Information Center (PIC) and the TI E2E™ Forum. Contact
information for the PIC can be found on the TI website. Additional device-specific information can be found in the
Section 6.1.
1.1.3 Important Usage Notes
Note
The TMDSCNCD263-PMIC has software examples and drivers in a one-time SDK release. For more
information on the installation of the SDK, refer to Section 3.1.
Note
The TMDSCNCD263-PMIC E1 design has various hardware modifications to make sure of proper
operation of the EVM. For additional details of all modifications, refer to Section 5.2.
Note
The AM263x Control Card requires a 5 V, 3 A power supply to function. While a USB type-C cable is
included, a 5 V, 3 A power supply is not included in the kit and must be ordered separately. For more
information, refer to Section 2.3.
Note
TMDSCNCD263-PMIC includes a PMIC and Boost regulator, U30 and U182 which can exceed 55℃
case temperature during normal operation. This user guide's statement and the PCB warning sticker
from the table below have been added to alert users to these higher temperature components.
Caution
Caution hot surface.
Contact can cause burns.
Do not touch!
Note
External Power Supply or Power Accessory Requirements:
• Nominal output voltage: 5-VDC
• Max output current: 3000 mA
• Efficiency Level V
Note
TI recommends using an external power supply or accessory which complies with applicable regional
safety standards such as (by example) UL, CSA, VDE, CCC, PSE, etc.
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1.1 Introduction
The original AM263x Control Card (TMDSCNCD263) was developed to enable easy and rapid prototyping of
the AM263x and all of the peripherals. The changes between the original Control Card and this specific version,
TMDSCNCD263-PMIC, is showcased in Table 1-1.
Table 1-1. Control Card Differences
Subsystem TMDSCNCD263 TMDSCNCD263-PMIC TMDSCNCD263-PMIC Part Number
Power Discrete power Power Management Integrated Chip
(PMIC)
O3850QDCARQ1
Voltage
Supervisor
N/A 1x Automotive, multichannel window
supervisor with very-high accuracy for
1.2 V and 3.3 V supply rails
TPS37042A3OFDDFRQ1
Ethernet 3x Industrial Ethernet PHYs with RJ45
connectors
1x Industrial Ethernet PHY with RJ45
Connector
DP83826ERHBT
2x Automotive Ethernet PHY with
MATEnet connectors
DP83TG720SWRHARQ1
This EVM supports integrated power and safety monitoring that is consistent with ISO26262 ASIL-D by using a
PMIC designed for safety-relevant applications as well as an independent, automotive-grade voltage supervisor.
The Control Card described in this user guide has an E1 and E2 revision. The E1 revision of the Control Card
requires Hardware modifications for proper use. The E1 design Hardware Modifications are described in Section
5.2. The E2 Design files serve as a reference for the proper implementation of the PMIC with the AM263x.
Design files for both E1 and E2 versions of the TMDSCNCD263-PMIC can be found in Section 4.
1.2 Kit Contents
The Sitara AM263x Control Card development kit contains the following items:
• AM263x Sitara series control card development board
• Type-A to Micro-B USB cable (1 meter length)
• USB Type-C Cable (1 meter length)
Note
The maximum length of the IO cables shall not exceed 3 meters.
Not included:
• HSEC 180-pin Baseboard Docking Station
• Standoffs
• USB Type-C 5-V/3-A AC/DC supply and cable
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1.3 Specification
Figure 1-1. System Architecture
1.4 Device Information
The AM263x Sitara™ Arm® Microcontrollers are built to meet the complex real-time processing needs of
next generation industrial and automotive embedded products. The AM263x MCU family consists of multiple
pin-to-pin compatible devices with up to four 400 MHz Arm® Cortex®-R5F cores. As an option, the Arm® R5F
subsystem can be programmed to run in lockstep or dual-core mode for multiple functional safety configurations.
The industrial communications subsystem (PRU-ICSS) enables integrated industrial Ethernet communication
protocols such as PROFINET®, TSN, Ethernet/IP®, EtherCAT® (among many others), standard Ethernet
connectivity, and even custom I/O interfaces. The family is designed for the future of motor control and digital
power applications with advanced analog sensing and digital actuation modules.
The multiple R5F cores are arranged in cluster subsystems with 256KB of shared tightly coupled memory (TCM)
along with 2MB of shared SRAM, greatly reducing the need for external memory. Extensive ECC is included
for on-chip memories, peripherals, and interconnects for enhanced reliability. Granular firewalls managed by the
Hardware Security Manager (HSM) enable developers to implement stringent security-minded system design
requirements. Cryptographic acceleration and secure boot are also available on AM263x devices.
For additional information about the AM263x, refer to either the data sheet: AM263x Sitara™ Microcontrollers
Data Sheet or the Technical Reference Manual: AM263x Sitara™ Microcontrollers Technical Reference Manual.
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1.5 HSEC 180-pin Control Card Docking Station
The TMDSHSECDOCK 180-pin docking station is available for purchase through Texas Instruments. The
docking station is a baseboard that enables rapid prototyping. There is a power switch on the docking station
that determines whether power to the Control Card is supplied by the 5 V connector or the USB connector.
Note
The docking station power switch must be toggled to the EXT-ON side to meet the power
requirements of the AM263x Control Card. EXT-ON indicates that the power is being sourced from
the Barrell connector of the Control Card Dock. The mini-USB (USB-ON) connector does not meet the
power requirements of the AM263x Control Card.
The AM263x Control Card has a power mux (TPS2121RUXT) that supplies power from the type-C connection,
as long as the voltage supplied by the type-C connection is equal to or greater than the voltage supplied by the
HSEC docking station. Therefore, if both a type-C connection is present and the Control Card is connected to a
powered HSEC docking station, then the power mux routes the type-C supplied voltage to VMAIN of the Control
Card. If there is no type-C connection and voltage is being supplied through the HSEC docking station, then the
power mux routes that voltage to VMAIN of the Control Card.
For more information on the docking station, refer to the 180-Pin Docking Station Informational Guide.
1.6 Security
The AM263x Control Card features a High Security, Field Securable (HS-FS) device. An HS-FS device has the
ability to use a one time programming to convert the device from HS-FS to High Security, Security Enforced
(HS-SE).
The AM263x device leaves the TI factory in an HS-FS state where customer keys are not programmed and has
the following attributes:
• Does not enforce the secure boot process
• M4 JTAG port is closed
• R5 JTAG port is open
• Security Subsystem firewalls are closed
• SoC Firewalls are open
• ROM Boot expects a TI signed binary (encryption is optional)
• TIFS-MCU binary is signed by the TI private key
The One Time Programmable (OTP) keyrwriter converts the secure device from HS-FS to HS-SE. The OTP
keywriter programs customer keys into the device eFustes to enforce secure boot and establish a root of trust.
The secure boot requires an image to be encrypted (optional) and signed using customer keys, which is verified
by the SoC. A secure device in the HS-SE state has the following attributes:
• M4, R5 JTAG ports are both closed
• Security Subsystems and SoC Firewalls are both closed
• TIFS-MCU and SBL need to be signed with active customer key
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2 Hardware
2.1 Functional Block Diagram
Power MUX
TSP2121RUXT
VDD, VDDF,
VDDAR[3:1],
VDD_TEMP (1.2V)
VDDS33 (3.3V)
VDDA33 (3.3V)
VDDS18_LDO (1.8V)
VDDA18_LDO (1.8V)
AM263x MCU
VDDS18 (1.8V)
VDDA18,
VDDA18_OSC_PLL
(1.8V)
1.8V Digital
1.8V Analog
TPS653850A-Q1/
O3850AQDCARQ1
PMIC Ferrite (3A)
Ethernet PHY 1.0V/2.0A
TPS62097RWKT LDO
1.2V Core Digital
3.3V Digital
3.3V Analog
ADC_VREFHI_G0,
ADC_VREFHI_G0,
ADC_VREFHI_G0
(1.8V)
DAC_VREF0,
DAC_VREF1 (1.8V)
RP Resistor Pull-Up/Down
RP
AND Gate
1.2V
3.3V
PORZ
WARMRSTN
SOP[0]/QSPI0_D0,
SOP[1]/QSPI0_D1,
SOP[2]/SPI0_CLK,
SOP[3]/SPI0_D0
SOP[3:0]
XTAL_XI/XTAL_XO
25 MHz
Oscillator
VSYS_MON
System 5V RD 0.9V REF
RD Resistor Divider
ADC0_AIN[1:0]
ADC0_AIN[3:2]
ADC0_AIN[5:4]
HSEC 180-Pin
Card-Edge
ADC1_AIN[1:0]
ADC1_AIN[3:2]
ADC1_AIN[5:4]
ADC2_AIN[1:0]
ADC2_AIN[3:2]
ADC2_AIN[5:4]
ADC3_AIN[1:0]
ADC3_AIN[3:2]
ADC3_AIN[5:4]
ADC4_AIN[1:0]
ADC_CAL[1:0]
DAC_OUT
EPWM[0:7, 21]_A/B
SPI0_D0, SPI0_D1,
SPI0_CLK, SPI0_CS0
SPI1_D0, SPI1_D1,
SPI1_CLK, SPI1_CS0
I2C1_SDA, I2C1_SCL
SDFM0_CLK[3:0],
SDFM0_D[3:0]
EQEP[0,2]_A/B,
EQEP[0,2]_INDEX,
EQEP[0,2]_STROBE
EXT_REFCLK0
I2C1 SDA, SCL
I2C3 SDA, SCL
UART2/LIN2 TX/RX
MCAN1
PR0_ICSSM MDIO
MMC0_CLK,
MMC0_CMD,
MMC0_D[3:0],
MMC0_WP,
MMC0_CD
uSD
Connector
SPI0 D0, D1, CS, CLK
SPI1 D0, D1, CS, CLK
Digital IC
Control/
Memory
UART1/LIN1 TX/RX
TCK, TDI, TDO, TMS
UART0
JTAG
UART
CAN Network
RGMII/MII 1Gbit
Ethernet PHY #1
DP83826ERHBT
RJ-45PRU-ICSS (PRU1) RGMII/MII
CPSW RGMII1/RMII1/MII1
PRU-ICSS (PRU0) RGMII/MII
CPSW RGMII2/RMII2/MII2
Isolation
JTAG
UART
CPSW MDIO
MUX
FSI2
Key
Connector/Source/Load
Major IC
QSPI0_CLK,
QSPI0_CSn0,
QSPI0_D0,
QSPI0_D1,
QSPI0_D2,
QSPI0_D3,
QSPI Flash, 512Mbyte
S25HL512TFAMHI010
WARMRSTN
STATUS OUTPUT
Ethernet
PHYs
1.0V
PR0_IEP0_EDIO_DATA_IN_OUT31
PR0_IEP0_EDC_SYNC_OUT0
100-mil
Headers
AM263x MCU
ADC VREF
Paths
JTAG and
UART Debug/
SBL Loading
MCAN PHY
TCAN1042HGVDQ1
USB Type-C
5.0V/3A
HSEC 5.0V
3.3V System
EPWM[0:7, 21]
DAC VREF
Paths
Boost Regulator
12V/1A
LM3488MM
5V VMAIN
VMAIN 12V
PMIC_NRES
Voltage
Monitor
TSP3704
Power Good
AND Gate
Push
Button VMAIN RD
Ethernet PHY #2
100 mil 10
pin Header
Ethernet PHY #1
Ethernet PHY #3
4 Channel
Clock Buffer /3
Ethernet PHYs
RGMII/MII 1Gbit
Automotive
Ethernet PHY #2
DP83TG720
MATEnet
Connector
RGMII/MII 1Gbit
Automotive
Ethernet PHY #3
DP83TG720
MATEnet
Connector
SPI0
SPI1
I2C1
SDFM0
UART1_TX, UART1_RX
MCAN0_TX,
MCAN0_RX
GPMC0_AD[0-15],
GPMC0_CLKB
UART1
MCAN0
GPMC0
TCK, TDI, TDO, TMS
EQEP[0,2]
JTAG
MUX
HSEC MII0
MUX
HSEC MII1
HSEC MII0
HSEC MII1
Figure 2-1. AM263x Control Card Block Diagram
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2.2 Component Identification
Figure 2-2. Component Identification Front
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Figure 2-3. Component Identification Back
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2.3 Power Requirements
The AM263x Control Card is powered from a 5 V, 3 A USB type-C input or from a 5 V, 3 A HSEC connection
supplied by the docking station. The following sections describe the power distribution network topology that
supplies the AM263x Control Card, supporting components, and the reference voltages.
Power supply solutions that are compatible with the AM263x Control Card:
• When using the USB type-C input:
– 5 V, 3 A power adapter with USB-C receptacle
– 5 V, 3 A power adapter with captive USB-C cable
– PC USB type-C port that has Power Delivery classification
• Thunderbolt
• Battery behind USB logo
Figure 2-4. USB Type-C Power Delivery Classification
• When using the HSEC DC barrel jack power input:
– A power adapter that is at least 15 W
Power supply solutions that are NOT compatible with the AM263x Control Card:
• When using USB type-C input:
– Any USB adapter cables such as:
• Type-A to type-C
• micro-B to type-C
• DC barrel jack to type-C
– 5 V, 1.5 A power adapter with USB-C captive cable or receptacle
– PC USB type-C port not capable of 3 A
2.3.1 Power Input Using USB Type-C Connector
The AM263x Control Card can be powered through a USB type-C connection. The USB Type-C source is
capable of providing 3 A at 5 V and advertises the current sourcing capability through the CC1 and CC2
signals. On this EVM, the CC1 and CC2 from the USB type-C connector are interfaced to the port controller
IC (TUSB320LAIRWBR). This device uses the CC pins to determine port attach/detach, cable orientation, role
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detection, and port control for Type-C current mode. The CC logic detects the Type-C current mode as default,
medium, or high depending on the role detected.
The Port pin is pulled down to ground with a resistor to configure the IC in upward facing port (UFP) mode.
VBUS detection is implemented to determine a successful attach in upward facing port (UFP) mode. The OUT1
and OUT2 pins are connected to a NOR gate. Active low on both the OUT1 and OUT2 pins advertises high
current (3A) in the attached state which enables the load switch (TPS22965DSGT) to provide the VBUS_MAIN
supply which powers other regulators that create the power rails for the device.
In UFP mode, the port controller IC constantly presents pull-down resistors on both CC pins. The port controller
IC also monitors the CC pins for the voltage level corresponding to the Type-C mode current advertisement
by the connected downward facing port (DFP). The port controller IC de-bounces the CC pins and waits for
VBUS detection before successfully attaching. As a UFP, the port controller device detects and communicates
the advertised current level of the DFP to the system through the OUT1 and OUT2 GPIOs.
The power requirement for AM263x Control Card is 5 V at 3 A. If the source is not capable of providing
the required power, then the output at the NOR gate becomes low, disabling the VBUS_MAIN power switch.
Therefore, if the power requirement is not met, then all power supplies except VSYS_TA_3V3 remain in an off
state. The board gets powered on completely only when the source can provide 5 V at 3 A.
Figure 2-5. Type-C CC Configuration
Table 2-1. Current Sourcing Capability and State of USB Type-C Cable
OUT1 OUT2 Advertisement
H H Default current in unattached state
H L Default current in attached state
L H Medium current (1.5A) in attached state
L L High current (3.0A) in attached state
The AM263x Control Card includes a power source based on a Power Management Integrated Chip (PMIC) for
each of the power rails. During the initial stage of the power supply, 5 V supplied by the type-C USB connector is
used to generate all of the necessary voltages required by the PMIC and subsequently the rest of the board via
the PMIC LDO outputs. For more information about the PMIC, refer to Section 2.3.5.
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2.3.2 Power Status LEDs
Multiple power-indication LEDs are provided on-board to indicate to users the output status of major supplies.
The LEDs indicate power across various domains as shown in the table below.
Table 2-2. Power Status LEDs
Name Default Status Operation Function
LD16 OFF SAFETY_ERROR Power error indication for voltage - VUSB_5V0
LD17 ON VMAIN_12V0 Power indicator for voltage - VMAIN_12V0
LD15 ON VSYS_3V3A Power indicator for voltage - VSYS_3V3A
LD14 ON VSYS_1V2_PG Power indicator for voltage -VSYS_1V2_PG
LD1 ON VSYS_TA_3V3 Power indicator for voltage -VSYS_TA_3V3
LD6 OFF XDS110_PROG_STAZ2 LED glows after XDS configuration
LD7 OFF XDS110_PROG_STAZ1
Figure 2-6. Power Status LEDs
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2.3.3 Power Tree
Figure 2-7. Power Tree
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2.3.4 Power Sequence
Figure 2-8. Power Sequence Diagram
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2.3.5 PMIC
The TMDSCNCD263-PMIC makes use of a Multirail Power Supply for Microcontrollers in Safety-Relevant
Applications (TPS3850QDCARQ1). The PMIC integrates multiple supply rails to power the MCU, CAN, and
other on-board peripherals.
Figure 2-9. PMIC
Note
VSOUT1 and VSOUT2 are not powered on by default and requires a SPI write to enable the relevant
supply rails.
The PMIC supports wake-up from an ignition signal (IGN) or wake-up from a CAN transceiver (CAN_WU).
An independent voltage monitoring unit inside the PMIC monitors undervoltage and overvoltage on all internal
supply rails and regulator outputs of the battery supply. All supplies are protected with current limiting and
overtemperature pre-warning and shutdown.
For more information about the PMIC and features, refer to the PMIC Data Sheet.
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2.4 Reset
Figure 2-10 shows the reset architecture of the AM263x Control Card.
Figure 2-10. Reset Architecture
The AM263x SoC has the following resets:
• PORz is the Power-On-Reset for the MAIN Domain.
• WARMRESETn is the Warm Reset to MAIN Domain.
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Figure 2-11. PORz Reset Signal Tree
The PORz signal is driven by a 3-input AND gate that generates a power on reset for the MAIN domain when:
• The PMIC drives the NRES, MCU Reset output signal low.
• The Voltage Monitor (TPS37042A3OFDDFRQ1) drives either RESET1 or RESET2 when VSYS_3V3A or
VSYS_1V2 respectively are outside of the defined boundaries. For VSYS_3V3A, RESET1 is asserted when
SENSE1 is either 8% above or below 3.3 V (including device accuracy). For VSYS_1V2, RESET2 is asserted
when SENSE2 is either 5% above or below 1.2 V (including device accuracy.
• The user push button (SW2) is pressed.
• The Test Automation Header outputs a logic LOW signal (TA_PORZn) to a P-Channel MOSFET gate which
causes V_GS of the PMOS to be less than zero and so the PORz signal connects to the PMOS drain which
is tied directly to ground.
The PORz signal is tied to:
• AM263x SoC PORz input
• RGMII1 Ethernet PHY reset
• ICSSM1 Gigabit Ethernet PHY reset
• ICSSM2 Industrial Ethernet PHY reset
• BOOTMODE buffer output enable
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Figure 2-12. WARMRESETn Reset Signal Tree
The WARMRESETn signal creates a warm reset to the MAIN domain when:
• The user push button (SW4) is pressed.
• The Test Automation Header outputs a logic LOW signal (TA_RESETz) to a P-Channel MOSFET gate which
causes V_GS of the PMOS to be less than zero and so the RESETz signal connects to the PMOS drain
which is tied directly to ground.
The WARMRESETn signal is tied to:
• AM263x SoC WARMRESETN output
• RESETz signal created from push button + PMOS logic
• IO Expander reset
• Micro SD reset
The AM263x Control Card also has an external interrupt to the SoC, INTn, that occurs when:
• The user push button (SW1) is pressed.
• The Test Automation Header outputs a logic LOW signal (TA_GPIO1) to a P-Channel MOSFET gate which
causes V_GS of the PMOS to be less than zero, connecting the INTn signal to he PMOS drain tied directly to
ground.
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2.5 Clock
The AM263x SoC requires a 25-MHz clock input for XTAL_XI. All reference clocks required for the SoC and the
three Ethernet PHYs are generated from a single four output clock buffer (LMK1C1104PWR), which is sourced
from a single 25-MHz LVCMOS Oscillator by default. A clock buffer is used for level translation from 3.3 V to 1.8
V.
The Control Card also requires a 16-MHz clock source for the TM4C129 microcontroller for UART-USB JTAG
support.
Alternatively, the SoC clock input can be sourced from a single 25-MHz crystal. To use the crystal there must be
resistors mounted and unmounted as shown in Table 2-3. When the using a crystal as the SoC clock source,
then the AM263x CLKOUT0 signal is used to source the four output clock buffer for the Ethernet PHY reference
clock signals.
Figure 2-13. Crystal Clock Tree
The following table describes the proper resistors to be mounted and DNI'd for each clock source configuration.
Table 2-3. Clock Source
Clock Source Mounted DNI
25-MHz LVCMOS Oscillator (default) R161, R135 R158, R155, R134
25-MHz Crystal R158, R155, R134 R161, R135
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2.6 Boot Mode Selection
The bootmode for the AM263x is selected by either the DIP switch (SW3) or the test automation header. The
test automation header uses an I2C IO expansion buffer to drive the bootmode when PORz is toggled. The
supported boot modes are as shown in Supported Boot Modes.
Table 2-4. Supported Boot Modes
Boot Mode/Peripheral Boot Media/Host Notes
QSPI (4S) - Quad Read Mode QSPI Flash Download and boot SBL from QSPI flash in quad read mode. Attempt
Primary SBL, followed by Secondary SBL if primary loading fails.
UART External Host Download and boot SBL from UART. Device is expected to get SBL
from UART. Device supports the XMODEM protocol for download over
UART.
QSPI (1S) - Single Read Mode QSPI Flash Download and boot SBL from QSPI flash in single read mode. Attempt
Primary SBL, followed by Secondary SBL if primary loading fails.
QSPI (4S) - Quad Read UART
Fallback Mode
QSPI Flash / External Host Download and boot SBL from QSPI flash in quad read mode. Attempt
Primary SBL, followed by Secondary SBL if primary loading fails. If
Secondary SBL also fails then boot from external host via UART
interface.
QSPI (1S) - Single Read UART
Fallback Mode
QSPI Flash / External Host Download and boot SBL from QSPI flash in single read mode. Attempt
Primary SBL, followed by Secondary SBL if primary loading fails. If
Secondary SBL also fails then boot from external host via UART
interface.
DevBoot N/A No SBL. Used for development purposes only.
Figure 2-14. SW3 Switch Positions
Table 2-5. Boot-Mode Selection Table
Boot Mode
SPI0_D0_pad
(SOP3)
SPI0_CLK_pad
(SOP2) QSPI_D1 (SOP1) QSPI_D0 (SOP0)
QSPI (4S) - Quad Read Mode 0 0 0 0
UART 0 0 0 1
QSPI (1S) - Single Read Mode 0 0 1 0
QSPI (4S) - Quad Read UART Fallback
Mode
0 1 0 0
QSPI (1S) - Single Read UART Fallback
Mode
0 1 0 1
DevBoot 1 0 1 1
Unsupported Boot Mode All other combinations not defined above
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2.7 JTAG Path Selection
The AM263x Control Card allows for JTAG connections to the SoC through the on-board XDS110 or an external
emulator via the HSEC docking station. A switch (SW5) is used to drive the select line of a mux (U19) to
determine the JTAG path for the SoC. Section 2.12.9 provides additional detail on JTAG pathing.
2.8 Header Information
This version of the AM263x Control Card has 11 different headers. For the locations of each header, refer to
Section 2.2. The signal details for each header pin is detailed below.
• Test Automation Bootmode Control Header
– For more information about the Test Automation Header, refer to Section 2.12.10
Table 2-6. Test Automation Header
Designator Pin 1 Pin 2
J3 TA_GPIO3 DGND
• MCAN Header
– For more information about the MCAN interface, refer to Section 2.12.7
Table 2-7. MCAN Header
Designator Pin 1 Pin 2 Pin 3
J5 MCAN1_CAN_H DGND MCAN1_CAN_L
• FSI Header
– For more information about the FSI Interface, refer to Section 2.12.8
Table 2-8. FSI Header
Designator Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 Pin 9 Pin 10
J6 FSIRX2_CLK FSITX2_CLK DGND DGND FSIRX2_DATA0 FSITX2_DATA0 FSIRX2_DATA1 FSITX2_DATA1 DGND VSYS_3V3A
• PRU-ICSS IEP Headers
– For more information about the PRU-ICSS, refer to Section 2.12.2.2
Table 2-9. PRU-ICSS IEP Headers
Designator Pin 1 Pin 2
J8 PR0_IEP0_EDIO_DATA_IN_OUT_31 DGND
J9 PR0_IEP0_EDC_SYNC_OUT1 DGND
J10 PR0_IEP0_EDIO_DATA_IN_OUT_30 DGND
J11 PR0_IEP0_EDC_SYNC_OUT0 DGND
• LIN Headers
– For more information about the LIN interface, refer to Section 2.12.11
Table 2-10. LIN Headers
Designator Pin 1 Pin 2 Pin 3
J32 VLIN LIN DGND
J33 VBAT_LIN DGND N/A
• PMIC Headers
– For more information about the PMIC, refer to Section 2.3.5
Table 2-11. PMIC Headers
Designator Pin 1 Pin 2
J35 IGNITION DGND
J36 CANWU DGND
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