Texas Instruments ADS8900BEVM-PDK User manual

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ADS8900BEVM-PDK
multiSPI is a trademark of Texas Instruments.
multiSPI is a registered trademark of Texas Instruments.
Microsoft, Windows are registered trademarks of Microsoft Corporation.
LabVIEW is a trademark of National Instruments.
All other trademarks are the property of their respective owners.
User's Guide
SBAU269–October 2016
ADS8900BEVM-PDK
This user's guide describes the characteristics, operation, and use of the ADS8900B evaluation module
(EVM) performance demonstration kit (PDK). This kit is an evaluation platform for the ADS8900B, which is
a 20-bit, 1-MSPS, fully-differential input, successive approximation register (SAR) analog-to-digital
converter (ADC) that features an enhanced serial multiSPI™ digital interface. The EVM-PDK eases the
evaluation of the ADS8900B device with hardware, software, and computer connectivity through the
universal serial bus (USB) interface. This user's guide includes complete circuit descriptions, schematic
diagrams, and a bill of materials.
The following related documents are available through the Texas Instruments web site at www.ti.com.
Related Documentation
Device Literature Number
ADS8900B SBAS728
OPA625 SBOS688
OPA376 SBOS406
OPA378 SBOS417
REF5050 SBOS410
TPS7A4700 SBVS204

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Contents
1 Overview...................................................................................................................... 4
1.1 ADS8900BEVM-PDK Features ................................................................................... 4
1.2 ADS8900BEVM Features.......................................................................................... 4
2 Analog Interface.............................................................................................................. 5
2.1 Connectors for Differential Signal Source ....................................................................... 5
2.2 ADC Differential Input Signal Driver.............................................................................. 5
2.3 Onboard ADC Reference.......................................................................................... 8
3 Digital Interfaces ............................................................................................................. 8
3.1 multiSPI®for ADC Digital IO ...................................................................................... 8
4 Power Supplies .............................................................................................................. 9
5 ADS8900BEVM-PDK Initial Setup......................................................................................... 9
5.1 Default Jumper Settings ........................................................................................... 9
5.2 EVM Graphical User Interface (GUI) Software Installation.................................................... 9
6 ADS8900BEVM-PDK Operation ......................................................................................... 13
6.1 EVM GUI Global Settings for ADC Control .................................................................... 15
6.2 Register Map Configuration Tool................................................................................ 17
6.3 Time Domain Display Tool....................................................................................... 18
6.4 Spectral Analysis Tool............................................................................................ 19
6.5 Histogram Tool .................................................................................................... 21
6.6 Linearity Analysis Tool............................................................................................ 22
6.7 Reference Settling Analysis...................................................................................... 23
7 Bill of Materials, PCB Layout, and Schematics......................................................................... 25
7.1 Bill of Materials .................................................................................................... 25
7.2 PCB Layout ........................................................................................................ 28
7.3 Schematics......................................................................................................... 31
List of Figures
1 OPA625 Differential Input Driving Path .................................................................................. 6
2 Common-Mode Selection Jumpers........................................................................................ 7
3 ADS8900B Software Installation Prompts .............................................................................. 10
4 Device Driver Installation Wizard Prompts.............................................................................. 10
5 LabVIEW Run-Time Engine Installation................................................................................. 11
6 ADS8900BEVM Folder Post-Installation ................................................................................ 12
7 EVM-PDK Hardware Setup and LED Indicators ....................................................................... 13
8 Launch the EVM GUI Software........................................................................................... 14
9 EVM GUI Global Input Parameters...................................................................................... 15
10 Register Map Configuration............................................................................................... 17
11 Time Domain Display Tool Options...................................................................................... 18
12 Spectral Analysis Tool..................................................................................................... 20
13 Histogram Analysis Tool .................................................................................................. 21
14 Linearity Analysis Tool..................................................................................................... 23
15 Reference Settling Tool ................................................................................................... 24
16 ADS8900BEVM PCB Layer 1: Top Layer .............................................................................. 28
17 ADS8900BEVM PCB Layer 2: GND Plane............................................................................. 29
18 ADS8900BEVM PCB Layer 3: Power Planes.......................................................................... 30
19 ADS8900BEVM PCB Layer 4: Bottom Layer........................................................................... 31
20 Schematic Diagram (Page 1) of the ADS8900BEVM PCB........................................................... 32
21 Schematic Diagram (Page 2) of the ADS8900BEVM PCB........................................................... 33
22 Schematic Diagram (Page 3) of the ADS8900BEVM PCB........................................................... 34
List of Tables

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1 J7 and J3 SMA Connectors Description.................................................................................. 5
2 J4 and J6 Headers Description............................................................................................ 5
3 J1 and J2 Configuration per Input Common-Mode...................................................................... 7
4 External Source Requirements for Evaluation of the ADS8900B.................................................... 19
5 External Source Requirements for ADS8900B Evaluation ........................................................... 22
6 ADS8900BEVM Bill of Materials ......................................................................................... 25

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1 Overview
The ADS8900BEVM-PDK is a platform for evaluating the performance of the ADS8900B SAR ADC, which
is a fully-differential input, 20-bit, 1-MSPS device. The evaluation kit includes the ADS8900BEVM board
and the precision host interface (PHI) controller board that enables the accompanying computer software
to communicate with the ADC over USB for data capture and analysis.
The ADS8900BEVM board includes the ADS8900B SAR ADC, all the peripheral analog circuits, and
components required to extract optimum performance from the ADC.
The PHI board primarily serves three functions:
• Provides a communication interface from the EVM to the computer through a USB port
• Provides the digital input and output signals necessary to communicate with the ADS8900BEVM
• Supplies power to all active circuitry on the ADS8900B board
Along with the ADS8900BEVM and PHI controller board, this evaluation kit includes an A-to-micro-B USB
cable to connect to a computer.
1.1 ADS8900BEVM-PDK Features
The ADS8900BEVM-PDK includes the following features:
• Hardware and software required for diagnostic testing as well as accurate performance evaluation of
the ADS8900B ADC
• USB powered—no external power supply is required
• The PHI controller that provides a convenient communication interface to the ADS8900B ADC over a
USB 2.0 (or higher) for power delivery as well as digital input and output
• Easy-to-use evaluation software for Microsoft®Windows®7, Windows 8, 64-bit operating systems
• The software suite includes graphical tools for data capture, histogram analysis, spectral analysis,
linearity analysis, and reference settling analysis. This suite also has a provision for exporting data to a
text file for post-processing.
1.2 ADS8900BEVM Features
The ADS8900BEVM includes the following features:
• Onboard low-noise and low distortion ADC input drivers optimized to meet ADC performance
• Onboard precision 5.0-V voltage reference with a low-pass filter
• Jumper-selectable 0-V and 2.5-V input common-mode options allow unipolar and bipolar inputs
• Onboard ultralow noise low-dropout (LDO) regulator for excellent 5.2-V single-supply regulation of all
operation amplifiers and voltage reference

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2 Analog Interface
As an analog interface, the evaluation board uses operational amplifiers in a variety of configurations to
drive the ADS8900B input signal and reference inputs. This section covers driver details including jumper
configuration for different input signal common modes and board connectors for a differential signal
source.
2.1 Connectors for Differential Signal Source
The ADS8900BEVM is designed for easy interfacing to an external analog differential source via a
subminiature version A (SMA) connector or 100-mil headers. J7 and J3 are SMA connectors that allow
analog source connectivity through coaxial cables. Also, 100-mil jumper cables or mini-grabbers can be
used to connect analog sources to the J4:2 and J6:2 pins.
NOTE: The input does not support single-ended signals. The external source must be differential or
balanced keeping the negative and positive inputs to the board symmetric such that Vs(+) =
–Vs(–) at any given time.
Table 1. J7 and J3 SMA Connectors Description
Pin Number Signal Description
J3 Vs(–) Negative differential board input,
1-kΩinput impedance
J7 Vs(+) Positive differential board input,
1-kΩinput impedance
Table 2. J4 and J6 Headers Description
Pin Number Signal Description
J4:3 TEST 0.23 V Do not use: diagnostic use only
J4:2 Vs(–) Negative differential board input,
1-kΩinput impedance
J4:1 AGND Analog ground
J6:3 AGND Analog ground
J6:2 Vs(+) Positive differential board input,
1-kΩinput impedance
J6:1 TEST 4.77 V Do not use: diagnostic use only
2.2 ADC Differential Input Signal Driver
The differential signal inputs of the ADS8900B are not dynamically high impedance. SAR ADC inputs
terminate in switched-capacitor networks that create large instantaneous current loads when the switches
are closed that effectively make the ADC inputs dynamically low impedance. Thus, the evaluation board
has low impedance on board drivers that maintain ADC performance with maximum loading at the full
device throughput of 1-MSPS for signal.

ADC
AINP
AINN
OPA625
+
±
OPA625
±
+
.
.
.
.
.
.
External
Differential
Source
Note: External source
must be balanced
VS(+) = -VS(-)
3
2
1
3
2
1
RS
RS
VS (-)
VS (+)
J4
J6
J7
1-kŸ
1-kŸ
1-nF
10-nF
1-kŸ2.2-Ÿ
2.2-Ÿ
10-nF
10-nF
OPA625_CM
1-kŸ
1-nF
J3
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2.2.1 Input Signal Path
Figure 1 shows the signal path for the differential signal applied at the board inputs. The board input
impedance is 1-kΩwith 10-nF differential filtering that keeps noise in external cabling common. The
overall signal path bandwidth is limited to 160-kHz by the anti-aliasing filter formed from a 1-kΩresistor
and 1-nF capacitor at the amplifier feedback. Finally, the two OPA625 operational amplifiers drive the
ADS8900B differential inputs with 2.2-Ωimpedance up to 7-MHz that properly drives the low dynamic
impedance of the ADC inputs at 1-MSPS.
Figure 1. OPA625 Differential Input Driving Path
2.2.2 Input Common-Mode Jumper Configuration
The ADS8900BEVM board accommodates three external source common-mode options: 0 V, 2.5 V, and
floating with jumpers J1 and J2; see Figure 2 and Table 3.
J2 selects the OPA625 common-mode as 2.5 V (J2:OPEN) or 1.25 V (J2:CLOSED). J1 increases the
OPA625 common-mode by almost 100 mV to avoid amplifier output saturation with full-scale external
source signal amplitude. R1 is installed as 280 kΩ, allowing full-scale external source signals for external
source impedance (RS) between 0 Ωand 32 Ω, with 0-V common mode. R1 must be changed to
compensate for larger external source impedance (RS) values or for 2.5-V external source common-mode,
as explained in Section 2.2.3.

2.5 V QADC_VCM Q2.6 V
ADC_ VCM =5 × tr•À
tr•À+ (R1// tr•À) × l1 +
s•À
s•À+ RSpFl2.5 × s•À s•À+ RSp
ADC_ VCM =5 × (sr•À//tr•À)
(sr•À//tr•À) + (R1//tr•À) × l1 +
s•À
s•À+ RSp
20kŸ
280kŸ5.0V
20kŸ
10kŸ
OPA625_CM OPA376
Gain = 1
J2
J1
R1
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Figure 2. Common-Mode Selection Jumpers
Table 3. J1 and J2 Configuration per Input Common-Mode
J1 Setting
(R1 Comp) J2 Setting External Signal Common-Mode Differential Source Type
CLOSED CLOSED 0 V Bipolar: If R1 = 280 kΩ, RSrange is 0 Ωto 32 Ω
CLOSED OPEN 2.5 V Unipolar: must change R1 to match RS
CLOSED OPEN Floating AC-coupled bipolar: If R1 = 280 kΩ, no RSrestriction
2.2.3 R1 Setting vs Source Impedance
The external source impedance (RS) adds up to the 1 kΩof the input resistor, thereby moving the output
common-mode of the OPA625 amplifiers. To compensate for this change in output common-mode, R1
can be modified according to the particular external source impedance value used with the evaluation
board to allow full-scale input range without saturating the OPA625 amplifiers.
The board is shipped with R1 as 280 kΩthat allows an external source impedance (RS) range between
0Ωto 32 Ωfor a 0-V common-mode configuration (J1:closed and J2:closed). For floating or ac-coupled
signals, the input common-mode is set by the OPA625 amplifiers themselves and R1 must remain at
280 kΩfor any given source impedance. The ADC common-mode for 0-V input common-mode setting is
calculated using Equation 1.
(1)
In the case of unipolar input signals with a 2.5-V common-mode, the ADC common-mode is calculated
using Equation 2.
(2)
For Equation 1 and Equation 2 the value of R1 must be calculated to satisfy Equation 3:(3)

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2.3 Onboard ADC Reference
The EVM does not include a provision for driving the reference input of the ADS8900B from an external
source. The reference input signal path is entirely self-contained on the ADS8900BEVM and consists of
the REF5050, a 5.0-V precision voltage reference. The output of the REF5050 is filtered by a 10-kΩand
10-µF low-pass filter. The low-pass filtered output functions as an input to the internal reference buffer of
the ADS8900B ADC. This internal reference driver offers zero-offset, low-noise, and is optimized for a 1-
LSB voltage regulation under maximum loading conditions at full device throughput of 1 MSPS.
3 Digital Interfaces
As noted in Section 1, the EVM interfaces with the PHI that, in turn, communicates with the computer over
USB. There are two devices on the EVM with which the PHI communicates: the ADS8900B ADC (over
SPI or multiSPI) and the EEPROM (over I2C). The EEPROM comes pre-programmed with the information
required to configure and initialize the ADS8900BEVM-PDK platform. Once the hardware is initialized, the
EEPROM is no longer used.
3.1 multiSPI®for ADC Digital IO
The ADS8900BEVM-PDK supports all the interface modes as detailed in the ADS8900B datasheet (TBD).
In addition to the standard SPI modes, (with single-, dual-, and quad-SDO lanes), the multiSPI modes
support single- and dual-data output rates and the four possible clock source settings as well. The PHI is
capable of operating at a 3.3-V logic level and is directly connected to the digital I/O lines of the ADC.

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4 Power Supplies
The PHI provides multiple power-supply options for the EVM, derived from the USB supply of the
computer.
The EEPROM on the ADS8900BEVM use a 3.3-V power supply generated directly by the PHI. The ADC
and analog input drive circuits are powered by the TPS7A4700 onboard the EVM, which is a low-noise
linear regulator that uses the 5.5-V supply out of a switching regulator on the PHI to generate a much
cleaner 5.2-V output. The 3.3-V supply to the digital section of the ADC is provided directly by an LDO on
the PHI.
The power supply for each active component on the EVM is bypassed with a ceramic capacitor placed
close to that component. Additionally, the EVM layout uses thick traces or large copper fill areas, where
possible, between bypass capacitors and their loads to minimize inductance along the load current path.
5 ADS8900BEVM-PDK Initial Setup
This section explains the initial hardware and software setup procedure that must be completed for the
proper operation of the ADS8900BEVM-PDK.
5.1 Default Jumper Settings
Jumper settings are determined by common mode and source impedance of the external source that
provides a differential signal to the board. Remove shunts from J4 and J6 and set J2 and J1 according to
the external source as described in Section 2.
5.2 EVM Graphical User Interface (GUI) Software Installation
Download the latest version of the EVM GUI installer from the Tools and Software folder of the ADS8900B
and run the GUI installer to install the EVM GUI software on the user’s computer.
CAUTION
Manually disable any antivirus software running on the computer before
downloading the EVM GUI installer onto the local hard disk. Otherwise,
depending on the antivirus settings, an error message may appear or the
installer.exe file may be deleted.
Accept the license agreements and follow the on-screen instructions to complete the installation.

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Figure 3. ADS8900B Software Installation Prompts
As a part of the ADS8900BEVM GUI installation, a prompt with a Device Driver Installation will appear on
the screen. Click Next to proceed.
Figure 4. Device Driver Installation Wizard Prompts

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NOTE: A notice may appear on the screen stating that Widows cannot verify the publisher of this
driver software. Select Install this driver software anyway.
The ADS8900BEVM-PDK requires LabVIEW™ Run-Time Engine and may prompt for the installation of
this software, if not already installed.
Figure 5. LabVIEW Run-Time Engine Installation

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After these installations, verify that C:\Program Files (x86)\Texas Instruments\ADS8900BEVM is as shown
in Figure 6.
Figure 6. ADS8900BEVM Folder Post-Installation

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6 ADS8900BEVM-PDK Operation
The following instructions are a step-by-step guide to connecting the ADS8900BEVM-PDK to the
computer and evaluating the performance of the ADS8900B:
1. Connect the ADS8900BEVM to the PHI. Install the two screws as indicated in Figure 7.
2. Use the USB cable provided to connect the PHI to the computer.
• LED D5 on the PHI lights up, indicating that the PHI is powered up.
• LEDs D1 and D2 on the PHI start blinking to indicate that the PHI is booted up and communicating
with the PC. The resulting LED indicators are shown in Figure 7.
Figure 7. EVM-PDK Hardware Setup and LED Indicators

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3. Launch the ADS8900BEVM GUI software, as shown in Figure 8.
Figure 8. Launch the EVM GUI Software

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6.1 EVM GUI Global Settings for ADC Control
Although the EVM GUI does not allow direct access to the levels and timing configuration of the ADC
digital interface, the EVM GUI does give users high-level control over virtually all functions of the
ADS8900B including interface modes, sampling rate, and number of samples to be captured.
Figure 9 identifies the input parameters of the GUI (as well as their default values) through which the
various functions of the ADS8900B can be exercised. These settings are global because they persist
across the GUI tools listed in the top left pane (or from one page to another).
Figure 9. EVM GUI Global Input Parameters
The host configuration options in this pane allow the user to choose from various SPI and multiSPI host
interface options available on the ADS8900B. The host always communicates with the ADS8900B using
the standard SPI protocol over the single SDI lane, irrespective of the mode selected for data capture.
The drop-down boxes under the Interface Configuration sub-menu allow the user to select the data
capture protocol. The SDO Width drop-down allows selection between Single-, Dual- and Quad-SDO
lanes. The SDO Mode drop-down allows selection between Standard SPI and multiSPI modes.
In SPI mode, the SDI Mode drop-down allows selection between the four SPI protocol combinations for
CPOL and CPHA.
In multiSPI mode, the Clock Source drop-down allows selection between Source and System
Synchronous modes; the Data Rate drop-down allows selection between SDR and DDR modes. Detailed
descriptions of each of these modes is available in the ADS8900B datasheet (TBD). The selected data
capture protocol is summarized in the Protocol Selected indicator box.

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The user can select SCLK Frequency and Sampling Rate on this pane and is dependent of the Protocol
selected. The GUI allows the user to enter the targeted values for these two parameters and the GUI
computes the best values that can be achieved, considering the timing constraints of the selected Device
Protocol.
The user can specify a target SCLK frequency (in Hz) and the GUI tries to match this frequency as closely
as possible by changing the PHI PLL settings and the achievable frequency that can differ from the target
value displayed. Similarly, the sampling rate of the ADC can be adjusted by modifying the Target
Sampling Rate argument (also in Hz). The achievable ADC sampling rate can differ from the target value,
depending on the applied SCLK frequency and selected Device Mode and the closest match achievable is
displayed. This pane, therefore, allows the user to try various settings available on the ADS8900B in an
iterative fashion until the user converges to the best settings for the corresponding test scenario.
The final option in this pane is the selection for the Update Mode. The default value is Immediate,
indicating that the interface settings selection made by the user is applied to configure both the host and
the ADS8900B instantly. Manual indicates that the selection made is made only when the user finalizes
their choices and is ready to configure the device.
The Device Reset button functions as a Master RESET to both the ADS8900BEVM and the GUI. When
the button is pressed, the ADC RESETs to the RESET configuration explained in the datasheet (TBD).
The GUI also updates the Interface Configuration settings and the Register Map to reflect the device
RESET state.

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6.2 Register Map Configuration Tool
The register map configuration tool allows the user to view and modify the registers of the ADS8900B.
This tool can be selected by clicking on the Register Map Config radio button at the Pages section of the
left pane, as indicated in Figure 10. On power-up, the values on this page correspond to the Host
Configuration Settings that enable ADC sampling at the maximum sampling rate specified for the ADC.
The register values can be edited by double-clicking the corresponding value field. If interface mode
settings are affected by the change in register values, this change reflects on the left pane immediately.
The effect of changes in the register value reflect on the ADS8900B device on ADS8900BEVM-PDK
based on the Update Mode selection, as described in Section 6.1.
Figure 10. Register Map Configuration
Section 6.3 through Section 6.7 describe the data collection and analysis features of the ADS8900BEVM-
PDK GUI.

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6.3 Time Domain Display Tool
The time domain display tool allows visualization of the ADC response to a given input signal. This tool is
useful for both studying the behavior and debugging any gross problems with the ADC or drive circuits.
The user can trigger a capture of the data of the selected number of samples from the ADS8900B, as per
the current interface mode settings using the capture button as indicated in Figure 11. The sample indices
are on the x-axis and there are two y-axes showing the corresponding output codes as well as the
equivalent analog voltages based on the specified reference voltage. Switching pages to any of the
Analysis tools described in the subsequent sections, triggers calculations to be performed on the same set
of data.
Figure 11. Time Domain Display Tool Options

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6.4 Spectral Analysis Tool
The spectral analysis tool is intended to evaluate the dynamic performance (SNR, THD, SFDR, SINAD,
and ENOB) of the ADS8900B SAR ADC through single-tone sinusoidal signal FFT analysis using the 7-
term Blackman-Harris window setting. Also, the window setting of None can be used to search for noise
spurs over frequency in dc inputs.
For dynamic performance evaluation, the external differential source must have better specifications than
the ADC itself to ensure that the measured system performance is not limited by the performance of the
signal source. Therefore, the external reference source must meet the source requirements mentioned in
Table 4.
Table 4. External Source Requirements for Evaluation of the ADS8900B
Specification Description Specification Value
Signal frequency 2 kHz
External source type Balanced differential
External source common-mode 0 V or floating
(see Section 2.2.2 for jumper settings)
External source impedance (RS) 10 Ω–30 Ω
External source differential impedance
(RS_DIFF = 2 × RS)20 Ω–60 Ω
Source differential signal
(VPP Amplitude for –0.1 dBFS) (2 × RS× 4.45 × 10–3) + 8.9 V
or
(RS_DIFF × 4.45 × 10–3) + 8.9 V
Maximum noise 10 µVRMS
Maximum SNR 110 dB
Maximum THD –130 dB
For 2-kHz SNR and ENOB evaluation at a maximum throughput of 1 MSPS, the number of samples must
be 32768 or 65536. More samples brings the noise floor so low that the external source phase noise can
dominate the SNR and ENOB calculations. On the contrary, for THD and SFDR evaluation, a much larger
number of samples must be used to reduce the noise floor below –140 dBc to analyze noise-free
harmonics and spurs in the order of –120 dBc. Such analysis requires at least 262144 samples.

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Figure 12. Spectral Analysis Tool
Finally, the FFT tool includes windowing options that are required to mitigate the effects of non-coherent
sampling (this discussion is beyond the scope of this document). The 7-Term Blackman Harris window is
the default option and has sufficient dynamic range to resolve the frequency components of up to a 24-bit
ADC. Note that the None option corresponds to not using a window (or using a rectangular window) and is
not recommended.