Texas Instruments AM263 Series Guide

Application Note
AM263x Hardware Design Guide
ABSTRACT
This document intends to serve as a guide for hardware designers creating PCB systems based on the
AM263x family of MCU devices. This document serves to integrate device-specific schematic and PCB layout
recommendations and examples from the various AM263x evaluation modules (EVM) such as the LP-AM263
Launchpad™ and TMDSCNCD263 controlCard, with the AM263x Sitara™ Microcontroller Data Sheet, AM263x
Sitara™ Microcontroller Technical Reference Manual and other collateral documents and tools, as shown in
Section 12.
Table of Contents
1 Introduction.............................................................................................................................................................................2
1.1 Acronyms........................................................................................................................................................................... 3
2 Power....................................................................................................................................................................................... 3
2.1 Discrete DC-DC Power Solution........................................................................................................................................ 3
2.2 Integrated PMIC Power Solution........................................................................................................................................5
2.3 Power Decoupling and Filtering ........................................................................................................................................ 5
2.4 Power Consumption...........................................................................................................................................................9
2.5 Power Distribution Network................................................................................................................................................9
2.6 e-Fuse Power...................................................................................................................................................................15
3 Clocking.................................................................................................................................................................................16
3.1 Crystal and Oscillator Input Options.................................................................................................................................16
3.2 Output Clock Generation..................................................................................................................................................17
3.3 Crystal Selection and Shunt Capacitance........................................................................................................................17
3.4 Crystal Placement and Routing........................................................................................................................................18
4 Resets.................................................................................................................................................................................... 18
5 Bootstrapping....................................................................................................................................................................... 20
5.1 SOP Signal Implementation............................................................................................................................................. 20
5.2 QSPI Memory Controller Implementation........................................................................................................................ 21
5.3 ROM QSPI Boot Requirements....................................................................................................................................... 24
6 JTAG Emulators and Trace.................................................................................................................................................. 24
7 Multiplexed Peripherals....................................................................................................................................................... 25
8 Digital Peripherals................................................................................................................................................................ 26
8.1 General Digital Peripheral Routing Guidelines.................................................................................................................26
9 Layer Stackup....................................................................................................................................................................... 26
9.1 Key Stackup Features......................................................................................................................................................27
10 Vias.......................................................................................................................................................................................28
11 BGA Power Fan-Out and Decoupling Placement.............................................................................................................28
11.1 Ground Return................................................................................................................................................................28
11.2 1.2 V Core Digital Power................................................................................................................................................ 29
11.3 3.3 V Digital and Analog Power......................................................................................................................................31
11.4 1.8 V Digital and Analog Power......................................................................................................................................34
12 References.......................................................................................................................................................................... 37
Trademarks
Launchpad™ and Sitara™ are trademarks of Texas Instruments.
Arm® and Cortex® are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
All trademarks are the property of their respective owners.
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AM263x Hardware Design Guide 1
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1 Introduction
The AM263x are single, dual or quad-core Arm® Cortex®-R5F based MCU in the Sitara™ MCU family of devices
intended for the industrial and automotive motion control environments. A typical AM263x-based design is
shown in Figure 1-1. This diagram is excerpted from the AM263x Launchpad (LP-AM263) system block diagram.
As can be seen below, the AM263x devices offer designers a wide range of digital connectivity, control and
analog sensor feedback options.
VDD, VDDF,
VDDAR[3:1],
VDD_TEMP (1.2 V)
VDDS33 (3.3 V)
VDDA33 (3.3 V)
VDDS18_LDO (1.8 V)
VDDA18_LDO (1.8 V)
AM263x MCU+
VDDS18 (1.8 V)
VDDA18,
VDDA18_OSC_PLL
(1.8 V)
System Voltage to 1.2 V
Buck Converter
System Voltage to 1.2 V
Buck Converter Ferrite (3 A)
System Power
Ethernet PHY 1.1 V/1.5 A
TPS74801DRCR LDO
Ethernet PHY 2.5 V/1.5 A
TPS74801DRCR LDO
1.2 V
3.3 V
3.3 V
ADC_VREFHI_G0,
ADC_VREFHI_G0,
ADC_VREFHI_G0
(1.8 V)
DAC_VREF0,
DAC_VREF1 (1.8 V)
RP Resistor Pull-Up/Down
RP
AND Gate
1.2V Power Good
3.3V Power Good
PORZ PORZ
WARMRSTN
SOP[0]/QSPI0_D0,
SOP[1]/QSPI0_D1,
SOP[2]/SPI0_CLK,
SOP[3]/SPI0_D0
SOP[3:0]
XTAL_XI/XTAL_XO
25 MHz
XTAL
VSYS_MONSystem 5V RD 0.9 V REF
RD Resistor Divider
ADC0_AIN[1:0]
ADC0_AIN[3:2]
ADC0_AIN[5:4]
Analog
Sensor
Feedback
ADC1_AIN[1:0]
ADC1_AIN[3:2]
ADC1_AIN[5:4]
ADC2_AIN[1:0]
ADC2_AIN[3:2]
ADC2_AIN[5:4]
ADC3_AIN[1:0]
ADC3_AIN[3:2]
ADC3_AIN[5:4]
ADC4_AIN[1:0]
ADC4_AIN[3:2]
ADC4_AIN[5:4]
ADC_CAL[1:0]
DAC_OUT Analog
Sensor Input
EPWM0_A/B
EPWM1_A/B
EPWM2_A/B
EPWM3_A/B
Power Stage
Control
EPWM13_A/B
EQEP0_A/B,
EQEP0_INDEX,
EQEP0_STROBE
SDFM1_CLK0/D0,
SDFM1_CLK1/D1
Analog
Sensor
Feedback
EXT_REFCLK0
25 MHz
Clock
Ethernet
PHY #1
I2C1 SDA, SCL
I2C3 SDA, SCL
UART2/LIN2 TX/RX
MCAN0
MCAN1
CPSW MDIO
MMC0_CLK,
MMC0_CMD,
MMC0_D[3:0],
MMC0_WP,
MMC0_CD
uSD
Connector
SPI0 D0, D1, CS, CLK
SPI1 D0, D1, CS, CLK
Digital IC
Control/
Memory
UART1/LIN1 TX/RX
EQEP2_A/B,
EQEP2_INDEX,
EQEP2_STROBE
SDFM1_CLK2/D2,
SDFM1_CLK3/D3
Analog
Sensor
Feedback
EQEP2/SDFM1[3:2]
SDFM0_CLK[3:0], SDFM0_D[3:0]
PR0_IEP0_DATA_INOUT30
PR0_IEP0_EDC_SYNC_OUT1
EQEP0/SDFM1[1:0]
TCK, TDI, TDO, TMS
UART0
JTAG
UART
CAN Network
MCAN PHY
TCAN1042HGVDQ1
CAN Network
RGMII/MII 1Gbit
Ethernet PHY #1
DP83869HMRGZT
RJ-45
RGMII/MII 1Gbit
Ethernet PHY #2
DP83869HMRGZT
RJ-45
CPSW RGMII1/RMII1/MII1
Ethernet PHY #1
CPSW RMII2/RGMII2/MII2
PR0_PRU0, ICSSM_MII0
PR0_PRU1, ICSSM_MII1
IEP0_DATA/IEP0_EDC_SYNC
Isolation
JTAG
UART
25 MHz
Clock
RS
AM263x
REFCLKOUT
SDFM0
PR0_ICSSM MDIO
MUX
FSI1 Analog Sensor
Control/Feedback
Ethernet PHY #2
Key
Connector/Source/Load
Major IC
QSPI0_CLK,
QSPI0_CSn0,
QSPI0_D0,
QSPI0_D1,
QSPI0_D2,
QSPI0_D3,
QSPI Flash, 512 Mbyte
S25HL512TFAMHI010
WARMRSTN
STATUS OUTPUT
Ethernet PHY
2.5 V
Ethernet PHY
1.1 V
TI Launchpad XL Form-Factor
- AM263x MCU+
- Dual R5F ARM Safety Cores
- 5 Mbyte SRAM
- 512 Mbyte QSPI Flash Memory
- 1Mbyte I2C EEPROM Memory (board ID)
Analog
- 20x ADC input channels
- 1x DAC output channel
Control
- 10x ePWM output channels
- 2x EQEP encoder input channels
- 2x SFDM resolver input channels
- 4x FSI channels
Connectivity
- 2x UART
- 2x SPI
- 2x I2C
Industrial/Automotive Networking
- 2x PRU (Programmable Real-time Units)
- 2x MCAN
- 2x LIN
- 2x RGMII/RMII/MII Industrial Ethernet
Development
- Isolated, Embedded XDS110 JTAG/UART
PR0_IEP0_EDIO_DATA_IN_OUT31
PR0_IEP0_EDC_SYNC_OUT0
Analog Sensor
Feedback
Boosterpack
Headers
AM263x MCU+
Optional
VREF
JTAG and
UART Debug/
SBL Loading
MCAN PHY
TCAN1042HGVDQ1
ADC Calibration Source
Isolation
Isolation
System
Power
Figure 1-1. Typical AM263x System Block Diagram (Based on LP-AM263 Launchpad Design)
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This document should be referenced along with the other key AM263x collateral references. These include:
• The AM263x Sitara™ Microcontroller Data Sheet [1] is the primary resource for all device pinout and pin-level
multiplexing options.
• The SYSCONFIG [6] pinmux planning tool should be utilizing when starting a new AM263x pinout and driver
utilization.
• The AM263x Sitara™ Microcontroller Technical Reference Manual [2] documents detail each core and
peripheral subsystem from a conceptual, usage and programming model perspective.
• The AM263x MCU-SDK [10] ties the data sheet and technical reference manual together with core and
peripheral software usage examples.
1.1 Acronyms
Table 1-1. Acronyms Used in This Document
Acronym Description
EVM Evaluation Module. Referencing TI PCB assemblies such as the AM263x controlCard (TMDSCNCD263) or
AM263x LaunchPad (LP-AM263)
PDN Power Distribution Network. The active and passive components providing regulated power to a load such as the
AM263x MCU power pins.
EMI Electromagnetic Interference
PI Power Integrity
SI Signal Integrity
BOM Bill of Materials
2 Power
2.1 Discrete DC-DC Power Solution
The AM263x Launchpad and AM263x controlCard EVM designs both integrate a set of buck-converter, DC-DC
regulators that may be useful as a reference power solution for some systems. This solution consists of a pair of
TPS62913 buck-converter regulators for AM263x MCU core, system digital and analog I/O power, and a set of
TPS74801 LDO for powering paired industrial Ethernet PHY.
Current and transient requirements of the DC-DC closed-loop and passive power plane and decoupling network
are taken from the previously shown power consumption and transient loading tables. Many DC-DC regulators
can be matched to fit within these requirements and the maximum power consumption.
It is also recommended to use the power-good generation circuits available on these and similar DC-DC
regulators to drive the power on reset (PORz) into the AM263x.
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AM263x MCU+
VDD, VDDF,
VDDAR[3:1],
VDD_TEMP (1.2 V)
VDDS33 (3.3 V)
VDDA33 (3.3 V)
VDDS18_LDO (1.8 V)
VDDA18_LDO (1.8 V)
VDDS18 (1.8 V)
VDDA18,
VDDA18_OSC_PLL
(1.8 V)
5.0 V to 1.2 V / 3 A
TPS62913 Buck Converter
5.0 V to 3.3 V / 3 A
TPS62913 Buck Converter Ferrite (1 A)
5 V
Ethernet PHY 1.1 V /1.5 A
TPS74801DRCR LDO
Ethernet PHY 2.5 V / 1.5 A
TPS74801DRCR LDO
1.2 V
3.3 V
3.3 V
ADC_VREFHI_G0,
ADC_VREFHI_G0,
ADC_VREFHI_G0 (1.8 V)
DAC_VREF0,
DAC_VREF1 (1.8 V)
AND Gate
1.2 V Power Good
3.3 V Power Good
PORZ PORZ
VSYS_MONSystem 5 V R
D0.9 V REF
Ethernet PHY2.5 V
Ethernet PHY1.1 V
Optional
VREF
System 5 V
Figure 2-1. AM263x DC-DC Regulator Example Solution
EN/SYNC
1
S-CONF
10
VIN
6
FB 9
NR/SS 8
PG 5
PGND 4
SW 2
VO 3
PSNS
7
TPS62913RPUR
U29
GND
VSYS_5V0
GND
TPS62913_1_EN_SYNC
TPS62913_1_SCONF
TPS62913_1_SW
TPS62913_1_FB
TPS62913_1_NR_SS
VSYS_5V0
10.0k
R146
18.2k
R148
GND
470nF
25V
C160
GND
VSYS_5V0
35V
10µF
C167
35V
10µF
C168
GND
2.2uH
L2
74438356022
10V
47uF
C159
22µF
10V
C158
22µF
10V
C157
GND
VDD_AM263_1V2
2.49k
R153
4.99k
R154
VDD_AM263_1V2
GND
TPS62913_1_FB
PG_VDD_1V2
EN/SYNC Pin:
- Pulled to system 5.0 V, will enable
power-on as the rail passes through
1.01 V. Soft-start operation will occur
<1ms after startup.
S-CONF (Smart Config) Pin, 18.2 k

:
- 2.2 MHz switching frequency
- spread-spectrum disabled
- output discharge enabled
NR/SS:
470 nF provides 5mS soft-start time and
reasonable RC filter for noise performance
with internal reference source
FB:
Resistor divider to scale output voltage
nominal to 0.8 V reference voltage for
internal comparator
Figure 2-2. AM263x LP-AM263 Schematic Excerpt 1.2 V Core Power Implementation
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EN/SYNC
1
S-CONF
10
VIN
6
FB 9
NR/SS 8
PG 5
PGND 4
SW 2
VO 3
PSNS
7
TPS62913RPUR
U32
GND
VSYS_5V0
GND
TPS62913_2_EN_SYNC
TPS62913_2_SCONF
TPS62913_2_SW
TPS62913_2_FB
TPS62913_2_NR_SS
VSYS_5V0
10.0k
R156
18.2k
R160
GND
470nF
25V
C177
GND
VSYS_5V0
35V
10µF
C179
35V
10µF
C180
GND
2.2uH
L3
74438356022
10V
47uF
C171
22µF
10V
C170
22µF
10V
C169
GND
VSYS_3V3
4.99k
R163
GND
TPS62913_2_FB
15.4k
R162
PG_VSYS_3V3
VSYS_3V3
FB:
Resistor divider to scale output voltage
nominal to 0.8V reference voltage for
internal comparator
Figure 2-3. AM263x LP-AM263 Schematic Excerpt 3.3 V System Digital/Analog I/O Power Implementation
PG_VDD_1V2
PG_VSYS_3V3
PG_VDD_1V2
PG_VSYS_3V3
10.0k
R295
10.0k
R296
VSYS_3V3
Figure 2-4. AM263x LP-AM263 Schematic Excerpt – Power Good Implementation (see PORz Reset
Implementation as well)
2.2 Integrated PMIC Power Solution
To support integrated power and safety monitoring a power-management IC (PMIC) chip-set solution based on
the TPS653850-Q1 PMIC, TPS62130A buck-converter, and TPS3703A power supervisors is currently proposed.
For additional details on this PMIC safety solution offering, contact your local field sales team.
2.3 Power Decoupling and Filtering
Table 2-1 describes the initial BGA decoupling and power filtering required for the AM263x. These were based
on the initial simulation feedback of the Control Card EVM PCB and AM263x package with the above transient
use-cases.
The decoupling network presented in the below sections and in the AM263x EVM schematics and layouts
are reasonable starting points for any AM263x PCB design. However, due to specific PCB routing differences
and the resulting plane capacitance and decoupling mounting inductances and other parasitics, it is highly
recommended that designers simulate and measure their specific power distribution network performance.
Simulations and measurements should ideally be done with target application software active, and intended
operating environment conditions applied to the system.
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Table 2-1. AM263x Recommended Decoupling per Power Net
Device Supply Quantity Comment Part Number Manufacturer
VDD_CORE 2 2.2 µF, 6.3 V, ± 10%, X7R,
AEC-Q200 Grade 1, 0603
GCM188R70J225KE22D Murata
3 0.22 µF, 16 V,± 10%, X7R,
AEC-Q200 Grade 1, 0402
GCM155R71C224KE02D Murata
16 0.01 µF, 50 V, ± 10%,
X7R, AEC-Q200 Grade 1,
0402
CGA2B3X7R1H103K050B
B
TDK
VNWA 1 0.22 µF, 16 V, ± 10%,
X7R, AEC-Q200 Grade 1,
0402
GCM155R71C224KE02D Murata
1 0.01 µF, 50 V, ± 10%,
X7R, AEC-Q200 Grade 1,
0402
CGA2B3X7R1H103K050B
B
Murata
VDD_F 1 0.22 µF, 16 V, ± 10%,
X7R, AEC-Q200 Grade 1,
0402
GCM155R71C224KE02D TDK
1 0.01 µF, 50 V, ± 10%,
X7R, AEC-Q200 Grade 1,
0402
CGA2B3X7R1H103K050B
B
TDK
VDDAR_CORE 1 2.2 uF, 6.3 V, ± 10%, X7R,
AEC-Q200 Grade 1, 0603
GCM188R70J225KE22D Murata
2 0.22 µF, 16 V,± 10%, X7R,
AEC-Q200 Grade 1, 0402
GCM155R71C224KE02D Murata
1 Ferrite Bead, 120 Ω @
100 MHz, 2 A, 0603
742792625 Wurth
3 0.01 µF, 50 V, ± 10%,
X7R, AEC-Q200 Grade 1,
0402
CGA2B3X7R1H103K050B
B
TDK
VDDA18_LDO
VDDA18
VDDA18_OSC_PLL
VDDA18_TEMP
1 3.3 µF, 10 V, ± 10%, X5R,
0603
GRM188R61A335KE15D Murata
4 0.1 µF, 6.3 V, ± 10%, X7R,
0402
GRM155R70J104KA01D Murata
VDDS18_LDO
VDDS18
1 3.3 µF, 10 V, ± 10%, X5R,
0603
GRM188R61A335KE15D Murata
4 0.1 µF, 6.3 V, ± 10%, X7R,
0402
GRM155R70J104KA01D Murata
VDDS33 3 2.2 µF, 6.3 V, ± 10%, X7R,
AEC-Q200 Grade 1, 0603
GCM188R70J225KE22D Murata
4 0.22 µF, 16 V, ± 10%,
X7R, AEC-Q200 Grade 1,
0402
GCM155R71C224KE02D Murata
1 Ferrite Bead, 120 Ω @
100 MHz, 2 A, 0603
742792625 Wurth
7 0.01 µF, 50 V, ± 10%,
X7R, AEC-Q200 Grade 1,
0402
CGA2B3X7R1H103K050B
B
TDK
VDDA33 1 2.2 µF, 6.3 V, ± 10%, X7R,
AEC-Q200 Grade 1, 0603
GCM188R70J225KE22D Murata
2 0.22 µF, 16 V, ± 10%,
X7R, AEC-Q200 Grade 1,
0402
GCM155R71C224KE02D Murata
1 Ferrite Bead, 120 Ω @
100 MHz, 2 A, 0603
742792625 Wurth
3 0.01 µF, 50 V, ± 10%,
X7R, AEC-Q200 Grade 1,
0402
CGA2B3X7R1H103K050B
B
TDK
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GND
VDD_AM263_1V2
10V
3.3uF
C1
10V
3.3uF
C2
10V
3.3uF
C3
6.3V
1.0uF
C22
6.3V
1.0uF
C21
6.3V
1.0uF
C20
6.3V
1.0uF
C19
6.3V
1.0uF
C32
6.3V
1.0uF
C31
6.3V
1.0uF
C30
6.3V
1.0uF
C29
6.3V
1.0uF
C42
6.3V
1.0uF
C41
6.3V
1.0uF
C40
6.3V
1.0uF
C39
6.3V
1.0uF
C47
6.3V
1.0uF
C46
6.3V
1.0uF
C45
6.3V
1.0uF
C44
VDD_AM263_1V2
GND
10V
3.3uF
C52
10V
3.3uF
C53
16V
0.1uF
C56
16V
0.1uF
C55
16V
0.1uF
C54
VDD_AM263_1V2 VDD_AM263_1V2
GND GND
VDD_AM263_1V2
GND
16V
0.1uF
C50
16V
0.1uF
C49
16V
0.1uF
C51
VNWA 1V2 VDD_F 1V2 VDDA 1V2 Temperature
VDD 1V2 Core Digital VDDAR[3:1] 1V2 SRAM Array
Figure 2-5. AM263x LaunchPad Excerpt – 1.2 V Power Decoupling Schematic
VDDS 3V3 Digital
GND
VDDA 3V3 Analog
GND
VSYS_3V3 VDDA_AM263_3V3
VSYS_3V3
GND
6.3V
0.1uF
C7
6.3V
0.1uF
C8
6.3V
0.1uF
C9
6.3V
0.1uF
C10
6.3V
0.1uF
C11
6.3V
0.1uF
C12
6.3V
0.1uF
C13
6.3V
0.1uF
C24
6.3V
0.1uF
C26
6.3V
0.1uF
C27
6.3V
0.1uF
C28
10V
3.3uF
C4
10V
3.3uF
C5
10V
3.3uF
C6
10V
3.3uF
C23
1 2
FB1
BLM18EG121SN1D
10V
3.3uF
C25
Figure 2-6. AM263x LaunchPad Excerpt – 3.3 V Digital I/O and Analog I/O Decoupling and Filtering
Schematic
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VDDS 1V8 Digital
VDDA 1V8 Analog
VDDS_AM263_LDO_1V8
6.3V
0.1uF
C15
6.3V
0.1uF
C16
6.3V
0.1uF
C17
6.3V
0.1uF
C18
GND
6.3V
0.1uF
C34
6.3V
0.1uF
C38
GND
4.7µF
10V
C33
10V
3.3uF
C14
VDDA18_AM263_OSC_PLL
1 2
FB2
BLM18EG121SN1D
6.3V
0.1uF
C37
GND GND
VDDA_AM263_1V8_LDO
6.3V
0.1uF
C35
6.3V
0.1uF
C36
6.3V
0.1uF
C98
Figure 2-7. AM263x LaunchPad Excerpt – 1.8 V Digital I/O and Analog I/O Decoupling and Filtering
Schematic
4.7µF
10V
C89
6.3V
0.1uF
C90
GND
6.3V
0.1uF
C91
DAC_VREF
4.7µF
10V
C76
4.7µF
10V
C77
6.3V
0.1uF
C78
6.3V
0.1uF
C79
6.3V
0.1uF
C80
AM263_ADC_VREFHI_G01
AM263_ADC_VREFHI_G2
AM263_ADC_VREFLO_G01
AM263_ADC_VREFLO_G2
Figure 2-8. AM263x LaunchPad Excerpt – ADC and DAC VREF Decoupling Schematic
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2.4 Power Consumption
This section outlines the latest estimates of the AM263x power consumption on a per device power net basis.
These values may change as more power modeling and characterization is performed. This data can be used to
scale peak DC-DC conversion power margin, perform IR drop analysis of the PCB layout, and help with thermal
loading analysis.
These estimates are based on initial power simulations of the device. For the latest characterized, peak power
numbers, see the AM263x Sitara™ Microcontroller Data Sheet.
Also, a use-case based power estimation tool (PET) is provided for the AM263x MCU. This tool can help further
bound the peak power based on specific core and peripheral utilization duty-cycle.
Table 2-2. AM263x Estimated Peak Power Consumption
Device Supply V Peak mA Comment
VDD, VDDAR[3:1 ] 1.2 2500 Digital core power
VDDS33 3.3 200 3.3 V digital I/O power
VDDA33 3.3 100 3.3 V analog I/O power
2.5 Power Distribution Network
This section outlines the latest estimates of the AM263x transient current requirements on a per net basis. These
values may change as more power modeling and characterization is performed.
These transient use-case values were used to constrain the PDN design of the AM263x EVM (controlCard and
LaunchPad) by creating a set of minimum/maximum operating frequency and PDN impedance (Zmax) target
limits. These limits were based on the magnitude and slew-rate of simulated transient current use-cases. The
use-cases were used to estimate the PDN bandwidth needed to adequately decouple the resulting transient
event. Additional z-parameter simulation of the EVM PDN was used to verify that the power plane design and
decoupling placement and component values could then meet these limits. This is summarized in Figure 2-9.
Impedance
Magnitude (ohms)
Target
Zmax
Target
Fmax
Frequency (Hz)
Passing Specifications
Failing Specifications
Outside of
Specification
Fmin
Outside of
Specification
PDN Frequency Response
Figure 2-9. AM263x PDN Requirements – Example Diagram
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Table 2-3. AM263x Transient Current Model – Use-case Conditions
Transient
Case Net Name
Nominal
Voltage (V)
DC IR
Budget (%)
AC Ripple
Budget (%)
Idle Current
(mA)
Peak Current
(mA)
Idle to Peak
Slew Rate
(ns) Comment
VDD
BASELINE1
VDD 1.2 2.5 2.5 0 2402 2.5 Baseline,
simple
transient
model
assuming 0 to
peak
transition in
minimal 1
R5F clock
cycle.
VDD
XTAL_PLL1
VDD 1.2 2.5 2.5 42 875 10 XTAL to PLL
turn-on
transient
VDD WFI1 VDD 1.2 2.5 2.5 750 1117 12.5 4x RF5 WFI
event
transient
VDDS33
BASELINE1
VDDS33 3.3 2.5 2.5 0 84 2.5 Baseline,
simple
transient
model
assuming 0 to
peak
transition in a
single R5F
clock cycle
VDDA33
BASELINE1
VDDA33 3.3 2.5 2.5 0 34 2.5 Baseline,
simple
transient
model
assuming 0 to
peak
transition in a
single R5F
clock cycle
VDDS18LDO
BASELINE1
VDDS18LDO 1.8 2.5 2.5 0 01 2.5 Baseline,
simple
transient
model
assuming 0 to
peak
transition in
minimal 1
R5F clock
cycle
VDDA18LDO
BASELINE1
VDDA18LDO 1.8 2.5 2.5 0 66 2.5 Baseline,
simple
transient
model
assuming 0 to
peak
transition in
minimal 1
R5F clock
cycle
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Table 2-4. AM263x Transient Current Model – Resulting PDN Requirements
Transient
Case Net Name Fmax (MHz)
Current Step
(mA)
PCB DC
Tolerance
(mV)
PCB AC
Tolerance
(mV)
PCB Target
DC IR (mΩ)
PCB Target
AC Zmax
(mΩ) Comment
VDD
BASELINE1
VDD 200 2402 30 30 12 12 Baseline,
simple
transient
model
assuming 0 to
peak
transition in
minimal 1
R5F clock
cycle.
VDD
XTAL_PLL1
VDD 50 833 30 30 36 36 XTAL to PLL
turn-on
transient
VDD
WFI1
VDD 40 367 30 30 82 82 4x RF5 WFI
event
transient
VDDS33
BASELINE1
VDDS33 200 84 83 83 982 982 Baseline,
simple
transient
model
assuming 0 to
peak
transition in
minimal 1
R5F clock
cycle
VDDA33
BASELINE1
VDDA33 200 34 83 83 2419 2419 Baseline,
simple
transient
model
assuming 0 to
peak
transition in
minimal 1
R5F clock
cycle
VDDS18LDO
BASELINE1
VDDS18LDO 200 1 45 45 45 45 Baseline,
simple
transient
model
assuming 0 to
peak
transition in
minimal 1
R5F clock
cycle
VDDA18LDO
BASELINE1
VDDA18LDO 200 66 45 45 682 682 Baseline,
simple
transient
model
assuming 0 to
peak
transition in
minimal 1
R5F clock
cycle
2.5.1 Simulations
The following simulated PDN z-parameter performance was extracted from the LaunchPad and controlCard
layouts using Ansys SI wave. Wide-band s-parameter models of each of the selected capacitors were taken from
the manufacturer. Simulations capture only 25°C (room temperature) PCB and capacitor model performance.
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2.5.1.1 Core Digital Power 1.2 V
Z11 simulations were performed on the 1.2 V core digital power net of the LP-AM263 LaunchPad EVM to verify
transient power margin. The simulation domain included the:
• AM263x BGA (UI) 1.2 V digital and GND return fan-out
• Internal PCB 1.2 V and GND return planes
• Decoupling placed on the 1.2 V power net,
• U29 buck regulator output LC filter up to switch node
These simulations were done iteratively with multiple capacitor BOM changes made between each iteration.
Each iteration was characterized primarily by the maximum and minimum frequency bandwidth below Ztarget
(see above sections) and the BOM selection changed to maximize bandwidth and maximum Ztarget margin.
Only the initial and final chosen BOM iterations are shown in Figure 2-10 and Figure 2-11.
Figure 2-10. AM263x LaunchPad PDN Simulations – 1.2 V Core Power Simulation Domain
Figure 2-11. AM263x LaunchPad PDN Simulations – 1.2 V Core Power Simulated Z11
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• AM263x LaunchPad PDN Simulations – 1.2 V Core Power Simulated Z11
– This resulted in the marker (m2) point of 5.5 mΩ
– Ztarget requirement of 36mOhm maintained from 50 KHz to 63 MHz
– Major difference in BOM was replacing all 0.1 µF BGA and local decoupling capacitors with 1.0 µF
capacitors this entirely removed the 10 MHz resonant point in the PDN impedance spectrum
• PROC111E1_20210921 Initial simulations
– Major resonance at 10 MHz eliminated almost all margin against 36 mΩ Ztarget requirement
2.5.1.2 Digital/Analog I/O Power 3.3 V
Z11 simulations were performed on the 3.3 V digital and analog power net of the controlCard EVM to verify
transient power margin. The simulation domain included the:
• AM263x BGA (U1) 3.3V power and ground return BGA and fan-out
• Internal power and ground return routing layers
• Regulator output
Initial runs of these simulations showed that no BOM changes were needed to meet the maximum and minimum
frequency bandwidth below Ztarget (see above sections). Only the initial simulation with the final chosen BOM
iterations are shown below.
The simulations were divided between the VDDS33 digital 3.3 V plane and decoupling network and the VDDA33
analog 3.3 V traces and decoupling local to the design. The F dividing line between these simulations is the
FL18 ferrite bead element was used to separate these two decoupling performance simulations.
Figure 2-12. AM263x LaunchPad PDN Simulations – 3.3 V Digital/Analog I/O Power Simulation Domain
(A)
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Figure 2-13. AM263x LaunchPad PDN Simulations – 3.3 V Digital/Analog I/O Power Simulation Domain
(layer 8, bottom)
Figure 2-14. AM263x LaunchPad PDN Simulations – 3.3 V Digital I/O Power Simulated Z11
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Figure 2-15. AM263x LaunchPad PDN Simulations – 3.3 V Analog I/O Power Simulated Z11
2.6 e-Fuse Power
The AM263x, one-time programmable, e-Fuse memory can be utilized for storing customer cryptographic keys
and other information specific to individual devices. These e-Fuse memory locations can only be programmed
when the target device VPP, e-Fuse power pin, is powered by a 1.7V nominal output voltage, 100mA peak
power supply. This 1.7V VPP power supply can be onboard or off-board. The specific placement of the VPP
supply and implementation depend on how the e-Fuse memory will be utilized by the designer.
The e-Fuse programming typically follows one or both of the following scenarios:
•Factory programming – during post assembly test of the AM263x device, VPP is powered and the e-Fuses
are blown with the required sequence.
•Field programming – after the device has left the factory and is installed in the end-equipment, VPP is then
powered, and the e-Fuses are blown with the required sequence.
If the factory programming scenario is all that is required in a product, then it is typically preferable for the
VPP power supply to be off-board since this will reduce the number of supplies required to be placed on the
assembly. The VPP supply would only be used during this programming sequence, so keeping it on the board
would not be an efficient use of PCB floorplan area, cost or test time.
However, if the e-Fuse memory must be programmed outside the factory environment, the VPP power must
either be supplied from an onboard component or from an attached accessary board that can supply this power
as needed.
In the case of the TMDSCNCD263 controlCard evaluation module design, the VPP supply was left on the board
to enable convenient e-fuse programming by customers experimenting with this process. On the controlCard the
TLV75801PDRVR LDO, U66, was used to drop down the 3.3V system I/O voltage to the VPP 1.7V. Additionally,
the GPIO expander, U50 was used to toggle the VPP_LDO_EN pin to enable/disable the LDO in the required
sequence for e-Fuse programming.
For the full VPP electrical requirements and e-Fuse programming sequence, please see the AM263x datasheet,
section7.8 “VPP Specifications for One-Time Programmable (OTP) eFuses”.
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3 Clocking
3.1 Crystal and Oscillator Input Options
The AM263x XTAL_XI and XTAL_XO (pins T1 and R1) clock input can be sourced from either an attached
crystal or a single-ended oscillator output. The attached crystal should be a fundamental mode crystal operating
at 25 MHz. If operating from a single-ended oscillator output, the XTAL_XI pin should be connected to the
oscillator and the XTAL_XO pin must be left floating, unconnected on the PCB. In oscillator input mode, the
XTAL_XI pin can be tied to either a 1.8 V square-wave or sinewave oscillator. For full crystal and oscillator input
requirements, see the AM263x Sitara™ Microcontroller Data Sheet.
Figure 3-1. Excerpt From AM263x Control Card Schematics (for full crystal and oscillator input
requirements)
In the case of the AM263x Control Card, an onboard ABM10W-25.0000MHZ-8-K1Z-T3 25 MHz crystal provides
crystal mode clocking. Alternatively, an LMK1C1104PWR clock distributor circuit and SN74LV1T34 buffer
provide the 1.8 V square-wave clock to the XTAL_XI pin. The LMK1C1104PWR is also used to provide a clock
source to the onboard Ethernet PHY as well.
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Figure 3-2. Excerpt From AM263x controlCard Schematics - Oscillator Clock Source and Clock
Distributor
3.2 Output Clock Generation
The AM263x devices include two output clock sources, CLKOUT0 (pin M2) and CLKOUT1 (ping B16). These
are intended to be used to clock attached peripheral IC such as Industrial/Automotive Ethernet PHY. This can
save on BOM cost and additional IC placement and routing space. The AM263x Launchpad includes an optional
path for the CLKOUT0 (pin M2) signal to clock the onboard DP83869HMRGZT Ethernet PHY.
CLKOUT0/GPIO138 M2
EXT_REFCLK0/XBAROUT15/GPIO121/EQEP1_INDEX P2
PORz
R2
SAFETY_ERRORn D4
WARMRSTN
C3
XTAL_XI
T1
XTAL_XO
R1
U1C
AM263x_0p96
TP2
0
R4
AM263_CLKOUT0_R AM263_CLKOUT0 AM263_CLKOUT0
TP1
0R5AM263_RESETN_PB
AM263_XTAL_XI
AM263_XTAL_XO
AM263_WARMRSTN
AM263_PORZ
AM263_SAFETY_ERRORN
AM263_WARMRSTN
AM263_RESETN_PB
10.0k
R258
VSYS_3V3
AM263_EXT_REFCLK0
AM263_SAFETY_ERRORN
Figure 3-3. Excerpt From AM263x LaunchPad Layout – CLKOUT0 and EXT_REFCLK0 Output
3.3 Crystal Selection and Shunt Capacitance
In crystal operating mode, the AM263x can be interfaced to a wide variety of compatible crystals. Based on PCB
parasitic capacitance and crystal selected, the additional load capacitance needs to be modified to achieve the
best start-up stability and frequency accuracy.
For full crystal loading tolerances, see the AM263x Sitara™ Microcontroller Data Sheet.
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3.4 Crystal Placement and Routing
Crystal oscillator input should be placed as close as possible to the AM263x XTAL_XI/XO with minimal length
traces between crystal and AM263x pads. A ground ring shorted to the local VSS plane should be placed
adjacent and between the XTAL_XI and XTAL_XO traces to help prevent coupling from adjacent signals onto the
clock higher impedance crystal input paths.
Figure 3-4. Excerpt From AM263x Launchpad Layout - Crystal Layout and Ground Ring Structure
4 Resets
The AM263x MCU has two hardware reset sources:
• PORZ: Power on reset (logic low enable) signal, pin R2
– Should be driven from the power-good circuits of the associated 1.2 V core and 3.3 V I/O regulators
• WARMRSTN: Warm reset (logic low enable) input and reset status output signal, pin C3
– The power-on the default configuration sets this pin as open-drain output, which outputs the reset status of
the device.
– When the device enters reset, this signal is driven logic low.
– When the device is fully out of reset, this signal is driven logic high.
The PORZ is intended to be kept at logic low at initial startup of the system. Once each regulator sourcing the
AM263x power pins has been verified to be operating at nominal output voltage, then the PORZ signal can
be brought up to logic high. This action will start the AM263x boot ROM execution, beginning with sampling of
the SOP pins. The AM263x Launchpad implementation does this with a single SN74LVC1G11 AND gate which
takes in as input the open-drain output power-good signals from the onboard DC-DC regulators and an optional
push-button reset switch. A weak pull-down resistor is recommended on the PORZ signal to keep the signal
before startup of the system. PORz should be forced low if either 1.2 V or 3.3 V rail power goes below the
nominal operating range.
For a full description of the power-on and power-off reset sequencing requirements, see the AM263x Sitara™
Microcontroller Data Sheet.
GND
VSYS_3V3
0.1uF
C57
GND
GND
AM263_PORZ_PB
PG_VDD_1V2
PG_VSYS_3V3
PG_VDD_1V2
PG_VSYS_3V3
10.0k
R6
AM263_PORZ
AM263_PORZ_PB 4
1
3
6
U2A
GND 2 VCC
5
U2B
Figure 4-1. Excerpt From AM263x Launchpad Schematic – PORZ Generation
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The WARMRSTN pin is a multi-purpose software reset input and hardware reset status pin. In the power-on-
default configuration, this pin is configured as an open-drain output and requires an external pull-up resistor to
VDDS33 3.3 V I/O voltage rail. In this mode, WARMRSTN can be used as an MCU reset indicator and can be
used to drive reset input for attached peripheral IC such as Ethernet PHY and memories.
Figure 4-2. Excerpt From AM263x Control Card Schematic – PORZ and WARMRSTN Pinout
WARMRSTN can also be configured by software as software reset. Additional software reset sources are also
available on the AM263x devices. For more information on reset functionality, see the Reset chapter in the
AM263x Sitara™ Microcontroller Technical Reference Manual.
Because of the default open-drain configuration of this pin, if both the reset status output mode and the software
reset input mode is needed in a design, it is recommended that open-drain buffers be used to drive the optional
reset input status. In the case of the AM263x Control Card, a SN74LVC1G07 open-drain buffer is used to
optionally drive the push-button WARMRSTN without conflicting with the reset status output which is used to
reset the Ethernet PHY onboard during initial board power-on.
Figure 4-3. Excerpt From AM263x Control Card Schematic – WARMRESETN Push-Button Open-Drain
Driver
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5 Bootstrapping
The start-on-power (SOP) signals are used to latch in the selected boot mode into the AM263x device. During
the PORZ rising edge (low to high logic transition) the SOP[3:0] signals are sampled. The resulting 4 bits are
used to branch the boot ROM into the selected boot mode. Not all combinations are supported. For a full
description of the SOP pin states and supported boot modes, see the AM263x Sitara™ Microcontroller Data
Sheet.
5.1 SOP Signal Implementation
Each SOP[n] signal is multiplexed with a subset of QSPI and SPI peripheral functional mode signals as well. For
more information, see the signal description tables in the AM263x Sitara™ Microcontroller Data Sheet. The SOP
signal descriptions are excerpted below.
Table 5-1. SOP and Functional Mode Signal Mapping
Pin Number Primary Pinmux Signal SOP Mode Signal
N1 QSPI0_D0 SOP[0]
N4 QSPI_D1 SOP[1]
A11 SPI0_CLK SOP[2]
C10 SPI0_D0 SOP[3]
Because of this SOP/functional-mode multiplexing additional care must be taken in schematic and layout to
ensure that the SOP mode selection resistors, jumpers or switch paths are routed in such a way that the SOP
mode branches do not present inductive stubs to the functional mode signal paths. Failing to take care of this
may result in non-functional QSPI or SPI interfaces.
AM263_SOP2
AM263_SOP3
AM263_SOP2
AM263_SOP3
10.0kR173
10.0kR174
AM263_SPI0_CLK
AM263_SPI0_D0
AM263_SOP0
AM263_SOP1 AM263_SOP1
AM263_SOP0 10.0kR42
10.0kR43 AM263_QSPI0_D1
AM263_QSPI0_D0
Figure 5-1. Excerpt From AM263x Launchpad Schematic – SOP[3:0] Functional and SOP Paths
In the AM263x Control Card and Launchpad designs this SOP mode isolation is accomplished by including a
10KΩ resistor in the SOP signal path. The resistor is placed such as one pad is as close to the AM263x BGA
pad and in-line with the functional mode path. This creates a layout where the additional stub length necessary
to breakout the SOP path will only minimally impact the functional mode operation of the signals, as shown in
Figure 5-2 and Figure 5-3.
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