Texas Instruments CDCE62005EVM User manual

1 Features
2 General Description
3 Signal Path and Control
User's GuideSCAU024 – September 2008
Low Phase Noise Clock Evaluation Module — up to 1.5
GHz
•Easy-to-use evaluation module to generate lowphase noise clocks up to 1.5 GHz•Easy device programming via host-powered USBport
•Rapid configuration through provided EVM ControlSoftware
•Can be powered from the USB port, or by anexternal 3.3V power supply•Single-ended or differential input; external crystalcan be used with on-chip oscillator•Footprint for optional crystal filter on one output
Figure 1. CDCE62005EVM Evaluation Board
The CDCE62005 is a high performance, low phase noise frequency synthesizer and jitter cleaner. Itfeatures an on-chip PLL with dual integrated LC Voltage Controlled Oscillators (VCOs) operating from1.75–2.35 GHz. It provides support for three manually or automatically selected inputs, and provides up tofive differential, or ten single-ended, low-jitter outputs.
The CDCE62005 supports single-ended and differential input signals, as well as providing a crystaloscillator circuit that operates in conjunction with an external AT-cut crystal.
The CDCE62005 is programmed through an SPI interface using the supplied EVM programming graphicaluser interface (GUI).
The evaluation module (EVM) demonstrates the electrical performance of the device. Thisfully-assembled, factory-tested evaluation board allows complete validation of all device functions. Foroptimum performance, the board is equipped with 50 ΩSMA connectors and well-controlled 50 Ωimpedance microstrip transmission lines.
The CDCE62005 provides three selectable inputs – PRI REF, SEC REF, and AUX IN. The PRI REF andSEC REF inputs can accept up to 1500 MHz in the fan-out mode. In the PLL mode, PRI REF and SECREF can accept an input at up to 500MHz from a differential signal source, or up to 250MHz from a single
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4 Software Selectable Options
5 Installing the EVM Control Software and USB Driver
Software Selectable Options www.ti.com
ended CMOS signal source. The AUX IN allows the use of an external crystal in the frequency range of3.25MHz to 42MHz. The CDCE62005EVM provides a PC-board footprint for mounting a 5mm ×3,2mmSMD crystal. If the AUX IN is driven through the SMA connector, the on-board crystal must be removed,and R65 must be populated with a 0 ohm resistor. The CDCE62005EVM also provides support for drivingthe PRI REF signals from an on-board 5mm ×7mm crystal oscillator (U12).
The CDCE62005 provides up to five differential (LVDS or LVPECL) or ten single ended (LVCMOS) or anycombination of outputs up to 1.5 GHz (LVPECL). It operates as a jitter cleaner, or as a frequencysynthesizer, or both. An optional single ended output (AUX OUT) provides an LVCMOS copy of either thethird or fourth output. On the CDCE62005EVM the AUX OUT signal path has a footprint for an optionalcrystal filter (U13).
The CDCE62005 can use either a completely-internal loop filter, or a partially-external loop filter. Theloop-filter selection will affect the phase noise and loop stability of the PLL. If the CDCE62005 is to beused only as a frequency synthesizer, the completely internal loop filter option is recommended. If theCDCE62005 is used as a jitter cleaner, the partially external loop filter option is recommended, becausethis allows for lower loop bandwidths to be obtained using resistors and capacitors which are larger thanthe ones available on-chip.
The CDCE62005 options are selected by programming the on-chip registers. The CDCE62005 datasheetprovides the detailed information needed to configure and use this device.
Each of the five outputs of the CDCE62005 may be configured as an LVPECL, LVDS, or LVCMOS type.The CDCE62005 select/deselect the the 150 Ωload resistor required by the LVPECL output. Thecorresponding load resistor must be selected in the software interface when an output is configured asLVPECL.
The LVCMOS outputs can operate at frequencies up to 250MHz. The LVPECL outputs operate at up to1.5GHz (fan-out mode). The LVDS outputs operate at up to 800MHz.
The provided EVM Control Software (EVMCS) communicates with the CDCE62005 through a USBinterface through the CDCE62005 SPI port. The USB controller is normally powered over the USB cable,but can be optionally be powered by an external 5V DC adapter that is plugged into the additional powerconnector on the EVM. When the USB/SPI programming interface is available for use, the on-board LEDD25 is illuminated.
In addition to writing commands to the CDCE62005 SRAM while the board is powered, configurations canalso be stored in the on-chip EEPROM. This allows the EVM to start up in the desired configuration uponpowerup.
The CDCE62005 has a mode which permanently locks the EEPROM. After this mode is selected, theEEPROM contents within the CDCE62005 cannot be changed. This is useful when setting finalconfigurations.
The CDCE62005 EVMCS also allows device configurations to be saved into a configuration file (.INI),which can be loaded by the EVMCS at a later time to restore the saved settings.
The CDCE62005 EVMCS requires a Java Runtime Environment (JRE) to be installed. The latest JRE isavailable as a free download at http://java.com . Install the JRE first, before attempting to install theCDCE62005 EVMCS. To start the installation of the EVM software, double-click on the file named“ CDCE62005EVM-n_n_n-install.exe”, where n_n_n is the current software version number.
Note that the USB driver must be installed in the same installation folder as the EVMCS program file afterthe setup completes and the USB cable is connected (first time only).
After the setup wizard completes start the EVMCS from the start menu (Start →Texas Instruments Inc →CDCE62005 Software & Driver →CDCE62005).
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Program file and USB-controller
driver are in same location
www.ti.com Installing the EVM Control Software and USB Driver
Connect the USB cable to the EVM. If a box appears asking for an appropriate driver, Do not use theautomatic search option! Select a manual installation and when prompted for the driver location browseto the CDCE62005EVM program file folder that was used during instillation. If Windows does not ask for adriver, no action is needed.
After USB driver installation, the EVM software should connect properly and be ready for use. A greenlight in the USB Status and SPI Bus Status boxes indicates a good USB connection, and a dark lightindicates a faulty USB connection or a faulty SPI bus.
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5.1 CDCE62005 Control User Interface
5.2 Using the EVM Control Software
Installing the EVM Control Software and USB Driver www.ti.com
Figure 2. TI CDCE62005 EVMCS Display
The graphical layout of the EVMCS is based on the functional structure of the CDCE62005. Using theEVMCS, the system designer can change the Input Frequency, Input Divider, Input type, Input selection,PFD Charge Pump, Internal/External Loop Filter, Output MUX selection, Output Divider, and Output type.Other configurations are selected by the software with user-selectable options as described in the stepsbelow. If the CDCE62005EVM is USB powered, the “Enable EVM Power” check box must be checked. Ifthe CDCE62005 is powered from an external source, the “Enable EVM Power” check box must beunchecked.
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www.ti.com Installing the EVM Control Software and USB Driver
1. Primary/Secondary ReferenceThe primary or the secondary reference input buffer section on the EVMCS can be clicked for a popupwindow that opens, as shown in Figure 3 , showing selections on the external input signal type(differential or single ended), the external signal connection to the CDCE62005 primary/secondaryinputs (AC or DC termination), input-buffer internal termination (enabled or disabled), and theinput-buffer VBB voltage polarity (normal or inverted).
Figure 3. Input Buffer Properties
2. Reference Input Selection through Smart MUXThe Smart MUX section of the EVMCS can be clicked for a popup window that opens, as shown inFigure 4 , showing•Selections on the EECLKSEL option– “0” suggests using the REF_SEL pin for input selection and disabling the auto-select feature– “1” suggests using the auto-select feature and disabling the REF_SEL feature)– the Smart MUX reshaping (reshaping either or both of the primary and secondary input signals,introducing short delay to either or both of the primary and secondary input signals for fastoperation)
•Selection of the reference divider of the primary or the secondary input signal after the first of thetwo Smart MUX-es
Figure 4. Smart MUX
3. PFD and Charge Pump Selection
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Installing the EVM Control Software and USB Driver www.ti.com
The PFD and Charge Pump section of the EVMCS can be clicked for a popup window that opens, asshown in Figure 5 , showing selections for the charge pump current and charge pump pulse width. For theinternal loop filter, lower charge pump currents work well and for the external loop filter, higher chargepump currents work well.
Figure 5. Charge Pump
4. Loop Filter Selection
The Loop Filter section of the EVMCS can be clicked for a popup window that shows the internalloop-filter configuration, where the values of the resistors and capacitors of the active loop filter can beselected from the allowable dropdown list for each component.
Figure 6. Loop Filter, Internal Only
Alternately, the loop filter with additional external components can be enabled by clicking the “UseExternal Loop Filter Components” button and by enabling the appropriate DIPswitches (SW9 andSW10) on the bottom of the CDCE62005EVM as described in the “Configuring the Board” section ofthis User’s Guide. The external loop filter components (C4, R4 and C5) are in green in the picturedisplayed below. The component values entered into the text boxes are saved when a configurationfile is saved, and displayed when that configuration file is reloaded. However, the external componentvalues are not used by the EVMCS for calculations.
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www.ti.com Installing the EVM Control Software and USB Driver
Figure 7. Loop Filter, Additional External Components
5. Output MUX SelectionThe Output MUX section of the EVMCS for each of the five outputs can be clicked to open a popupwindow, shown in Figure 8 , showing each Output MUX clock source. These are selectable betweenthe primary input, secondary input, Smart MUX output or the PLL VCO core output.
Figure 8. Output MUX (each output channel)
6. Output Type SelectionThe Output buffer section of the EVMCS for each of the five outputs can be clicked to open a popupwindow that shows options for each output clock source. These are selectable between LVPECL, HighSwing LVPECL (in which cases the output 150 Ωtermination is automatically enabled), ReducedRange Link LVDS, General Purpose Link LVDS, LVCMOS (in which case each of the P and N act astwo separate LVCMOS outputs with the same frequency that can either be active, inverting, tri-state orlow) or each output can be disabled.
Figure 9. Output Buffer Config (each output)
7. PLL Dividers SelectionThe input, feedback and prescaler dividers can be selected by clicking on tabs in the EVMCS which
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6 Configuring the Board
Configuring the Board www.ti.com
opens a popup window displaying all the possible selections of those dividers. Care must be taken inchoosing these dividers, along with the VCO, charge pump and loop filter, such that the on-chip PLL ofthe CDCE62005 can operate in a stable closed-loop manner. Refer to the CDCE62005 data sheet forfurther information on appropriate configuration of the PLL for closed-loop operation. After the dividersare set accordingly, the PLL LOCK indicator display on the EVMCS are a bright green color. Also, theon-board LED D33 illuminates to indicate PLL lock. The output dividers for each output can also bechosen from possible selections displayed in the popup window, opened by clicking the output-dividertab in the EVMCS. Each output divider can also be disabled.8. Write to CDCE62005 EEPROM
To write any particular setting to the EEPROM (locked or unlocked), the menu item at the top of theEVMCS titled “Tool” must be clicked. This highlights the items “Write EEPROM Unlocked” and “WriteEEPROM Locked” as part of a drop-down menu. Choosing the appropriate one after setting the desiredPLL configurations writes to the EEPROM in its appropriate mode.
Figure 10. Tools – Write to EEPROM
Configuration for Programming and Testing (with USB cable attached) (Default Configuration)The CDCE62005EVM is configured by default to operate with the USB cable attached and a 3.3V powersupply added to EXT VDD and GND. In this configuration the USB microcontroller is powered by the USBport 5V supply, while the CDCE62005 is powered by the 3.3V external supply. This configuration is bestfor programming the CDCE62005 while also taking measurements. This configuration removes the powervariation found in USB power supplies by isolating the CDCE62005 from the USB supply.
Configuration for Programming (using USB power)The CDCE62005EVM can use power supplied through the USB cable as its sole power source. (Notrecommended for measurements) This capability is intended for saving configuration settings to theCDCE62005 and later powering the device from its internal memory (useful during performance testing ofthe device). In this configuration JP_3_3 must be moved from its default position to the new positionshown below. Also the “Enable EVM Power” box must be checked on the EVM display.
Configuration for On-board Reference Input BiasingIf the CDCE62005 on-chip biasing is not used for AC-coupled reference input signals for PRI_REF orSEC_REF, the CDCE62005EVM can alternately be set up to provide on-board biasing for LVPECL orLVDS inputs. These bias voltages of 1.2V for LVDS and 1.9V for LVPECL are derived from the on-boardvoltage regulator (U3). The bias points are available for every leg of the differential signals at bothPRI_REF and SEC_REF and can be enabled by using the jumpers on the CDCE62005EVM, JP_3_4 andJP_3_5 for PRI_REF and JP_3_6 and JP_3_7 for SEC_REF. Each of these jumpers can be configured asshown below for either LVPECL or LVDS bias.
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www.ti.com Configuring the Board
Configuration for On-board External Loop FilterIf the CDCE62005 is configured as a jitter cleaner, it requires the use of the partially-external loop filter,located on the bottom side of the CDCE62005EVM PC board. There are four external loop filter optionsprovided on the EVM. The external loop filter topology is as shown below.
The external loop filter can be chosen by selecting one from the four available options on theCDCE62005EVM using the dip switches, SW9 and SW10, located at the bottom side of the EVM andshown below.
Figure 11. External Loop Filter Selection Switches
Configuration for PLL Lock DetectThe CDCE62005 PLL lock detect can be chosen on the CDCE62005EVM as either an analog lock detector a digital lock detect using the jumper, JP_3_12, located at the back side of the CDCE62005EVM. Thisjumper can be configured as shown in Figure 12 for either analog or digital lock detect.
Figure 12. Lock Detect Select Jumper
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7 CDCE62005EVM Board Schematic Diagram
PUR
S2
+3V3
+5V
+5V
+3V3
+5V
+3V3 +3V3
+3V3
+3V3
+3V3 +3V3
VCC_IN
VCCA
+3V3
+3V3 +3V3
+3V3
VCC_PLL
+3V3
+3V3
+3V3
+3V3
+3V3
+3V3
LVDS_BIAS LVPECL_BIAS
VCC_VCO
VCC_OUT
+3V3
SDA SCL
POR
PWR_EN
VCC_OUT_ON VCCA_ON
PWR_EN
POR
VCC_OUT_ON VCCA_ON
PS_RESET
SCL SDA
Y0_150_TERM Y1_150_TERM Y2_150_TERM Y3_150_TERM Y4_150_TERM
PS_RESET
PLL_LOCK
SPI_MISO SPI_CLK SPI_MOSI SPI_LE AUX_SEL REF_SEL PD_ RESET_ MODE_SEL LVPECL_BIAS_PG LVDS_BIAS_PG
OSC_EN
MMBT4401
NPN
Device Communication
External 3.3V Power
(EXT Supply 5V)
22uF/20V Kemet T495D226(1)020A(2)4095
PLL LOCK
CD MODE
ALL Flashing = Error see GUI
S2,S3 = 0,0 = Aries LAB EVM
MANY VIAS with Heat Sink
BIG THERMAL VIAS for all POWER & GND
1.2V Ref Voltage 1.9V Ref Voltage
0805 Foot Print 0805 Foot Print
Lock Analog
Lock Digital
EXT VCC
GND
+
C35
22uF/20V Low ESR
+
C35
22uF/20V Low ESR
12
R79
249
R79
249
C37
10uF/6.3V
C37
10uF/6.3V
C42
0.1uF
C42
0.1uF
1
3
2
JP_3_12JP_3_12
EN#
3
IN1
5OUT1 7
SENSE 1
OUT2 8
IN2
6
GND
4RESET# 2
U2
TPS77333DGK
U2
TPS77333DGK
1 2
R142
10k
R142
10k
C46
10uF/6.3V
C46
10uF/6.3V
1
2
R52
1.5k
R52
1.5k
C38
1uF
C38
1uF
1 2
R111
4.7k
R111
4.7k
C64
10uF/6.3V
C64
10uF/6.3V
12
R31 1.5k R31 1.5k
P7
EXT-VCC
P7
EXT-VCC
1 2
R106
10k
R106
10k
12
R50
1M
R50
1M
12
R87 4.7K R87 4.7K
1 2
R51
1.5k
R51
1.5k
1 2
R116
68.1
R116
68.1
12
L6
BLM15HD102SN1D
L6
BLM15HD102SN1D
Vcc 8
SDA 5
A0
1
A1
2
A3
3
Vss
4SCL 6
WP 7
U4 24LC512 U4 24LC512
1 2
R109
10k
R109
10k
C74
10uF/6.3V
C74
10uF/6.3V
3
1
2
Q6
2N2222A
Q6
2N2222A
1 2
R115
49.9
R115
49.9
1 2
R117
86.6
R117
86.6
12
C32
33pF
C32
33pF
1 2
R166
10k
R166
10k
1 2
R49
1.5k
R49
1.5k
C48
10uF/6.3V
C48
10uF/6.3V
1 2
R167
10k
R167
10k
1 2
R58
10k
R58
10k
12
L7
BLM15HD102SN1D
L7
BLM15HD102SN1D
1 2
R143
10k
R143
10k
+
C31
22uF/20V Low ESR
+
C31
22uF/20V Low ESR
C59
0.1uF
C59
0.1uF
12
C29
33pF
C29
33pF
1 2
R138
4.7k
R138
4.7k
1 2
R129
4.7k
R129
4.7k
1 2
R110
10k
R110
10k
D8
MBRS2040LT3
D8
MBRS2040LT3
12
R733 R733
1 2
R144
10k
R144
10k
1
2
R515k R515k
3
1
2
Q1
2N2222A
Q1
2N2222A
12
R85
453
R85
453
GND
3
GND/HS
1GND/HS 20
NC1 18
GND/HS 19
GND/HS
2
NC2 17
NC
4
EN_
5
IN1
6
IN2
7
_RESET 16
FB 15
OUT2 14 OUT1 13
GND/HS 12 GND/HS 11
GND/HS
9
GND/HS
10
NC3
8GND/PWRPAD 21
U3
TPS76701QPWP
U3
TPS76701QPWP
12
R633 R633
1 2
R112
4.7k
R112
4.7k
12
R102301 R102301
12
R41.5k R41.5k
DM0
19 DP0 18
SDA
11
X1
61
X2
60
GND2
24 GND1
5
SCL
12
PUR
17
TEST1
15 TEST0 14
GND3
42
RST
13
GND4
59
VCC1
10
VCC2
39
P3.0/RxD/S0 58
P3.1/TxD/S1 57
P3.2 56
P3.4/T0 54
P0.0 43 P0.1 44 P0.2 45 P0.3 46 P0.4 47 P0.5 48 P0.6 49 P0.7 50
VCC3
62
SUSP
16
P1.0 31 P1.1 32 P1.2 33 P1.3 34 P1.4 35 P1.5 36 P1.6 40 P1.7 41 P2.0 22 P2.1 23 P2.2 25 P2.3 26 P2.4 27 P2.5 28 P2.6 29 P2.7 30
VREN
38
VDDOUT
37
S2 8 S3 9
P3.3/INT1# 55
P3.5 53 P3.6 52 P3.7 51
SELF/BUS
21
TEST2
20
1
1
2
2
3
3
4
4
6
6
7
7
63
63
64
64
U1
TUSB3210
U1
TUSB3210
D25
LED GREEN
D25
LED GREEN
12
R86100k R86100k
12
R123301 R123301
1 3
2
JP_3_3JP_3_3
C43
1uF
C43
1uF
12
R21 15K R21 15K
C70
10uF/6.3V
C70
10uF/6.3V
D33
LED GREEN
D33
LED GREEN
C40
0.1uF
C40
0.1uF
3 1 2 4
5 6
+5V
DM
DP
GND
J1
Type B USB-Shield
+5V
DM
DP
GND
J1
Type B USB-Shield
D26
LED GREEN
D26
LED GREEN
C73
10uF/6.3V
C73
10uF/6.3V
1 2
R59
10k
R59
10k
P5
GND
P5
GND
12
R30 1.5k R30 1.5k
12
R103301 R103301
C68
10uF/6.3V
C68
10uF/6.3V
12
12MHZ1
SE3409-ND
12MHZ1
SE3409-ND
C33
1uF
C33
1uF
D34
LED GREEN
D34
LED GREEN
12
L8
BLM15HD102SN1D
L8
BLM15HD102SN1D
C47
0.1uF
C47
0.1uF
1 2
R118
49.9
R118
49.9
1
2
3
J3J3
C81
10uF/6.3V
C81
10uF/6.3V
12
43
5
RESET1RESET1
C41
0.1uF
C41
0.1uF
1 2
R108
4.7k
R108
4.7k
D9
MBRS2040LT3
D9
MBRS2040LT3
12
R114301 R114301
1
2
R53
1.5k
R53
1.5k
CDCE62005EVM Board Schematic Diagram www.ti.com
Low Phase Noise Clock Evaluation Module — up to 1.5 GHz10 SCAU024 – September 2008Submit Documentation Feedback

EXT_LFN
EXT_LFP
EXT_LFN
EXT_LFP
PLL LOOP FILTER
Low Inducatnace Filter ( Layout)
LOOP BW ~
FILTER 1
FILTER 2
FILTER 3
FILTER 4
JUST for TEST
LOOP BW ~ 650Hz CP=3mA LOOP BW ~ LOOP BW ~ (R3 = 5K , C3 = 20pF)
(R3 = 5K , C3 = 120pF)
(R3 = 5K , C3 = 120pF)
(R3 = 5K , C3 = 120pF)
1 2
8 7
3 4
6 5
SW9
TDA04H0SK1
SW9
TDA04H0SK1
1
2
R82 0 R82 0
12
R74
5.1
R74
5.1
1 2
8 7
3 4
6 5
SW10
TDA04H0SK1
SW10
TDA04H0SK1
12
R88
5.1
R88
5.1
C106
10uF
C106
10uF
12
R76
5.1
R76
5.1
C116
100uF
C116
100uF
C105
1uF
C105
1uF
12
R75-NP
1.09K
R75-NP
1.09K C109 4.7uF X5R-NP
C109 4.7uF X5R-NP
C114
47uF
C114
47uF
12
R81 0 R81 0
C115
10uF
C115
10uF
C107 0.27uF-NP C107 0.27uF-NP
C111
4.7uF
C111
4.7uF
12
R75
5.1
R75
5.1
C110
22uF
C110
22uF
C108
2.2uF
C108
2.2uF
www.ti.com CDCE62005EVM Board Schematic Diagram
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VCC_OUT VCC_OUT VCC_OUT VCC_OUT VCC_OUT
YP0 YN0 YP1 YN1 YP2 YN2 YP3 YN3 YP4 YN4
Y0_150_TERM Y1_150_TERM Y2_150_TERM Y3_150_TERM Y4_150_TERM
YP0 YN0 YP1 YN1 YP2 YN2 YP3 YN3 YP4 YN4
OUTPUT CLOCKS
YP0 YN0 YP1 YN1 YP2 YN2 YP3 YN3 YP4
YN4
12
R218 150R218 150
2
3
1
4
5
J45
SMA-EDGE J45 SMA-EDGE
12R217
10k
R217
10k
2
3
1
4
5
J36
SMA-EDGE J36 SMA-EDGE
12
R231 150R231 150
2
3
1
4
5
J39
SMA-EDGE J39 SMA-EDGE
2
3
1
4
5
J43
SMA-EDGE J43 SMA-EDGE
Q55
FDV303N
Q55
FDV303N
12
R226 150R226 150
1 2
R220
0 -NP
R220
0 -NP
Q58
FDV303N
Q58
FDV303N
Q54
FDV303N
Q54
FDV303N
2
3
1
4
5
J48
SMA-EDGE J48 SMA-EDGE
Q62
FDV303N
Q62
FDV303N
1 2
R224
0 -NP
R224
0 -NP
Q60
FDV303N
Q60
FDV303N
1 2
R214
0 -NP
R214
0 -NP
2
3
1
4
5
J35
SMA-EDGE J35 SMA-EDGE
12
R216 150R216 150
1 2
R234
0 -NP
R234
0 -NP
C120
0.1uF
C120
0.1uF
12
R223 150 R223 150
1 2
R229
0 -NP
R229
0 -NP
C119
0.1uF
C119
0.1uF
12
R213 150R213 150
Q56
FDV303N
Q56
FDV303N
12R222
10k
R222
10k
C131
0.1uF
C131
0.1uF
Q57
FDV303N
Q57
FDV303N
C130
0.1uF
C130
0.1uF
1 2
R225
0 -NP
R225
0 -NP
2
3
1
4
5
J49
SMA-EDGE J49 SMA-EDGE
12R212
10k
R212
10k
C88
0.1uF
C88
0.1uF
1 2
R215
0 -NP
R215
0 -NP
C87
0.1uF
C87
0.1uF
C90
0.1uF
C90
0.1uF
Q45
FDV303N
Q45
FDV303N
12
R233 150R233 150
12R232
10k
R232
10k
2
3
1
4
5
J34
SMA-EDGE J34 SMA-EDGE
C86
0.1uF
C86
0.1uF
1 2
R219
0 -NP
R219
0 -NP
12
R228 150R228 150
12R227
10k
R227
10k
Q61
FDV303N
Q61
FDV303N
1 2
R235
0 -NP
R235
0 -NP
2
3
1
4
5
J32
SMA-EDGE J32 SMA-EDGE
Q59
FDV303N
Q59
FDV303N
12
R221 150R221 150
C89
0.1uF
C89
0.1uF
C84
0.1uF
C84
0.1uF
1 2
R230
0 -NP
R230
0 -NP
2
3
1
4
5
J41
SMA-EDGE J41 SMA-EDGE
12
R211 150 R211 150
CDCE62005EVM Board Schematic Diagram www.ti.com
Low Phase Noise Clock Evaluation Module — up to 1.5 GHz12 SCAU024 – September 2008Submit Documentation Feedback

VCC_IN
VCC_IN
VCC_VCO
VCCA
VCC_OUT
VCC_VCO
VCC_PLLVCC_PLL
VCC_PLL VCC_PLL
VCC_IN
VCC_OUT VCC_OUT
VCC_OUT
VCC_OUT
YP0 YN0 YP2 YN2 YP4 YN4 YP1 YN1 YP3 YN3
PRI_REFP PRI_REFN SEC_REFP SEC_REFN
SPI_CLK
SPI_MOSI SPI_MISO
SPI_LE
MODE_SEL
TESTOUTA
VBB
PLL_LOCK
RESET_
PD_
AUX_IN EXT_LFP EXT_LFN
REF_SEL TESTOUTA
PAD
R
VCC_OUT
C
AUX OUT
61.44MHz Filter
C82
10uF/6.3V
C82
10uF/6.3V
C154
0.1uF
C154
0.1uF
C145
0.1uF
C145
0.1uF
12
L5
BLM15HD102SN1D
L5
BLM15HD102SN1D
C162
0.1uF
C162
0.1uF
C156
0.1uF
C156
0.1uF
TESTOUTA 30
VCC_AUXIN
44
VCC_AUXOUT
15
VCC2_PLL
39
VCC6 8
U0N 28
U0P 27
VCC5 11
U1N 20
U1P 19
VCC4 18
U2N 17
U2P 16
VCC3 21
SPI_MISO 22
MODE_SEL 33
POWER_DOWN
12
AUX_OUT
13
VCC0 26
U3N 10
U3P 9
VCC2 29
U4N 7
U4P 6
VCC1 32
REG_CAP2
38
GND_VCO
36
VCC_VCO
34
REF_SEL 31
SPI_CLK 24
SPI_LE 25
SPI_MOSI 23
REG_CAP1
4
RESET
14
VCC1_PLL
5VCC2_PLL
42
SEC_REF+
3
SEC_REF-
2
VCC_IN
1
PRI_REF+
45
PRI_REF-
46
VCC_IN
47
VBB 48
EXT_LFP
40
AUX_IN
43
EXT_LFN
41
PLL_LOCK
37
VCC_VCO
35
THERMAL_PAD
49
U5
CDCE62005
U5
CDCE62005
C155
0.1uF
C155
0.1uF
C150
0.1uF -NP
C150
0.1uF -NP
C157
0.1uF
C157
0.1uF
12
R133
0
R133
0
IN
1
GND4 7
OUT 5
GND3 8
GND2
4GND1 3GND5 6
GND
2
U13
Xtal Fltr 61.44Mhz
U13
Xtal Fltr 61.44Mhz
C148
0.1uF
C148
0.1uF
C151
0.1uF
C151
0.1uF
C152
0.1uF
C152
0.1uF
C161
0.1uF
C161
0.1uF
C160
0.1uF
C160
0.1uF
2
3
1
4
5
J46
SMA-EDGE
J46
SMA-EDGE
C158
0.1uF
C158
0.1uF
12
R141 50 R141 50
C144
0.1uF
C144
0.1uF
1 2
R94
0
R94
0
C159
0.1uF
C159
0.1uF
C141
0.1uF
C141
0.1uF
C149
0.1uF
C149
0.1uF
C142
0.1uF
C142
0.1uF
C75
2.2uF
C75
2.2uF
C163
0.1uF
C163
0.1uF
C83
10uF/6.3V
C83
10uF/6.3V
12
R134
0
R134
0
C147
0.1uF
C147
0.1uF
1
2
R95 100 R95 100
C146
0.1uF
C146
0.1uF
www.ti.com CDCE62005EVM Board Schematic Diagram
SCAU024 – September 2008 Low Phase Noise Clock Evaluation Module — up to 1.5 GHz 13Submit Documentation Feedback

LVPECL_BIAS LVPECL_BIAS LVPECL_BIAS LVPECL_BIAS
LVDS_BIAS LVDS_BIAS LVDS_BIAS LVDS_BIAS
+3V3
PRI_REFN PRI_REFP
SEC_REFN SEC_REFP
AUX_IN
OSC_EN
PRI_REFN PRI_REFP
INPUT CLOCK PRI INPUT CLOCK SEC
LAYOUT Critical
AUX IN
SEC_REFN SEC_REFP
PRI_REFP
PRI_REFN
LVDS
BIAS
LVDS
LVPECL
LVPECL
BIAS BIAS BIAS
LVDS LVDS
LVPECL LVPECL
2
3
1
4
5
J104 SMA-EDGEJ104 SMA-EDGE
12
R136
49.9 R136 49.9
C71
1uF
C71
1uF
12
R137
49.9
R137
49.9
C85
5pf -NP
C85
5pf -NP
C65
1uF
C65
1uF
1
3
2
JP_3_7JP_3_7
C67
1uF
C67
1uF
C76
0.1uF
C76
0.1uF
C36
1uF
C36
1uF
C69
1uF
C69
1uF
1
3
2
JP_3_4JP_3_4 C50
1uF
C50
1uF
C57
1uF
C57
1uF
C80
0.1uF
C80
0.1uF
OE
1VCC 6
NC/OUTN 5
OUT/ OUTP 4
GND
3
NC
2
U12
PE7745DU-30.72M
U12
PE7745DU-30.72M
C77
0.1uF
C77
0.1uF
C58
1uF
C58
1uF
12
R130
49.9
R130
49.9
C78
0.1uF
C78
0.1uF
1
3
2
JP_3_6JP_3_6
12
L9
BLM15HD102SN1D
L9
BLM15HD102SN1D
12
R132
49.9
R132
49.9
1
2R65
100k -NP R65 100k -NP
C66
1uF
C66
1uF
2
3
4
5
1
J213
SMA-VERT
J213
SMA-VERT
C79
0.1uF
C79
0.1uF
12
R135 49.9 - NP R135 49.9 - NP
2
3
1
4
5
J103 SMA-EDGEJ103 SMA-EDGE
12
R131
49.9
R131
49.9
1
3
2
JP_3_5JP_3_5
2
3
1
4
5
J203
SMA-EDGE
J203
SMA-EDGE
12
3
4 56
25.00MhzCrystal Crystal 25.00 MHz 25.00MhzCrystal Crystal 25.00 MHz
2
3
1
4
5
J204 SMA-EDGEJ204 SMA-EDGE
CDCE62005EVM Board Schematic Diagram www.ti.com
Low Phase Noise Clock Evaluation Module — up to 1.5 GHz14 SCAU024 – September 2008Submit Documentation Feedback

www.ti.com CDCE62005EVM Board Schematic Diagram
EVALUATION BOARD/KIT IMPORTANT NOTICE
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATIONPURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling theproduct(s) must have electronics training and observe good engineering practice standards. As such, the goods being provided arenot intended to be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations,including product safety and environmental measures typically found in end products that incorporate such semiconductorcomponents or circuit boards. This evaluation board/kit does not fall within the scope of the European Union directives regardingelectromagnetic compatibility, restricted substances (RoHS), recycling (WEEE), FCC, CE or UL, and therefore may not meet thetechnical requirements of these directives or other related directives.Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/kit may be returned within 30days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BYSELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDINGANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE.The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from allclaims arising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility totake any and all appropriate precautions with regard to electrostatic discharge.EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE TO THE OTHERFOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not exclusive.
TI assumes no liability for applications assistance, customer product design, software performance, or infringement ofpatents or services described herein.
Please read the User’s Guide and, specifically, the Warnings and Restrictions notice in the User’s Guide prior to handling theproduct. This notice contains important safety information about temperatures and voltages. For additional information on TI’senvironmental and/or safety programs, please contact the TI application engineer or visit www.ti.com/esh .No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine, process, orcombination in which such TI products or services might be or are used.
SCAU024 – September 2008 Low Phase Noise Clock Evaluation Module — up to 1.5 GHz 15Submit Documentation Feedback

CDCE62005EVM Board Schematic Diagram www.ti.com
EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the input voltage range of 3 V to 3.6 V and the output voltage range of 0 V to 3.6 V.Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there arequestions concerning the input range, please contact a TI field representative prior to connecting the input power.Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to theEVM. Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the loadspecification, please contact a TI field representative.During normal operation, some circuit components may have case temperatures greater than 120 °C. The EVM is designed tooperate properly with certain components above 85 °C as long as the input and output ranges are maintained. These componentsinclude but are not limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types ofdevices can be identified using the EVM schematic located in the EVM User's Guide. When placing measurement probes nearthese devices during operation, please be aware that these devices may be very warm to the touch.
16 Low Phase Noise Clock Evaluation Module — up to 1.5 GHz SCAU024 – September 2008Submit Documentation Feedback

IMPORTANT NOTICE
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