Texas Instruments TPSM33625EVM User manual

User’s Guide
TPSM33625, TPSM3365F Evaluation Module
ABSTRACT
The TPSM33625EVM and TPSM33625FEVM enables the evaluation of the TPSM33625 and TPSM33625F
power modules. The EVMs allow for several configurations of the power module. Additionally, electrical test
points provide ease in verifying the performance of the power regulator. Lastly, these EVMs serve as a basis for
the TPSM33625 and TPSM33625F layout and component selection.
CAUTION
!
Read the user's guide before use.
CAUTION
Hot surface! Contact can cause burns. Do not touch!
Table of Contents
1 Introduction.............................................................................................................................................................................3
2 Setup Procedure..................................................................................................................................................................... 4
3 Test Setup................................................................................................................................................................................5
4 Schematic................................................................................................................................................................................7
5 TPSM33625EVM and TPSM33625FEVM Evaluation............................................................................................................ 9
6 Layout.................................................................................................................................................................................... 13
7 Bill of Materials..................................................................................................................................................................... 17
8 Related Documentation........................................................................................................................................................18
9 Revision History................................................................................................................................................................... 19
List of Figures
Figure 3-1. Test Setup Diagram...................................................................................................................................................6
Figure 4-1. Schematic-Compliance Testing Filter........................................................................................................................ 7
Figure 4-2. Schematic (TPSM33625EVM) – TPSM33625.......................................................................................................... 7
Figure 4-3. Schematic (TPSM33625FEVM) – TPSM33625F...................................................................................................... 7
Figure 4-4. Schematic (TPSM33625EVM) – Configuration Jumpers and Evaluation Test Points...............................................8
Figure 4-5. Schematic (TPSM33625FEVM) – Configuration Jumpers and Evaluation Test Points.............................................8
Figure 5-1. CISPR32 Conducted Scan........................................................................................................................................9
Figure 5-2. CISPR32 Conducted Scan........................................................................................................................................9
Figure 5-3. IR Top Case Measurement......................................................................................................................................10
Figure 5-4. IR Top Case Measurement......................................................................................................................................10
Figure 5-5. IR Top Case Measurement......................................................................................................................................11
Figure 5-6. IR Top Case Measurement......................................................................................................................................11
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Figure 5-7. IR Top Case Measurement......................................................................................................................................12
Figure 5-8. IR Top Case Measurement......................................................................................................................................12
Figure 6-1. PCB Top 2-D (TPSM33625EVM)............................................................................................................................ 13
Figure 6-2. PCB Top 2-D (TPSM33625FEVM).......................................................................................................................... 13
Figure 6-3. PCB Bottom 2-D......................................................................................................................................................14
Figure 6-4. Top Layer.................................................................................................................................................................14
Figure 6-5. Mid Layer 1..............................................................................................................................................................15
Figure 6-6. Mid Layer 2..............................................................................................................................................................15
Figure 6-7. Bottom Layer........................................................................................................................................................... 16
List of Tables
Table 1-1. EVM Overview............................................................................................................................................................ 3
Table 2-1. Suggested Frequency and Output Voltage Settings................................................................................................... 4
Table 3-1. Description of Jumpers, Test Points, and Terminal Blocks......................................................................................... 5
Table 7-1. Bill of Materials..........................................................................................................................................................17
Trademarks
All trademarks are the property of their respective owners.
Trademarks www.ti.com
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1 Introduction
The output voltage of the TPSM33625EVM and TPSM33625FEVM can be configured from 1.8 V to 12 V with
a load current up to 2.5 A. Measurement points are provided to easily measure conversion efficiency and look
at other performance metrics. In addition, jumpers and test points are provided to evaluate the features of the
TPSM33625 and TPSM33625F, such as programmable enable UVLO, adjustable switching frequency and mode
select (or synchronization), and power-good flag.
The EVM layout allows the TPSM33625 and TPSM33625F and the orderable part numbers to be installed, and
their specific features to be evaluated. The TPSM33625EVM comes installed with the TPSM33625RDNR, the
adjustable switching frequency (RT pin) version of the TPSM33625. The TPSM33625FEVM comes installed with
the TPSM33625FRDNR, the fixed 1-MHz version of the TPSM33625 with mode selection and synchronization
pin.
The TPSM33625EVM is configured by default to be enabled with an output voltage of 5 V, and a switching
frequency of 2.2 MHz with frequency foldback (auto mode) at light load. The TPSM33625FEVM is configured
by default to be enabled with an output voltage of 5 V, and configured for auto mode. The following sections
outline the step-by-step procedure to use the TPSM33625EVM and TPSM33625FEVM and the performance that
is exhibited.
Table 1-1. EVM Overview
EVM Buck Regulator Buck Features
TPSM33625EVM TPSM33625RDNR
Output: 3.3 V/ADJ (1-15 V)
Fsw: ADJ
Mode: Auto
TPSM33625FEVM TPSM33625FRDNR
Output: 5 V/ADJ (1-15 V)
Fsw: 1 MHz
Mode: Auto/FPWM
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2 Setup Procedure
The following procedure outlines the steps to be taken for using the TPSM33625EVM and TPSM625FEVM. Use
this section in conjunction with Section 3 to correctly setup the EVM.
1. Determine the output voltage that is to be evaluated, then reference Section 2. This table provides the
recommended jumper configurations.
2. After making any required changes, confirm that the output voltage is within a couple percent of the set
output voltage.
3. Verify the performance of the EVM and compare with applicable curves within this user's guide.
4. Consult on e2e if there are concerns in the evaluation of this device.
Table 2-1. Suggested Frequency and Output Voltage Settings
VOUT (V) Suggested Frequency
1.8 300 kHz
2.5 800 kHz
3.3 1 MHz
51 MHz (J4: 3 – 4) *2.2 MHz can improve transient response for given
output capacitance.
12 2.2 MHz
Setup Procedure www.ti.com
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3 Test Setup
Table 3-1. Description of Jumpers, Test Points, and Terminal Blocks
Reference Designator Description
J1 Input to series, PI filter for EMC compliance testing. Note polarity, which is annotated in the silkscreen.
Connect to a terminal block with a short, thick gauge (18AWG) wire.
TP1, TP2
VIN test points that bypass the EMC filter and connect directly to input capacitors. Enables more accurate
efficiency measurements as well as potential parasitic minimization and signal integrity of AC measurements.
Connect to test points with a short, thick gauge (18AWG) wire.
TP4 PGOOD test point for verifying PGOOD (output) flag feature.
TP3, TP6
VOUT test points connected directly to output capacitors. Enables more accurate efficiency measurements, as
well, potential parasitic minimization and signal integrity of AC measurements. Connect to test points with a
short, thick gauge (18AWG) wire.
J2 Output (VOUT) terminal block. Connect to terminal block with a short, thick gauge (18AWG) wire.
TP11, TP12 EN test point for accurately measuring EN voltage. If EN voltage is to be applied (externally), resistor R2 and
R4 potentially can need to be removed.
J5 Disable the regulator by shorting the pins of the jumper.
J4
TPSM33625EVM:
Jumper for configuring the switching frequency of the converter. Using the "key" annotated in the schematic
and also in the silkscreen.
Placing the jumper on the adjacent pins sets the annotated switching frequency.
TPSM33625FEVM:
Jumper for configuring the mode or for external signal source synchronization. The EVM is configured for
fixed 1-MHz operation. The mode is set by using the "key" annotated in the schematic and also in the
silkscreen, and by placing the jumper on the pins next to the annotated mode.
Auto mode: Diode emulation (discontinuous inductor current) and frequency foldback in light-load condition.
FPWM mode: Forced continuous conduction (continuous inductor current), constant frequency operation in
light-load condition.
In addition to determining the mode of the device, this pin can be used for synchronization to the
frequency and phase of an external signal source. Reference the data sheet for corresponding signal source
requirements.
TP7, TP8 Test points for applying an external signal source to synchronize the regulator to. The synchronization function
is only to be used with the TPSM33625FEVM (TPSM33625FRDNR).
J3 Jumper for configuring the output voltage. Set the voltage by using the "key" annotated in the schematic and
also in the silkscreen, and by placing the jumper on the pins next to the annotated output voltage.
TP9, TP10 Test points for applying an AC signal source (across an injection resistor) often used in evaluating the loop
response in a current mode regulator, such as the TPSM33625 or TPSM33625F.
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DC Supply
-+
E-Load
-+
DVM
-+
DVM
-+
AA
Ammeter Ammeter
Figure 3-1. Test Setup Diagram
Test Setup www.ti.com
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4 Schematic
Customers can choose to implement a PI filter in series with the input of a power regulator, which allows for the
differential noise generated to be attenuated, allowing a noise emission regulation to be met. The filter crossover
frequency is designed for 1-MHz switching frequency, attenuating the switching frequency and the corresponding
harmonics greatly. A damping capacitor is provided (C5), to damp the high-Q PI filter. For more information on
filter damping, see Section 8.
Figure 4-1. Schematic-Compliance Testing Filter
In the buck schematic, the difference between the TPSM33625EVM and TPSM33625FFEVM is the
REFDES=U1 device part number. Use a buck schematic with additional feedback resistors to program
the output voltage and add a placeholder for additional output capacitance to achieve stability or meet a
output transient specification with pin definition RT (adjustable frequency) or Mode/Sync (mode select or
synchronization) differing.
Figure 4-2. Schematic (TPSM33625EVM) – TPSM33625
Figure 4-3. Schematic (TPSM33625FEVM) – TPSM33625F
A disable, frequency select, and output voltage select jumper are provided to aid the evaluation. Additionally, test
points to evaluate product features and stability are provided.
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Figure 4-4. Schematic (TPSM33625EVM) – Configuration Jumpers and Evaluation Test Points
A disable, mode select or synchronization, and output voltage select jumper are provided to aid the evaluation.
Additionally, test points to evaluate product features and stability are provided.
Figure 4-5. Schematic (TPSM33625FEVM) – Configuration Jumpers and Evaluation Test Points
Schematic www.ti.com
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5 TPSM33625EVM and TPSM33625FEVM Evaluation
The data was tested on unmodified EVM, configured for 1-MHz operation and 5 VOUT, and was measured at 12
V and a 2-A load.
Figure 5-1. CISPR32 Conducted Scan
The data was tested on unmodified EVM, configured for 1-MHz operation and 5 VOUT, and was measured at 24
VIN and a 2-A load.
Figure 5-2. CISPR32 Conducted Scan
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12 VIN, 2.2 MHz, 2-A load (continuous)
Figure 5-3. IR Top Case Measurement
12 VIN, 1 MHz, 2-A load (continuous)
Figure 5-4. IR Top Case Measurement
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12 VIN, 500 kHz, 2-A load (continuous)
Figure 5-5. IR Top Case Measurement
24 VIN, 2.2 MHz, 2-A load (continuous)
Figure 5-6. IR Top Case Measurement
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24 VIN, 1 MHz, 2-A load (continuous)
Figure 5-7. IR Top Case Measurement
24 VIN, 500 kHz, 2-A load (continuous)
Figure 5-8. IR Top Case Measurement
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6 Layout
The top silkscreen (that is, J4) differs between the TPSM33625EVM and TPSM3365FEVM, which is the only
difference between the layer plots (no routing).
Figure 6-1. PCB Top 2-D (TPSM33625EVM)
Figure 6-2. PCB Top 2-D (TPSM33625FEVM)
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Figure 6-3. PCB Bottom 2-D
Figure 6-4. Top Layer
Layout www.ti.com
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Reserved for solid ground plane for low-noise and optimized thermal design.
Figure 6-5. Mid Layer 1
Primary routing layer
Figure 6-6. Mid Layer 2
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Reserved for PI filter and non-critical passive component placement (minus input capacitor). An input capacitor
is placed on bottom side of PCB as the input capacitor provides a slightly lower input loop inductance. A single
layer implementation is satisfactory as well.
Figure 6-7. Bottom Layer
Layout www.ti.com
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7 Bill of Materials
Table 7-1. Bill of Materials
Designator Qty Value Description Package
Reference Part Number Manufacturer
C1, C2, C3, C4 4 2.2 μF CAP, CERM, 2.2 μF, 50 V, ±10%,
X7R, AEC-Q200 Grade 1, 0805 0805 CGA4J3X7R1H225K125AB TDK
C5 1 100 μF CAP, AL, 100 μF, 50 V, ±20%, 0.6
Ω, SMD HA0 EMVY500ADA101MHA0G Chemi-Con
C6, C7 2 4.7 μF CAP, CERM, 4.7 μF, 50 V, ±10%,
X7R, 1210 1210 C3225X7R1H475K250AB TDK
C8 1 0.1 μF CAP, CERM, 0.1 μF, 50 V, ±20%,
X5R, 0402 0402 GRM155R61H104ME14D MuRata
C9 1 1 μF CAP, CERM, 1 μF, 16 V, ±10%,
X5R, 0402 0402 EMK105BJ105KVHF Taiyo Yuden
C10, C11 2 22 μF CAP, CERM, 22 μF, 16 V, ±20%,
X7R, AEC-Q200 Grade 1, 1210 1210 CGA6P1X7R1C226M250AC TDK
C14 1 22 pF
CAP, CERM, 22 pF, 50 V, ±5%,
C0G/NP0, AEC-Q200 Grade 1,
0402
0402 CGA2B2NP01H220J050BA TDK
H1, H2, H3, H4 4 Machine Screw, Round, #4-40 ×
1/4, Nylon, Philips panhead Screw NY PMS 440 0025 PH B&F Fastener
Supply
H5, H6, H7, H8 4 Standoff, Hex, 0.5"L #4-40 Nylon Standoff 1902C Keystone
J1, J2 2 TERM BLOCK 2POS 5 mm, TH 10x10x8.1 mm 1729018 Phoenix Contact
J3, J4 2 Header, 100 mil, 5 × 2, Tin, TH Header, 5 × 2,
100 mil, Tin PEC05DAAN Sullins Connector Solutions
J5 1 Header, 100 mil, 2 × 1, Gold, TH Header, 100
mil, 2 × 1, TH HTSW-102-07-G-S Samtec
L1 1 Shielded Power Inductors SMD2 XGL4020-152MEC Coilcraft
R1 1 0 RES, 0, 5%, 0.1 W, AEC-Q200
Grade 0, 0603 0603 CRCW06030000Z0EA Vishay-Dale
R2 1 255 k RES, 255 k, 1%, 0.063 W, AEC-
Q200 Grade 0, 0402 0402 CRCW0402255KFKED Vishay-Dale
R3 1 49.9 k RES, 49.9 k, 1%, 0.063 W, 0402 0402 CRCW040249K9FKED Vishay-Dale
R4 1 47 k RES, 47 k, 5%, 0.063 W, AEC-
Q200 Grade 0, 0402 0402 CRCW040247K0JNED Vishay-Dale
R5, R7 2 8.06 k RES, 8.06 k, 1%, 0.063 W, AEC-
Q200 Grade 0, 0402 0402 CRCW04028K06FKED Vishay-Dale
R6 1 6.98 k RES, 6.98 k, 1%, 0.063 W, AEC-
Q200 Grade 0, 0402 0402 CRCW04026K98FKED Vishay-Dale
R8 1 16.9 k RES, 16.9 k, 1%, 0.063 W, AEC-
Q200 Grade 0, 0402 0402 CRCW040216K9FKED Vishay-Dale
R9 1 69.8 k RES, 69.8 k, 1%, 0.063 W, 0402 0402 CRCW040269K8FKED Vishay-Dale
R10 1 10.0 k RES, 10.0 k, 1%, 0.063 W, AEC-
Q200 Grade 0, 0402 0402 CRCW040210K0FKED Vishay-Dale
R11 1 0 RES, 0, 5%, 0.063 W, AEC-Q200
Grade 0, 0402 0402 CRCW04020000Z0ED Vishay-Dale
R12 1 10.0 RES, 10.0, 1%, 0.063 W, AEC-
Q200 Grade 0, 0402 0402 CRCW040210R0FKED Vishay-Dale
R13 1 20.0 k RES, 20.0 k, 1%, 0.063 W, AEC-
Q200 Grade 0, 0402 0402 CRCW040220K0FKED Vishay-Dale
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Table 7-1. Bill of Materials (continued)
Designator Qty Value Description Package
Reference Part Number Manufacturer
R14 1 33.2 k RES, 33.2 k, 1%, 0.063 W, AEC-
Q200 Grade 0, 0402 0402 CRCW040233K2FKED Vishay-Dale
R15 1 54.9 k RES, 54.9 k, 1%, 0.063 W, AEC-
Q200 Grade 0, 0402 0402 CRCW040254K9FKED Vishay-Dale
SH-J1, SH-J2 2 Shunt, 100 mil, Gold plated, Black Shunt 2 pos.
100 mil 881545-2 TE Connectivity
TP1, TP2, TP3,
TP6 4 Test Point, Miniature, SMT Test Point,
Miniature, SMT 5019 Keystone
TP4, TP7, TP9,
TP10, TP11 5Test Point, Multipurpose, White, TH
White
Multipurpose
Testpoint
5012 Keystone
Electronics
TP5, TP8, TP12 3 Test Point, Multipurpose, Black, TH
Black
Multipurpose
Testpoint
5011 Keystone
Electronics
U1 1 36-V Input, 1-V to 15-V Output,
2.5-A DC-DC Power Module
QFN-
FCMOD11
TPSM33625RDNR
(TPSM33625FEVM:
TPSM33625FRDNR)
Texas Instruments
8 Related Documentation
Texas Instruments, Input Filter Design for Switching Power Supplies application report.
Related Documentation www.ti.com
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9 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (September 2022) to Revision A (March 2023) Page
• Deleted text in Schematic section.......................................................................................................................7
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STANDARD TERMS FOR EVALUATION MODULES
1. Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, and/or
documentation which may be provided together or separately (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordance
with the terms set forth herein. User's acceptance of the EVM is expressly subject to the following terms.
1.1 EVMs are intended solely for product or software developers for use in a research and development setting to facilitate feasibility
evaluation, experimentation, or scientific analysis of TI semiconductors products. EVMs have no direct function and are not
finished products. EVMs shall not be directly or indirectly assembled as a part or subassembly in any finished product. For
clarification, any software or software tools provided with the EVM (“Software”) shall not be subject to the terms and conditions
set forth herein but rather shall be subject to the applicable terms that accompany such Software
1.2 EVMs are not intended for consumer or household use. EVMs may not be sold, sublicensed, leased, rented, loaned, assigned,
or otherwise distributed for commercial purposes by Users, in whole or in part, or used in any finished product or production
system.
2Limited Warranty and Related Remedies/Disclaimers:
2.1 These terms do not apply to Software. The warranty, if any, for Software is covered in the applicable Software License
Agreement.
2.2 TI warrants that the TI EVM will conform to TI's published specifications for ninety (90) days after the date TI delivers such EVM
to User. Notwithstanding the foregoing, TI shall not be liable for a nonconforming EVM if (a) the nonconformity was caused by
neglect, misuse or mistreatment by an entity other than TI, including improper installation or testing, or for any EVMs that have
been altered or modified in any way by an entity other than TI, (b) the nonconformity resulted from User's design, specifications
or instructions for such EVMs or improper system design, or (c) User has not paid on time. Testing and other quality control
techniques are used to the extent TI deems necessary. TI does not test all parameters of each EVM.
User's claims against TI under this Section 2 are void if User fails to notify TI of any apparent defects in the EVMs within ten (10)
business days after delivery, or of any hidden defects with ten (10) business days after the defect has been detected.
2.3 TI's sole liability shall be at its option to repair or replace EVMs that fail to conform to the warranty set forth above, or credit
User's account for such EVM. TI's liability under this warranty shall be limited to EVMs that are returned during the warranty
period to the address designated by TI and that are determined by TI not to conform to such warranty. If TI elects to repair or
replace such EVM, TI shall have a reasonable time to repair such EVM or provide replacements. Repaired EVMs shall be
warranted for the remainder of the original warranty period. Replaced EVMs shall be warranted for a new full ninety (90) day
warranty period.
WARNING
Evaluation Kits are intended solely for use by technically qualified,
professional electronics experts who are familiar with the dangers
and application risks associated with handling electrical mechanical
components, systems, and subsystems.
User shall operate the Evaluation Kit within TI’s recommended
guidelines and any applicable legal or environmental requirements
as well as reasonable and customary safeguards. Failure to set up
and/or operate the Evaluation Kit within TI’s recommended
guidelines may result in personal injury or death or property
damage. Proper set up entails following TI’s instructions for
electrical ratings of interface circuits such as input, output and
electrical loads.
NOTE:
EXPOSURE TO ELECTROSTATIC DISCHARGE (ESD) MAY CAUSE DEGREDATION OR FAILURE OF THE EVALUATION
KIT; TI RECOMMENDS STORAGE OF THE EVALUATION KIT IN A PROTECTIVE ESD BAG.