Texas Instruments DP83561EVM User manual

User’s Guide
DP83561EVM User’s Guide
Nikhil Menon
ABSTRACT
This User’s Guide discusses how to properly operate and configure the DP83561EVM. For best layout practices,
schematic files, and Bill of Materials, see the associated sections and support documents.
DP83561EVM consists of a main PCB and two breakout boards: DP83561-SP Ethernet board, MAC interface
breakout board, and MAC interface back-to-back connector.
Figure 1-1. DP83561EVM Main PCB and Two Breakout Boards
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Table of Contents
1 Definitions............................................................................................................................................................................... 4
2 Introduction.............................................................................................................................................................................5
2.1 DP83561EVM Key Features.............................................................................................................................................. 5
2.2 Block Diagram....................................................................................................................................................................8
2.3 Operation – Quick Setup....................................................................................................................................................9
3 Board Setup Details..............................................................................................................................................................11
3.1 Power Supply Selection....................................................................................................................................................11
3.2 Configuration Options...................................................................................................................................................... 12
3.3 Clock Selection................................................................................................................................................................ 13
3.4 MAC Interface Breakout Connectors............................................................................................................................... 14
3.5 LED Indication..................................................................................................................................................................15
3.6 Serial Management Interface........................................................................................................................................... 15
3.7 Cable Assembly............................................................................................................................................................... 15
4 BER Testing...........................................................................................................................................................................16
5 Compliance Testing.............................................................................................................................................................. 18
6 SEFI Support Monitoring......................................................................................................................................................19
7 Software.................................................................................................................................................................................21
7.1 MSP430 Driver.................................................................................................................................................................21
7.2 USB-2-MDIO Software.....................................................................................................................................................21
8 Schematics............................................................................................................................................................................22
8.1 Main Power Schematic ................................................................................................................................................... 23
8.2 Main Block Schematic......................................................................................................................................................24
8.3 Bootstrap Settings Schematic.......................................................................................................................................... 25
8.4 Analog Front End and MAC Interface Schematic............................................................................................................ 26
8.5 USB Hub Schematic........................................................................................................................................................ 27
8.6 COMs 1 Schematic.......................................................................................................................................................... 28
8.7 COMs 2 Schematic.......................................................................................................................................................... 29
8.8 Breakout Boards Schematic.............................................................................................................................................30
8.9 Hardware Schematic........................................................................................................................................................31
9 Layout.................................................................................................................................................................................... 32
9.1 Top Overlay...................................................................................................................................................................... 32
9.2 Top Layer Mask................................................................................................................................................................33
9.3 Top Layer......................................................................................................................................................................... 34
9.4 Ground Layer 1................................................................................................................................................................ 35
9.5 Signal Layer 1.................................................................................................................................................................. 36
9.6 Signal Layer 2.................................................................................................................................................................. 37
9.7 Ground Layer 2................................................................................................................................................................ 38
9.8 Bottom Layer....................................................................................................................................................................39
9.9 Bottom Layer Mask.......................................................................................................................................................... 40
9.10 Bottom Overlay.............................................................................................................................................................. 41
9.11 Board Assembly............................................................................................................................................................. 42
10 Bill of Materials................................................................................................................................................................... 46
11 REACH Compliance............................................................................................................................................................54
12 Revision History................................................................................................................................................................. 54
List of Figures
Figure 1-1. DP83561EVM Main PCB and Two Breakout Boards................................................................................................ 1
Figure 2-1. DP83561EVM – Top Side..........................................................................................................................................6
Figure 2-2. DP83561EVM – Bottom Side.................................................................................................................................... 7
Figure 2-3. DP83561EVM Block Diagram................................................................................................................................... 8
Figure 2-4. Wide-Vin 5V-36V Supply Connection........................................................................................................................9
Figure 2-5. DP83561EVM External Supply Connection and Jumpers........................................................................................ 9
Figure 2-6. DP83561EVM Mirror Mode Strap............................................................................................................................10
Figure 3-1. DP83561EVM VDDIO Selection Straps.................................................................................................................. 11
Figure 3-2. DP83561EVM USB Power Supply.......................................................................................................................... 12
Figure 3-3. DP83561EVM RGMII Back-to-Back Connection Diagram...................................................................................... 14
Figure 3-4. MAC Interface Breakout Board Connection............................................................................................................ 15
Figure 4-1. MAC Interface Breakout Board External Loopback Connection Diagram...............................................................16
Figure 4-2. DP83561EVM BER Testing MII Connection Diagram............................................................................................. 17
Figure 5-1. DP83561EVM Compliance Test Fixture Connection...............................................................................................18
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Figure 6-1. DP83561EVM SEFI Interrupt Pins.......................................................................................................................... 19
Figure 8-1. DP83561EVM Main Power......................................................................................................................................23
Figure 8-2. DP83561EVM Main Block....................................................................................................................................... 24
Figure 8-3. DP83561EVM Bootstrap Settings........................................................................................................................... 25
Figure 8-4. DP83561EVM AFE and MAC Interface...................................................................................................................26
Figure 8-5. DP83561EVM USB Hub..........................................................................................................................................27
Figure 8-6. DP83561EVM COMs 1........................................................................................................................................... 28
Figure 8-7. DP83561EVM COMs 2........................................................................................................................................... 29
Figure 8-8. DP83561EVM Breakout Connectors.......................................................................................................................30
Figure 8-9. DP83561EVM Hardware......................................................................................................................................... 31
Figure 9-1. Top Overlay............................................................................................................................................................. 32
Figure 9-2. Top Layer Mask....................................................................................................................................................... 33
Figure 9-3. Top Layer.................................................................................................................................................................34
Figure 9-4. Ground Layer 1....................................................................................................................................................... 35
Figure 9-5. Signal Layer 1......................................................................................................................................................... 36
Figure 9-6. Signal Layer 2......................................................................................................................................................... 37
Figure 9-7. Ground Layer 2....................................................................................................................................................... 38
Figure 9-8. Bottom Layer........................................................................................................................................................... 39
Figure 9-9. Bottom Layer Mask................................................................................................................................................. 40
Figure 9-10. Bottom Overlay......................................................................................................................................................41
Figure 9-11. Top Assembly ....................................................................................................................................................... 42
Figure 9-12. Bottom Assembly.................................................................................................................................................. 43
Figure 9-13. Drill Drawing.......................................................................................................................................................... 44
Figure 9-14. Board Dimensions................................................................................................................................................. 45
List of Tables
Table 1-1. Terminology.................................................................................................................................................................4
Table 3-1. VDDIO Selection Strap Settings................................................................................................................................11
Table 3-2. DP83561-SP 4-Level Bootstrap Resistor Designation and Suggested Bootstrap Resistor Values.......................... 13
Table 3-3. DP83561-SP 2-Level Bootstrap Selection and Jumper Designation........................................................................ 13
Table 3-4. DP83561-SP LED Bootstrap Selection and Jumper Designation.............................................................................13
Table 10-1. Bill of Materials........................................................................................................................................................46
Table 11-1. REACH Compliance SVHC's.................................................................................................................................. 54
Trademarks
All trademarks are the property of their respective owners.
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1 Definitions
Table 1-1. Terminology
ACRONYM DEFINITION
PHY Physical Layer Transceiver
MAC Media Access Controller
SMI Serial Management Interface
MDIO Management Data I/O
MDC Management Data Clock
RGMII Reduced Gigabit Media Independent Interface
MII Media Independent Interface
SFD Start-of-Frame Detection
VDDA Analog Core Supply Rail
VDDIO Digital Supply Rail
PD Pulldown
PU Pullup
MC Microcontroller
AFE Analog Front End
SEFI Single Event Functional Interrupt
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2 Introduction
The DP83561-SP is a radiation hardened, high reliability gigabit Ethernet PHY designed for hostile environments
like those found in space, avionics, or downhill drilling. The DP83561-SP is a low power, fully featured Physical
Layer transceiver with integrated PMD sub-layers to support 10BASE-Te, 100BASE-TX and 1000BASE-T
Ethernet protocols.
The DP83561EVM is a tool used to highlight the features of the DP83561-SP Ethernet PHY. Breakout
connectors are included to allow MAC access and back-to-back configuration support. The EVM also provides
on-board tools to configure PHY registers using a USB-MDIO graphical user interface tool. The EVM can be
powered by a single Wide-Vin 5V-36V power supply or through a microUSB cable.
Note
The DP83561EVM uses DP83561-SP Engineering Module (EM) parts. EM parts do not ensure
radiation performance. They are suitable for prototyping but not suitable for production.
2.1 DP83561EVM Key Features
• Space Grade DP83561-SP is IEEE802.3 10BASE-Te, 100BASE-TX, and 1000BASE-T compliant
• RGMII/MII MAC interfaces
• BER testing via back-to-back configuration or loopback modes
• Compliance testing support
• SEFI monitoring
– PCS State machine monitor
– ECC monitor
– Supply current monitor
– Temperature monitor
– Auto-recovery option
• Onboard MSP support to configure PHY over MDIO/MDC
– USB-2-MDIO support
• Status LEDs
– Link
– Power supplies
– SMI command
• Variable I/O Voltage Range: 1.8-V, 2.5-V, and 3.3-V
• Bootstraps for hardware configuration
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Figure 2-1. DP83561EVM – Top Side
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Figure 2-2. DP83561EVM – Bottom Side
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2.2 Block Diagram
Figure 2-3. DP83561EVM Block Diagram
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2.3 Operation – Quick Setup
The DP83561EVM can operate from a single Wide-Vin 5V-36V DC supply connected to the power jack J16
or the header J18. The DP83561-SP is configured for Dual Supply Mode by default. Due to RJ45 orientation
and routing, Mirror Mode is enabled by default. Refer to Section 3.2.2 for additional information on Mirror Mode
configuration. The DP83561EVM can be quickly configured as follows:
• Ensure shunt removed at J37 header (set PHY for dual supply mode)
• Place shunt at J15 connecting pins 2 and 3.
• Ensure shunt removed at J23 to disconnect VDDA1P8 LDO (not needed in dual supply mode)
• Place shunt at J20 to connect VDDA2P5 LDO
• Place shunt at P2 in the 3.3 V position to connect VDDIO LDO
• Ensure shunts removed on J35 and J36.
• Place shunt at J24 to connect VDD1P1 LDO
• Ensure shunt removed at J21 header
• Place shunt at J31 to enable Mirror Mode (if necessary, refer to Section 3.2.2).
•Wide Vin: Connect 5V - 36V to pin 1 of J18 and ground to pin 2 of J18
Figure 2-4. Wide-Vin 5V-36V Supply Connection
Figure 2-5. DP83561EVM External Supply Connection and Jumpers
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Figure 2-6. DP83561EVM Mirror Mode Strap
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3 Board Setup Details
3.1 Power Supply Selection
Dual Supply Mode vs. Triple Supply Mode
The DP83561-SP can be powered by as few as two supplies in dual supply mode, or three supplies in triple
supply mode. In dual supply mode, the VDDA1P8 pin must be left floating. By default the DP83561EVM is
configured for dual supply mode. To configure the DP83561-SP in triple supply mode:
• Place shunt on J37 to enable the SUPPLYMODE_SEL strap as described in Section 3.2
The following sections describe powering the DP83561EVM using the on-board LDOs, external supplies, or USB
power. Please note that powering the VDDA1P8 pin is only required in triple supply Mode.
3.1.1 VDDIO Selection
In addition to supplying the correct voltage, the DP83561-SP uses straps to select VDDIO levels. If 2.5 V is used
as the VDDIO level, the VDDIOSEL_1 strap must be pulled high, which can be done by placing a shunt on J35.
If 1.8 V is used asthe VDDIO level, both the VDDIOSEL_1 and VDDIOSEL_0 straps must be pulled high, by
placing shunts on J35 and J36. For a VDDIO level of 3.3 V, these pins can be left floating.
Table 3-1. VDDIO Selection Strap Settings
Strap
VDDIO Level
VDDIOSEL_1 VDDIOSEL_0
0 0 3.3 V
0 1 Reserved
1 0 2.5 V
1 1 1.8 V
Figure 3-1. DP83561EVM VDDIO Selection Straps
3.1.2 On-board Power Supply Operation
• DP83561EVM Onboard Power Using Headers
– Place shunt at J23 to connect VDDA1P8 LDO (triple supply mode only)
– Place shunt at J20 to connect VDDA2P5 LDO
– Place shunt at P2 1.8-V, 2.5-V, or 3.3-V to VDDIO on J17 and place corresponding strap selection shunts
– Place shunt at J24 to connect VDD1P1 LDO
– Remove shunt at J21 header
–Wide Vin: Connect 5V - 36V to pin 1 of J18 and ground to pin 2 of J18
• DP83561EVM Onboard Power Using Power Jack
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– Place shunt at J23 to connect VDDA1P8 LDO (triple supply mode only)
– Place shunt at J20 to connect VDDA2P5 LDO
– Place shunt at P2 1.8-V, 2.5-V, or 3.3-V to VDDIO on J17 and place corresponding strap selection shunts
– Place shunt at J24 to connect VDD1P1 LDO
– Remove shunt at J21 header
–Wide Vin: Connect 5V - 36V to power jack connector J16
3.1.3 External Power Supply Operation
• DP83561EVM External Power
– Remove shunt at J23 to disconnect VDDA1P8 LDO
– Remove shunt at J20 to disconnect VDDA2P5 LDO
– Remove shunt at P2 to disconnect VDDIO LDO
– Remove shunt at J24 to disconnect VDD1P1 LDO
– Remove shunt at J21 header
– Connect 1.1V to VDD1P1 on J17
– Connect 1.8V to VDDA1P8 on J15 (triple supply mode only)
– Connect 2.5V to VDDA2P5 on J17
– Connect 1.8-V, 2.5-V, or 3.3-V to VDDIO on J17 and place corresponding strap selection shunts
– Connect ground to GND on J17
3.1.4 USB Power Supply Option
DP838561EVM block powered by USB.
• Place shunt at J23 to connect VDDA1P8 LDO (triple supply mode only)
• Place shunt at J20 to connect VDDA2P5 LDO
• Place shunt at P2 in desired VDDIO level to connect VDDIO LDO and place corresponding strap selection
shunts
• Place shunt at J24 to connect VDD1P1 LDO
– Place shunt at J21 header
•Connect micro-usb to J42
Note
Only populate J21 when powering over USB.
Figure 3-2. DP83561EVM USB Power Supply
3.2 Configuration Options
3.2.1 Bootstrap Options
Some DP83561-SP configurations can be done through bootstrap options. Options can be selected with jumpers
or resistor population. Refer to the device data sheet for additional information on bootstrap options. Refer to the
schematic and layout sections of this User’s Guide for resistor and jumper locations. By default, PHY address
must be set to 00 and all straps must be mode 0 except for MIRROR_EN.
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Table 3-2. DP83561-SP 4-Level Bootstrap Resistor Designation and Suggested Bootstrap Resistor Values
PIN NAME PIN
NUMBER STRAP NAME STRAP MODE
PU RESISTOR
(KΩ)
PU RESISTOR
DESIGNATION
PD RESISTOR
(KΩ)
PD RESISTOR
DESIGNATION
RX_D0 44 PHY_ADD[1:0]
1 OPEN
R152
OPEN
R154
2 10 2.49
3 5.76 2.49
4 2.49 OPEN
RX_D1 45 PHY_ADD[3:2]
1 OPEN
R155
OPEN
R158
2 10 2.49
3 5.76 2.49
4 2.49 OPEN
Table 3-3. DP83561-SP 2-Level Bootstrap Selection and Jumper Designation
PIN NAME PIN NUMBER STRAP NAME STRAP
MODE
JUMPER
PLACEMENT
JUMPER
DESIGNATION
VDDIOSEL_0 22 VDDIOSEL_0 0 OPEN J36
1 CLOSED
VDDIOSEL_1 21 VDDIOSEL_1 0 OPEN J35
1 CLOSED
SUPPLYMODE_SEL 23 SUPPLYMODE_SEL 0 OPEN J37
1 CLOSED
CRS/GPIO_3 33 RGMII/MII_SEL 0 OPEN J41
1 CLOSED
AUTO_RECOVER 34 AUTO_RECOVER 0 OPEN J39
1 CLOSED
RX_CTRL 48 MIRROR_EN 0 OPEN J31
1 CLOSED
SMI_DISABLE 50 SMI_DISABLE 0 OPEN J40
1 CLOSED
POWERGOOD 59 POWERGOOD 0 OPEN N/A
1 CLOSED
Table 3-4. DP83561-SP LED Bootstrap Selection and Jumper Designation
PIN NAME PIN NUMBER STRAP NAME STRAP MODE JUMPER PLACEMENT JUMPER DESIGNATION
LED_0 63 ANED_DIS 0 OPEN/PD J28
1 PU
LED_1 62 ANEGSEL_0 0 OPEN/PD J33
1 PU
LED_2 45 ANEGSEL_1 0 OPEN/PD J38
1 PU
3.2.2 Mirror Mode
The DP83561EVM enables Mirror Mode by default. As can be observed in Section 8.4, due to the RJ45
orientation and routing on the board, the differential transmit and receive pairs orientation and polarity have been
flipped on J27. Mirror mode must be enabled to correct this change, unless the link partner uses a similar routing
and layout strategy, matching the differential pairs correctly.
3.3 Clock Selection
3.3.1 On-Board 25 MHz Crystal
By default, the DP83561 is configured to use the on-board 25 MHz crystal. To verify the on-board 25 MHz crystal
is properly connected, confirm the following:
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• Remove R84
• Populate R82, R77
3.3.2 External Clock
To remove the on-board 25 MHz crystal and supply an external 25 MHz clock:
• Remove R82, R77
• Populate R84
• Provide External Clock to SMA at J11
3.4 MAC Interface Breakout Connectors
The DP83561EVM comes with two MAC interface breakout boards, and RGMII back-to-back connector board,
and a MAC interface breakout board. When configuring the DP83561-SP for MII mode, the MAC interface
breakout board must be used to access the MII pins.
RGMII Back-to-Back Configuration
• Connect J4 of the main DP83561EVM board to J22 of the RGMII back-to-back connector
• Connect J19 of the RGMII back-to-back connector to a second DP83561EVM or other RGMII MAC
Note
RGMII back-to-back connector is reversible, RGMII back-to-back breakout connector can be conneted
to a DP83561EVM on either J19 or J22.
DP83561EVM
B
DP83561EVM
A
RGMII back-
to-back
Breakout
Link Partner
A
Link Partner
B
CableCable
Figure 3-3. DP83561EVM RGMII Back-to-Back Connection Diagram
MAC Interface Breakout Board Configuration
The MAC Interface Breakout Board can be used to directly access the MII pins of the DP83561-SP. This board
can be used for configurations such as configuring the DP83561EVM for RGMII external loopback tests as
described by RGMII BER Testing - External Loopback Configuration, or connecting an MII MAC.
• Connect J4 of the main DP83561EVM board to J1 of the MAC interface breakout board
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• MAC interface pins can be accessed via J2 of the MAC interface breakout board connector.
Figure 3-4. MAC Interface Breakout Board Connection
3.5 LED Indication
• Look for D5, D6, D7, and D8 to illuminate when power is successfully supplied to each power rail.
• LED0, LED1, LED2 can be configured through LEDS_CFG1 Register 0x18
– By default, LED0 indicates valid link established.
– By default, LED1 indicates 1000Base-T link established
– By default, LED2 indicates RX/TX activity
3.6 Serial Management Interface
The DP83561EVM supports SMI (MDIO/MDC) through J43 and includes an on-board MSP for USB-2-MDIO
control.
Notes:
• DP83561-SP default PHY_ID is 00
• PHY IDs can be changed through bootstrap options found in the datasheet
3.7 Cable Assembly
• Plug a CAT5, CAT5E, or CAT6 cable into the RJ45 connector J16
• In applications where Mirror Mode needs to be enabled, place shunt on J31
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4 BER Testing
The DP83561EVM supports BER testing through RGMII back-to-back configuration and/or internal loopback
modes.
RGMII BER Testing - Back-to-Back Configuration
The DP83561EVM supports RGMII BER testing through back-to-back configuration as described by RGMII
Back-to-Back Configuration. BER testing can be conducted using two DP83561EVMs and two link partners by
checking the packets sent and received by the two link partners.
Referring to Figure 3-3, should a second link partner, Link Partner B, be unavailable, DP83561EVM B can be
programmed into Analog Loopback for the BER test. In this case, Link Partner A will send data across the cable
to DP83561EVM A, to be sent across the RGMII interface to DP83561EVM B, looped back to DP83561EVM A,
and received by Link Partner A. Please note, that in Analog Loopback, the MDI output pairs must have a 100
ohm differential termination. The RGMII Transmit Clock Delay must be set such that the RGMII transmit clock is
aligned with respect to transmit data for both boards. This can be done with the following register write:
• Write Register 0x32 = 0xD2
For additional information on configuring loopback modes, please refer to the device data sheet.
RGMII BER Testing - External Loopback Configuration
The DP83561EVM support RGMII BER testing through an external loopback configuration using the MAC
Interface Breakout Board. The MAC Interface Breakout Board may be connected to the main DP83561EVM
board as described in MAC Interface Breakout Board Configuration. To configure the MAC Interface Breakout
Board for external loopback, jumpers must be placed to connect the transmit pins to the corresponding receive
pins. Refer to Figure 4-1 for a connection diagram. The RGMII Transmit Clock Delay must be set such that the
RGMII transmit clock is aligned with respect to transmit data. This can be done with the following register write:
• Write Register 0x32 = 0xD2
MAC Interface
Breakout Board
TXD3
TXD2
TXD1
TXD0
TXCTRL
GTXCLK
RXD3
RXD2
RXD1
RXD0
RXCTRL
RXCLK
RXER
MDIO
MDC
RESET
CRS
COL
Figure 4-1. MAC Interface Breakout Board External Loopback Connection Diagram
MII BER Testing
In MII mode, the MAC Interface Breakout Board may be used as described in MAC Interface Breakout Board
Configuration to support MII BER testing. Referring to Figure 4-2, the link partner, which can be another
DP83561EVM, must be configured for Reverse Loopback, and the MII MAC must be configured to generate and
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receive packets, and check for errors. For additional information on configuring loopback modes, please refer to
the device data sheet.
MII MACDP83561EVM
MAC
Interface
Breakout
Link Partner Cable
Figure 4-2. DP83561EVM BER Testing MII Connection Diagram
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5 Compliance Testing
The DP83561EVM supports IEEE 802.3 Ethernet Compliance testing, providing an option to connect a test
fixture via an RJ45 connector on J16. Please refer to the device datasheet for details on setting the different
Ethernet Compliance Test Modes.
Figure 5-1. DP83561EVM Compliance Test Fixture Connection
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6 SEFI Support Monitoring
The DP83561-SP offers a SEFI monitoring suite, monitoring the IEEE PCS state machine, ECC configuration
register, supply current, PLL lock, and on-chip temperature. When Auto-Recovery is enabled, the device will
automatically reset the PHY when a SEFI is detected. Please refer to the device datasheet for detailed
descriptions of each function. This section describes how to observe each interrupt using the DP83561EVM.
The DP83561EVM has hooks to observe the following SEFI events:
• IEEE PCS State Machine Monitor
– If any invalid state changes are made, the DP83561 will indicate a SEFI has occurred and raise the
INT_STTMCHNE_N signal.
– The INT_STTMCHNE_N signal can be observed on the INT_STTMCHNE_N pin of J8.
• ECC Configuration Register Monitor
– If any change in the configuration registers are detected or corrected by the ECC, an interrupt on the
INT_CHECKSUM_N signal will be raised for indication to the higher level system.
– The INT_CHECKSUM_N signal can be observed on the INT_CHECKSUM_N pin of J8.
• Supply Current Monitor
– When supply current changes exceed the expected normal operating conditions, the INT_SUP_CUR_N
signal will be asserted.
– The INT_SUP_CUR_N signal can be observed on the INT_SUP_CUR_N pin of J8.
• Temperature Monitor
– The DP83561-SP has an on chip temperture monitor. The value measured by the sensor can be read
using the following steps:
• Write value 0xCD24 to register 0x01E8
• Read measured value off of register 0x01EA
Figure 6-1. DP83561EVM SEFI Interrupt Pins
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Note
To use the pins INT_SUP_CUR_N, INT_ECC_N, and INT_STTMCHNE_N as an interrupt, they must
be pulled up to VDDIO through use of an external 2.2k pull-up resistor. The resistors R42, R43,
and R44 respectively may be replaced with a 2.2k resistor and connected to VDDIO. VDDIO can be
accessed via pins 2, 4, and 6 of header P2.
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