Texas Instruments TPS5124EVM-001 User manual

User’s Guide
1
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User’s Guide

2
EVM IMPORTANT NOTICE
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:
This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION
PURPOSES ONLY and is not considered by TI to be fit for commercial use. As such, the goods being provided
may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective
considerations, including product safety measures typically found in the end product incorporating the goods.
As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic
compatibility and therefore may not meet the technical requirements of the directive.
Should this evaluation kit not meet the specifications indicated in the EVM User’s Guide, the kit may be returned
within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE
WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED,
IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY
PARTICULAR PURPOSE.
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user
indemnifies TI from all claims arising from the handling or use of the goods. Please be aware that the products
received may not be regulatory compliant or agency certified (FCC, UL, CE, etc.). Due to the open construction
of the product, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic
discharge.
EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE
TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not
exclusive.
TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein.
Please read the EVM User’s Guide and, specifically, the EVM Warnings and Restrictions notice in the EVM
User’s Guide prior to handling the product. This notice contains important safety information about temperatures
and voltages. For further safety concerns, please contact the TI application engineer.
Persons handling the product must have electronics training and observe good laboratory practice standards.
No license is granted under any patent right or other intellectual property right of TI covering or relating to any
machine, process, or combination in which such TI products or services might be or are used.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2003, Texas Instruments Incorporated

3
DYNAMIC WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the input voltage range of 0 Vdc to100 Vdc.
Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM.
If there are questions concerning the input range, please contact a TI field representative prior to connecting
the input power.
Applying loads outside of the specified output range may result in unintended operation and/or possible
permanent damage to the EVM. Please consult the EVM User’s Guide prior to connecting any load to the EVM
output. If there is uncertainty as to the load specification, please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than 50°C. The EVM
is designed to operate properly with certain components above 50°C as long as the input and output ranges are
maintained. These components include but are not limited to linear regulators, switching transistors, pass
transistors, and current sense resistors. These types of devices can be identified using the EVM schematic
located in the EVM User’s Guide. When placing measurement probes near these devices during operation,
please be aware that these devices may be very warm to the touch.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2004, Texas Instruments Incorporated

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4High-Performance Dual Synchronous Buck Conversion Using the TPS5124
High-Performance Dual Synchronous Buck Conversion
Using the TPS5124
Systems Powe
r
Contents
1 Introduction 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Features 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Schematic 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Component Selection 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Test Results/Performance Data 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 Layout Considerations 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7 PCB Layout 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8 List of Materials 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1 Introduction
The TPS5124 is a dual independent synchronous buck controller. Both controllers internal to the
TPS5124 operate at 180°phase shift and the input ripple is partially cancelled and therefore the
required input capacitance is reduced. Other features include separate soft-start circuit and
standby control. See the TPS5124 data sheet (SLUS571) for detail.

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High-Performance Dual Synchronous Buck Conversion Using the TPS5124
2 Features
This EVM is designed to operate from 12-V bus voltage. It generates two outputs, 3.3 V at 15 A
and 1.5 V at 10 A.
Table 1. TPS5124EVM−001 Performance Summary
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Input voltage range 6.5 12.0 15.0 V
Operating frequency 300 kHz
Input ripple voltage (RMS) VIN = 12 V, IOUT1 = 15 A, IOUT2 = 10 A 92 mV
Channel 1
Output current range 6.5 V ≤VIN ≤15 V 0 15 16 A
Line regulation 6.5 V ≤VIN ≤15 V IOUT = 15 A ±0.1%
Load regulation 1 A ≤IOUT ≤15 A VIN = 12 V ±0.3%
Load transient response voltage
IOUT rising from 0 A to 8.5 A −160
mVPK
Load transient response voltage
change IOUT falling from 8.5 A to 0 A 200 mVPK
Load transient response recovery
IOUT rising from 0 A to 8.5 A 80
s
Load transient response recovery
time IOUT falling from 8.5 A to 0 A 120 µs
Loop bandwidth IOUT = 15 A 30 kHz
Phase margin IOUT = 15 A 55 °
Output ripple voltage IOUT = 15 A 33 66 mVPP
Output rise time VIN = 12 V, VOUT = 3.3 V, IOUT = 15 A 2.85 ms
Full load efficiency VIN = 12 V, VOUT = 3.3 V, IOUT = 15 A 90.6%
Channel 2
Output current range 6.5 V ≤VIN ≤15 V 0 10 12 A
Line regulation 6.5 V ≤VIN ≤15 V ±0.1%
Load regulation 1 A ≤IOUT ≤10 A VIN = 12 V ±0.3%
Load transient response voltage
IOUT rising from 0 A to 7.5 A −120
mVPK
Load transient response voltage
change IOUT falling from 7.5 A to 0 A 220 mVPK
Load transient response recovery
IOUT rising from 0 A to 7.5 A 40
s
Load transient response recovery
time IOUT falling from 7.5 A to 0 A 80 µs
Loop bandwidth IOUT = 10 A 23 kHz
Phase margin IOUT = 10 A 55 °
Output ripple voltage IOUT = 10 A 15 30 mVPP
Output rise time VIN = 12 V, VOUT = 1.5 V, IOUT = 10 A 2.12 ms
Full load efficiency VIN = 12 V, VOUT = 1.53 V, IOUT = 10 A 85.5%
3 Schematic
The schematic of TPS5124EVM is shown in Figure 1.

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6High-Performance Dual Synchronous Buck Conversion Using the TPS5124
+ +
Figure 1. HPA053 TPS5124 Controller Schematic

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High-Performance Dual Synchronous Buck Conversion Using the TPS5124
4 Design Procedure
4.1 Frequency Setting
Many factors influence frequency selection. Higher switching frequency leads to smaller output
inductor and capacitor, reducing the size of the converter. However, higher switching frequencies
increase switching losses, and lower the converter’s efficiency. A frequency of 300 kHz is
chosen for this design for reasonable efficiency and size.
Capacitor C16, which is connected from CT (pin 5) to ground, programs the oscillator frequency.
A C16 value of 47 pF yields a switching frequency of 300 kHz at 25°C.
4.2 Inductance Value
The inductance value can be calculated using equation (1).
L+VOUT
f(min) IRIPPLE ǒ1*VOUT
VIN(max)Ǔ
where
•IRIPPLE is the ripple current flowing through the inductor
The ripple current affects the output voltage ripple and core losses. Based on 20% ripple current
and 300 kHz, the inductance value is calculated as 2.2 µH. An off-the-shelf 2.2-µH inductor from
Vishay is chosen. The part number is IHLP−5050CE−01−2R2M01. The DCR is 7 mΩand the
DCR related conduction loss is 1.6 W, which is about 3.3% of output power.
The same procedure is followed to choose the inductor for Channel 2. The same inductor is
chosen.
4.3 Output Capacitors
The required output capacitance and its ESR can be calculated using equations (2) and (3).
COUT(min) +IRIPPLE
8 f VRIPPLE
ESROUT +VRIPPLE
IRIPPLE
With 1% output voltage ripple, the required minimum output capacitance is 54 µF and its ESR
should be less than 7.7 mΩ.
From the load transient point of view, the capacitance needed for 6% overshoot can be
calculated using equation (4).
COUT +ǒIOUT(max)Ǔ2 L
ǒVOUT2Ǔ2*ǒVOUT1Ǔ2
(1)
(2)
(3)
(4)

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8High-Performance Dual Synchronous Buck Conversion Using the TPS5124
where
•VOUT2 is the allowed overshoot voltage
•VOUT1 is the nominal operating voltage
For 6% overshoot, the required capacitance is about 370 µF. Four 100-µF, 6.3-V ceramic
capacitors are used. Their ESR value is 2.0 mΩeach.
4.4 Input Capacitors
Due to the out of phase operation, the input current ripple is partially cancelled. The total RMS
current in the input capacitor is calculated as follows. This assumes the total input current goes
into the input capacitor to the power ground and ignores the ripple current in the inductor.
UDG−04010
0 V
ǒIOUT1 *IAVGǓ
ǒIOUT2 *IAVGǓ
IAVG
0T
T
2T
2)D2 T
D1 T
IAVG
Figure 2. Case One (D1 < 0.5, D2 < 0.5)
UDG−04010
ǒIOUT1 *IAVGǓ
ǒIOUT1 )IOUT2 *IAVGǓ
0 T
T
2T
2)D2 T
D1 T
IAVG
0 V
ǒIOUT2 *IAVGǓ
Figure 3. Case Two (D2 < 0.5 < D1 )

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High-Performance Dual Synchronous Buck Conversion Using the TPS5124
4.4.1 Case One: D1, D2 < 0.5.
The ripple current through the input capacitor is shown in Figure 2 and can be calculated using
equation (6).
IincapRMS :+
1
T ȧ
ȱ
ȲŕD1@T
0ǒIOUT1 *IAVGǓ2dt )ŕT
2
D1@TǒIAVGǓ2dt )ŕT
2)D2@T
T
2
ǒIOUT2 *IAVGǓ2dt )ŕT
T
2)D2@TǒIAVGǓ2dtȧ
ȳ
ȴ
Ǹ
IincapRMS :+D1 ǒIOUT1Ǔ2)D2 ǒIOUT2Ǔ2*ǒIAVGǓ2
Ǹ
where:
IAVG is the average input current.
IAVG +IOUT1 D1 )IOUT2 D2
4.4.2 Case Two: D2 < 0.5 < D1.
The ripple current through the input capacitor is shown in Figure 3 and can be calculated using
equation (8).
IincapRMS :+
1
T ƪŕT
2
0ǒIOUT1 *IAVGǓ2dt )ŕD1@T
T
2
ǒIOUT1 )IOUT2 *IAVGǓ2dt )ŕT
2)D2@T
D1@TǒIOUT2 *IAVGǓ2dt )ŕT
T
2)D2@TǒIAVGǓ2dtƫ
Ǹ
IincapRMS :+D1 ǒIOUT1Ǔ2)D2 ǒIOUT2Ǔ2)(2 D1*1) IOUT1 IOUT2 *ǒIAVGǓ2
Ǹ
This EVM meets “Case One” criteria. The maximum input ripple current is 6.7 A at VIN =12 V.
Two 150-µF, 20-V special polymer capacitors from Panasonic (part number is EEFWA1D151P)
are used. It can handle 3.7 A of ripple current each. The ESR value of each capacitor is 26 mΩ.
So the input ripple voltage is calculated using equation (10) and is approximately 88 mVRMS
IRIPPLE +IincapRMS ESR
(5)
(6)
(7)
(8)
(9)
(10)

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10 High-Performance Dual Synchronous Buck Conversion Using the TPS5124
4.5 Compensation Design
The following compensation loop design uses Channel 1 as example, but a design for Channel 2
follows the same rules.
TPS5124 uses voltage-mode control method. A Type III compensation network, formed by R1,
R2, R4, C14, C12, and C23, is used to guarantee the stability. The L-C frequency of the power
stage is around 5.4 kHz and the ESR zero is at 790 KHz due to the low ESR of the ceramic
capacitors. An overall crossover frequency (f0db) of 30 kHz is chosen for reasonable transient
response and stability. Both zeros (fZ1 and fZ2) from the compensator are set at 2.68 kHz. The
two poles (fP1 and fP2) and are set at 150 kHz and 2 MHz. The frequency of poles and zeros are
defined by the following equations.
fZ1 +1
2p R4 C14
fZ2 +1
2p R1 C12, assuming R1 ơR2
fP1 +1
2p R4 C23
fP2 +1
2p R2 C12, assuming C14 ơC23
The transfer function for the compensator is calculated as:
A(s) +(1)s C14 R2) [1)s C12 (R1 )R2)]
s R1 C14 ƪǒ1)C23
C14Ǔ)s R4 C23ƫ (1)s R2 C12)
100
−10
−30
−20
20
0
10
50
30
40
120
180
140
160
40
100
60
80
0
20
100 k
1 k 10 k
GAIN AND PHASE
vs
OSCILLATOR FREQUENCY
(CHANNEL 1)
Figure 4.
fOSC − Frequency − Hz
Phase − °
Gain − dB
Gain
Phase
VIN = 12 V
VOUT = 3.3 V
IOUT = 15 A
−10
−30
−20
20
0
10
30
40
120
140
160
40
100
60
80
0
20
180
100 100 k1 k 10 k
fOSC − Frequency − Hz
Gain − dB
GAIN AND PHASE
vs
OSCILLATOR FREQUENCY
(CHANNEL 2)
Figure 5. Channel 2
L = 0.6 µH
Phase − °
VIN = 12 V
VOUT = 1.5 V
IOUT = 10 A
Gain
Phase
−20
(11)
(12)
(13)
(14)
(15)

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High-Performance Dual Synchronous Buck Conversion Using the TPS5124
Figure 4 shows the closed loop gain and phase. For Channel 1, the overall crossover frequency
is approximately 30 kHz and the phase margin is 58°. For Channel 2, the crossover frequency is
approximately 23 kHz and phase margin is 55°.
4.6 Current Limiting
The current limit in TPS5124 is set using an internal current source and an external resistor
(R13 and R14). The current limit protection circuit compares the drain to source voltage of the
high-side and low-side drivers with respect to the set-point voltage. If the voltage exceeds the
limit during high side conduction, the current limit circuit terminates the high side driver pulse. If
the set point voltage is exceeded during low side conduction, the low side pulse is extended
through the next cycle. Together this action has the effect of decreasing the output voltage until
the under voltage protection circuit is activated and the fault latch is set and both the high-side
and low-side MOSFET drivers are shut off. Equation (16) should be used for calculating the
external resistor value for current protection set point.
RCL +
1.3 RDS(on) ǒILIM )IRIPPLE
2Ǔ
ITRIP
where
•RCL is external current limit resistor (R13 and R14)
•RDS(on) is the on−resistor of low side MOSFET (Q2 and Q4)
•1.3 is the temperature coefficient of the RDS(on)
•ILIM is the required current limit
•ITRIP is the internal current source with a typical value of 13 µA at 25°C
(16)

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12 High-Performance Dual Synchronous Buck Conversion Using the TPS5124
4.7 Timer Latch
The TPS5124 includes fault latch function with a user adjustable timer to latch the MOSFET
drivers in case of a fault condition. When either the OVP or UVP comparator detect a fault
condition, the timer starts to charge C18, the external capacitor connected to the SCP pin. The
circuit is designed so that for any value of C18, the undervoltage latch time tUVPL is about five
times larger than the overvoltage latch time tOVPL. The equations needed to calculate the
required value of C18 for the desired overvoltage and undervoltage latch delay times are
calculated in equations (17) or (18).
C18 +1.7 10*6 tUVPL
1.185
C18 +8 10*6 tOVPL
1.185
where
•C18 is the external capacitor connected to the SCP pin
•tUVPL is the time from UVP detection to latch
•tOVPL is the time from OVP detection to latch
For the EVM, tUVPL = 7 ms and tOVPL = 1.5 ms, so C18 = 0.01 µF.
If the voltage on the SCP pin reaches 1.185 V, the fault latch is set, and the MOSFET drivers are
set as follows:
4.7.1 Undervoltage Protection
The under voltage comparator circuit continually monitors the voltage at the INV pin. If the
voltage at that pin falls below 78% of the 0.85-V reference, the timer begins to charge C18. If the
fault condition persists beyond the time tUVPL, the fault latch is set and both the high-side and
low-side drivers is forced OFF.
4.7.2 Short circuit Protection
The short circuit protection circuitry uses the UVP circuit to latch the MOSFET drivers. When the
current limit circuit limits the output current, then the output voltage goes below the target output
voltage and UVP comparator detects a fault condition as described above.
4.7.3 Overvoltage Protection
The over voltage comparator circuit continually monitors the voltage at the INV pin. If VINV rises
above 112% of the 0.85-V reference, the timer begins to charge C18. If the fault condition
persists beyond the time tOVPL, the fault latch is set and the high-side drivers are forced OFF,
while the low-side drivers are forced ON.
CAUTION:
DO NOT set the SCP terminal to a voltage lower than 1.185 V while the device is
timing out an OVP or UVP event. If the SCP terminal is manually set to a voltage
lower than 1.185 V during this time, output overshoot may occur. The TPS5124
must be reset by grounding STBYx.
(17)
(18)

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High-Performance Dual Synchronous Buck Conversion Using the TPS5124
4.7.4 Disabling the Protection Function
If it is necessary to disable the protection functions of the TPS5124 for troubleshooting or other
purposes, the OCP, OVP and UVP circuits may be disabled.
4.7.4.1 Disabling Overcurrent Protection (OCP)
Remove the current limit resistors R13 and R14 to disable the current limit function.
4.7.4.2 Disabling Overvoltage Protection or Undervoltate Protection (OVP, UVP)
Grounding the SCP terminal can disable OVP and UVP.

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14 High-Performance Dual Synchronous Buck Conversion Using the TPS5124
5 Test Results
5.1 Efficiency Curves
The efficiency was tested under three different operation conditions.
IOUT − Output Current − A
Percent Efficiency − %
OVERALL EFFICIENCY
vs
OUTPUT CURRENT
VOUT1 (3.3 V) Enabled Only
Figure 6.
91
89
90
92
0 3 6 9 12 15
95
93
94
96 VIN = 6.5 V
VIN = 12 V
VIN = 15 V
IOUT − Output Current − A
Percent Efficiency − %
OVERALL EFFICIENCY
vs
OUTPUT CURRENT
VOUT2 (1.5 V) Enabled Only
Figure 7.
80
76
78
82
02 46810
88
84
86
90
92 VIN = 6.5 V
VIN = 12 V
VIN = 15 V

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High-Performance Dual Synchronous Buck Conversion Using the TPS5124
0 0.2 0.4 0.6 0.8 1.0
90
88
96
94
86
92
Output Power Over the Full Power
Percent Efficiency − %
OVERALL EFFICIENCY
vs
OUTPUT POWER
Both Channels Enabled
Figure 8.
VIN = 6.5 V
VIN = 12 V
VIN = 15 V
5.2 Typical Operating Waveform
Typical operating waveforms taken at VIN =12 V, IOUT1 = 15 A and IOUT2=10 A is shown in
Figure 9.
5.3 Start-Up Waveform
Figure 10 shows the start-up waveform taken at VIN =12 V, IOUT1 = 15 A and IOUT2=10 A. The
rising time is 2.85 ms for VOUT1 and 2.12ms for VOUT2.
Figure 9. Switch Node Waveform
t − Time − 2 µs/div
Figure 10. Start−Up Waveform
VOUT1
SS
VOUT2
t − Time − 10 ms/div

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16 High-Performance Dual Synchronous Buck Conversion Using the TPS5124
5.4 Output Ripple Voltage and Load Transient
The output ripple is about 20 mVP−P at 15 A on Channel 1 (3.3 V) output and 15 mVP−P at 10 A
on Channel 2 output as shown in Figure 11.
Figure 12 shows the load transient response. For Channel 1 (3.3 V), when the load steps from
0 A to 8.5 A, the overshoot and undershoot voltages are about 150 mV. For Channel 2 (1.5 V),
when the load steps from 0 A to 7.5 A, the overshoot voltage is approximately 220 mV and the
undershoot voltage is approximately 140 mV.
Figure 11. Output Ripple
Label
Label
t − Time − 2 µs/div
Figure 12. Load Transient Response
VOUT1
ILOAD Stepping from 0A to 8.5 A
t − Time − 40 µs/div Figure 13. Load Transient Response
VOUT2
ILOAD Stepping from 0A to 7.5 A
t − Time − 40 µs/div

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High-Performance Dual Synchronous Buck Conversion Using the TPS5124
6 Layout Guidelines
Proper design and layout is crucial to the performance of the power supply. Here are some
suggestions to the layout of TPS5124 design.
•A four−layer PCB design is recommended for designs using the TPS5124. Use at least one
layer dedicated to the PWRGND plane.
•All sensitive analog components such as INV, REF, CT, GND, SCP and SOFTSTART should
be reference to ANAGND.
•Ideally, all of the area directly under TPS5124 chip should also be ANAGND.
•ANAGND and PWRGND should be isolated as much as possible, with a single point
connection between them
6.1 Low side MOSFET(s)
•The source of low-side MOSFET(s) should be referenced to PWRGND. Otherwise ANAGND
is subject to the noise of the outputs.
•PWRGND should be placed close to the source of low-side MOSFET(s).
6.2 Connections
•Connections from the drivers to the gate of the power MOSFETs should be as short and
wide as possible to reduce stray inductance. This becomes more critical if external gate
resistors are not used. In addition, external gate resistor for the high-side FET(s) will
considerably reduce the noise at the LL node and improve the performance of the current
limit function.
•The connection from LL to the power MOSFET(s) should be as short and wide as possible.
6.3 Bypass capacitor
•The bypass capacitor for VCC should be placed close to the TPS5124.
•The bulk storage capacitors across VCC should be placed close to the power MOSFETs.
High-frequency bypass capacitors should be placed in parallel with the bulk capacitors and
connected close to the drain of the high-side MOSFET(s) and to the source of the low-side
MOSFET(s).
•For noise reduction, a 0.1-µF capacitor CTRIP should be placed in parallel with the trip
resistor RCL.
6.4 Bootstrap capacitor
•The bootstrap capacitor CBS (connected from LH to LL) should be placed close to the
TPS5124.
•LH and LL should be routed close to each other to minimize noise coupling to these traces.

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18 High-Performance Dual Synchronous Buck Conversion Using the TPS5124
•LH and LL should not be routed near the control pin area (e.g. INV, FB, REF, etc.).
6.5 Output voltage
•The output voltage sensing trace should be isolated by either ground plane.
•The output voltage sensing trace should not be placed under the inductors on the same
layer.
•The feedback components should be isolated from output components, such as, MOSFETs,
inductors, and output capacitors. Otherwise the feedback signal line is susceptible to output
noise.
•The resistors to set up the output voltage should be referenced to ANAGND.
•The INV trace should be as short as possible.
7 PCB layout
Figures 14 through 18 shows the PCB layout.
Figure 14. Top Assembly

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High-Performance Dual Synchronous Buck Conversion Using the TPS5124
Figure 15. Top Side
Figure 16. Internal 1

SLUU182 − March 2004
20 High-Performance Dual Synchronous Buck Conversion Using the TPS5124
Figure 17. Internal 2
Figure 18. Bottom Side