Texas Instruments TLIN1431EVM User manual

User’s Guide
TLIN1431EVM User's Guide
ABSTRACT
This user guide describes the TLIN1431-Q1 evaluation module (EVM). This EVM helps designers evaluate
the device performance, support fast development, and analyze automotive local interconnect network (LIN)
systems using the TLIN1431-Q1 family of LIN system basis chips (SBCs), which include wake functionality,
integrated high-side switch, and watchdog.
Figure 1-1. TLIN1431EVM Board Image
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Table of Contents
1 Introduction.............................................................................................................................................................................3
1.1 Features............................................................................................................................................................................. 3
1.2 Description......................................................................................................................................................................... 3
2 EVM Setup and Features........................................................................................................................................................4
2.1 Startup Mode Configurations............................................................................................................................................. 4
2.2 Commander and Responder Configurations......................................................................................................................5
2.3 Local Wake-Up...................................................................................................................................................................5
2.4 Channel Expansion............................................................................................................................................................ 6
2.5 VBAT Voltage Divider...........................................................................................................................................................7
2.6 Reset Input.........................................................................................................................................................................7
2.7 Logic-Level LIMP and WAKE Signals................................................................................................................................ 7
2.8 High-Voltage Signal Monitoring..........................................................................................................................................8
2.9 TXD and RXD.................................................................................................................................................................... 8
2.10 VCC Load Testing............................................................................................................................................................ 8
2.11 SPI Interface.....................................................................................................................................................................8
3 Jumpers, Headers, Connectors, Test Points, and Switches...............................................................................................9
4 Bill of Materials......................................................................................................................................................................11
5 Schematic..............................................................................................................................................................................14
Trademarks
All trademarks are the property of their respective owners.
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1 Introduction
1.1 Features
The EVM supports the following features:
• Commander and slave configuration options
• Terminal block and header pins on all power and LIN bus connections
• Access to the LDO output VCC
• Accessible wake functionality with push-button
• Selectable pull-up and pull-down resistors for device pins
• Logic-level signals for high-voltage WAKE and LIMP signals
• Test point connections for each board signal
1.2 Description
The TLIN1431EVM provides users with the ability to evaluate the TI TLIN1431-Q1 family of single-channel
LIN SBCs, which include LDO, wake, high-side switch, watchdog, integrated battery voltage divider, LIMP, and
channel expansion functionality. The EVM allows both commander and responder mode applications to be
evaluated through the use of a single jumper that connects or disconnects the external 1 kΩ pull-up resistor and
series diode required in commander mode applications on the LIN bus.
The EVM has access to the integrated VCC rail from the device LDO. This LDO output can be used as
logic-level input voltages for the logic pins of the TLIN1431-Q1. The TLIN14315-Q1 includes a 5-V LDO, and
the high-level logic inputs to the device can range from 2 V to 5.25 V, though the biasing of the PIN/nCS pin
determines whether 3.3 V SPI or 5 V SPI is used (known as “VIOless” capability). This allows the TLIN14315-Q1
to interface with both 3.3 V and 5 V logic levels. The TLIN14313-Q1 includes a 3.3-V LDO, and the high-level
logic inputs to the device range from 2 V to 3.6 V, allowing interfacing with 3.3 V systems.
Non-populated pads are included on TXD, RXD, and LIN to accommodate a variety of different tests requiring
various capacitive load conditions. Additionally, the LIN signal contains a non-populated SOD-323 footprint on
LIN allowing for the implementation of an ESD1LIN24-Q1 protection device as desired.
The TLIN SBC family supports both 12 V and 24 V automotive applications and is operated with a supply voltage
from 5.5 V to 28 V, and is capable of handling supply/battery voltages up to 42 V. The LIN bus provides extended
bus fault protection of ±58 V.
External headers with power and LIN bus connections allow for the EVM to be evaluated in a larger system.
Additional, channel expansion outputs provide the capability of interfacing with another device, such as a
TCAN1042-Q1 or a TLIN1021-Q1 (or other TCAN and TLIN devices) as applicable.
The wake input functionality of the TLIN1431-Q1 is accessible in many ways, including via external interface or
push-button wake.
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2 EVM Setup and Features
Use the following equipment to evaluate the performance of the TLIN1431-Q1:
• Power supply capable of supplying the desired supply voltage. Typical LIN applications use 12 V or 24 V, but
the TLIN1431-Q1 can operate with any supply voltage from 5.5 V to 28 V. Connect this voltage across the
VBAT and GND pins of the J11 paired banana jack connector.
• If the LIN bus interface is to be observed using an oscilloscope, use probes capable of tolerating voltages as
large as VBAT.
• The logic interface pins may interface to a microcontroller, pattern generator, or logic analyzer with logic
levels matching the LDO VCC voltage, or a high-level voltage consistent with the VIH requirements of the
device.
• The LDO output can be used for testing load and thermal capabilities with a source meter or physical
resistance connected between the jumper pins on J4 (pins 1 and 2) or any other VCC output pin or test point.
• An external device to be controlled via the channel expansion functionality (accessed from J6 and J7) can be
connected using jumper cables or wires as appropriate.
2.1 Startup Mode Configurations
2.1.1 Pin and SPI Modes
Two modes of operation are available on the TLIN1431-Q1: pin mode and SPI mode. The mode of the device is
determined by the state of pin 7 (PIN/nCS) upon power-up. If pin 7 is pulled low or connected to GND at startup,
the device operates in pin mode, with no SPI interface. If pin 7 is left floating or pulled high at startup, then the
device operates in SPI mode, where the SPI interface is enabled and the user can access the internal registers
of the device.
Additionally, the TLIN14315-Q1 is capable of VIO less operation as determined by the biasing of this PIN/nCS
pin. If it is left floating, the device operates using 3.3 V SPI communication. If it is pulled high to 5 V, then it
operates using 5 V SPI communication.
10k

500k

GND
PIN/nCS PIN Mode 3.3 V SPI 5 V SPI
3.3 V
PIN/nCS
3.3 V
PIN/nCS
3.3 V
VCC
(5 V)
Figure 2-1. PIN/nCS Configuration
Note the TLIN14313-Q1, which includes a 3.3 V LDO, does not include VIOless operation and is only capable of
3.3 V SPI communication.
J5 allows for easy biasing of the PIN/nCS pin to either a pull-down resistor for pin mode or floating/pull-up for
VIOless SPI mode operation.
The TLIN1431-Q1 device has alternate pin designations and functions depending on the power-up mode
chosen. The designations are shown in Table 2-1, and the functions of each pin are described in the TLIN1431-
Q1 data sheet.
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Table 2-1. Pinout in Pin Mode vs. Pinout in SPI Mode
Pin Pin mode SPI mode
4WDT – Programmable watchdog window set input CLK – SPI clock input
5nWDR – Watchdog failure output trigger SDO – SPI serial data output
6WDI – Watchdog timer edge-triggered input SDI – SPI serial data input
7PIN – Input that sets the device to pin mode nCS – SPI chip select
8EN – Device mode change input nINT – Device interrupt output
9HSSC – High-side switch control input FSO – Function output
The user can start up the TLIN1431-Q1 into pin mode by connecting a shunt between pins “PIN/nCS” and
“GND_PD” of J5, which applies a pull-down to GND to pin 7. Leaving all pins of J5 floating results in the
TLIN1431-Q1 operating in SPI mode, and the TLIN14315-Q1 operates with 3.3 V SPI. Connect a shunt between
pins “PIN/nCS” and “VCC_PU” of J5 to apply a pull-up to VCC, resulting in 5 V SPI operation for the TLIN14315-
Q1.
2.1.2 Wake Request (WKRQ) vs. Inhibit Output (INH)
The WKRQ/INH pin has the capability of operating as either a logic-level wake request (WKRQ) digital output,
or a high-voltage inhibit (INH) output based upon its biasing at startup. Applying a 100 kΩ or stronger pull-down
to GND on this pin results in the pin behaving as logic-level WKRQ. Alternatively, leaving this pin floating or
applying a 1 MΩ pull-down to GND results in the pin behaving as high-voltage INH.
Control
VSUP
WKRQ/
INH
VINT
Control
VSUP
WKRQ/
INH
VINT
INH
GND
WKRQ
100 k 
GND
1 M

Floating or 1 M

pull-
down make pin INH
Figure 2-2. WKRQ or INH Pin Select
The user can configure this pin as WKRQ by connecting a shunt between pins “U1.16” and “WKRQ” of J2
to apply a 100 kΩ pull-down. Alternatively, the user can configure the WKRQ/INH pin as high-voltage INH by
connecting a shunt between pins “U1.16” and “INH” of J2 at power-up to apply a 1 MΩ pull-down, or by leaving
all of these pins floating. In addition, capacitor pad C29 allows for the user to test a capacitor in parallel with the
1 MΩ resistor in order to evaluate the behavior of this pin at startup.
2.2 Commander and Responder Configurations
The TLIN1431-Q1 has an internal pull-up resistor and serial diode on LIN that allows it to operate as a
responder. To operate as a commander, an external 1 kΩ pull-up and serial diode is required on the bus.
The user can apply a shunt between the pins of J10 to apply this 1 kΩ pull-up and allow for use as a commander
node.
2.3 Local Wake-Up
The WAKE pin of the TLIN1431-Q1 is used for the local wake-up (LWU) function of the device, which is
explained in detail in the data sheet. This can be directly interfaced close to the device using J15, pin “WAKE”
without a shunt. Applying a shunt to J15 applies a pull-up and allows the use of the WAKE switch on the board.
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J14 allows the user to select the pull-up source for this circuitry. Connect a shunt between pins “WAKE_PU” and
“VBAT” to apply a pull-up to the battery voltage rail. In this configuration, the user can implement push-button
wake using the WAKE switch S1.
Connecting a shunt between pins “WAKE_PU” and “HSS” of J14 provides a pull-up to the high-side switch of
the device. This configuration is required if the user intends to implement cyclic-sense wake functionality. This
functionality is described in detail in the device’s data sheet.
2.4 Channel Expansion
The VCC, FSO, HSS, and VSUP pins allow for channel expansion, such that the TLIN1431-Q1 can control
an external transceiver or similar device. This effectively allows for an additional communication channel to be
controlled via the TLIN1431-Q1.
TLIN1431x-Q1
VDD33 VSUP
VSUP
VBAT
VBAT
DIV_ON
PV
20 pF
500 k

HSS
3.3 V
LDO
INH
1 M

1 M

pull-down or
leave floating for INH
100 nF
470

VSUP
Micro
TLIN1039
nCS
CLK
SDI
SDO
TXD
RXD
FSO
EN
LIN
LIN
TXD
RXD
LIMP
WAKE
VCC = 3.3V/5V
100 nF
nRST
nINT
I/O
VDD
LIN Controller
Or
SCI/UART
10 k

VDD
10 µ F
Figure 2-3. Channel Expansion with LIN Transceiver
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VIO
100 nF
CANH
CANL
3.3 V
TCAN1044VA
TLIN14315-Q1
VDD33 VSUP
VSUP
VBAT
VBAT
DIV_ON
PV
20 pF
500 k

3.3 V
LDO
INH/
WKRQ
1 M

1 M

pull-down or
leave floating for INH
100 nF
470

VCC = 5V
Micro
nCS
CLK
SDI
SDO
TXD
RXD
FSO
STB
LIN
TXD
RXD
LIMP
HSS
WAKE
100 nF
nINT
I/O
VDD
LIN Controller
Or
SCI/UART
CAN
Controller
nRST
10 k

VDD
10 µ F
VCC
Figure 2-4. Channel Expansion with CAN Transceiver
Note that the VCC and FSO pins are logic-level voltages, while the HSS and VSUP signals are high-voltage
outputs. Use care when implementing these outputs to ensure the proper voltage design requirements are met.
2.5 VBAT Voltage Divider
To activate the internal VBAT voltage divider on the TLIN1431-Q1, apply a high signal on DIV_ON using the
appropriate pin on J4. By default, an internal pull-down deactivates the internal voltage divider when the pin is
left floating.
The output of the voltage divider can be measured on PV.
2.6 Reset Input
Push-button nRST interfacing is possible using S2 on the EVM. Pressing S2 delivers a strong pull-down to the
active-low nRST pin.
2.7 Logic-Level LIMP and WAKE Signals
This EVM implements on-board comparators to provide logic-level outputs representing the states of LIMP and
WAKE respectively, which are high-voltage signals for the device. These are provided as “LIMP_MCU” and
“WAKE_MCU” on J4, thus configuring all J4 signals as logic-level, and potentially capable of being connected to
general-purpose inputs on an external micro controller.
Note that LIMP_MCU and WAKE_MCU are outputs, and are not connected to LIMP and WAKE. Thus, for
example. a signal cannot be applied to WAKE_MCU that would impact the high-voltage WAKE signal on the
TLIN1431-Q1.
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It is also possible to reconfigure the WAKE_MCU output to reflect the state of HSS rather than WAKE. This can
be accomplished by depopulating R17 and populating a 0 Ω resistor on R19. Take care to ensure that only one
of these resistors is populated at a time.
2.8 High-Voltage Signal Monitoring
INH, HSS, and WAKE, which are high-voltage signals for the TLIN1431-Q1, can be monitored using the
three orange test points on the board: TP1 (WAKE), TP15 (WKRQ/INH), and TP16 (HSS). These are colored
differently from the logic-level signals accessible via the other test points on the board.
2.9 TXD and RXD
TXD and RXD are accessible either via TP24/TP25, or via the J8 connector. These can be used to interface with
the input/output signals of the LIN bus.
Pads R15 and C9 allow for additional pull-down resistance or capacitance on the TXD line if it is needed for
applications such as oscilloscope impedance matching. Pad C11 allows for the addition of capacitance to the
RXD line.
Placing a shunt on J17 provides a pull-up to RXD. The TLIN1431-Q1 does not require a pull-up on RXD to
operate, though this can be used to evaluate the performance of RXD under these conditions.
2.10 VCC Load Testing
The LDO output (VCC) is accessible using TP4 or via pin 1 of J4. The user can apply a load to these pins to test
the stability and performance of the LDO on the TLIN1431-Q1.
2.11 SPI Interface
When operating in SPI mode, pins 4-7 of the TLIN1431-Q1 become the SPI interface for the device. Specifically,
“WDT/CLK” is the SPI clock input, “nWDR/SDO” is the SPI serial data output, “WDI/SDI” is the SPI serial data
input, and “PIN/nCS” is the SPI active-low chip select.
The four SPI interface pins are accessible via J4, pins 12, 14, 16, and 18. These four signals are vertically
separated from the rest of the logic signals on J4. Per the silkscreen legend on the board, these four signals are
on the leftmost column of J4, while the remaining signals on this header are located on the rightmost column.
These four SPI signals can be connected to a micro controller or similar processor to control the TLIN1431-Q1
via SPI. Note that the device must start up with PIN/nCS (pin 7) floating or pulled high to interface via SPI mode.
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3 Jumpers, Headers, Connectors, Test Points, and Switches
Table 3-1, Table 3-2, and Table 3-3 list all the jumpers, headers, connectors, test points, and switches on the
TLIN1431EVM and explain the functions of each of these components.
Table 3-1. Jumpers, Headers, and Connectors
Designator Function
J1 Connector for WDT/CLK, with adjacent VCC and GND pins for WDT triggering, or GND referencing for CLK
function.
J2 Connector for WKRQ/INH as described in Section 2.1.2.
J3 Connector for EN/nINT, with adjacent pull-up to VCC and GND pins for interfacing the enable/interrupt pin.
J4 Generic output connector with multiple board signals connected. Pins 4-7, which are SPI communication pins in SPI
mode, are separated column-wise from the other signals on J4. The non-signal pins are connected to GND.
J5 Connector for PIN/nCS, which is used to configure the startup mode of the TLIN1431-Q1 as described in Section
2.1.1 and operates as chip-select in SPI mode.
J6 & J7 Channel expansion output as described in Section 2.4.
J8 TXD and RXD connection as described in Section 2.9.
J9 Terminal block connector for LIMP.
J10 Commander node selector, as described in Section 2.2.
J11 Banana jack connector for the VBAT and GND supplies for the device.
J13 Connector for VBAT and VSUP.
J14 & J15 Configuration connectors for pull-up on WAKE pin, as described in Section 2.3.
J16 LIN output with adjacent VBAT and GND pins.
J17 RXD pull-up selector, as described in Section 2.9.
J18 Pull-down connector for LIMP. Connect a shunt to apply a 100 kΩ pull-down on the LIMP pin.
J21 GND connection rail.
Table 3-2. Test Points
Designator Function
TP1 Test point for WAKE (HV)
TP2 Test point for LIMP (HV)
TP3 Test point for VSUP (HV)
TP4 Test point for VCC
TP5 Test point for VBAT (HV)
TP6-TP14 GND connections
TP15 Test point for WKRQ/INH (HV possible)
TP16 Test point for HSS (HV)
TP17 Test point for nRST
TP19 Test point for nWDR/SDO
TP20 Test point for PV
TP22 Test point for WDT/CLK
TP23 Test point for PIN/nCS
TP24 Test point for TXD
TP25 Test point for RXD
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Table 3-3. Switches
Designator Function
S1 Push-button switch for WAKE interfacing, only active if J14 and J15 are appropriately connected as described in
Section 2.3.
S2 Push-button switch for applying a strong pull-down to nRST as described in Section 2.6.
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