Texas Instruments LMK04208 User manual

LMK04208
User's Guide
Literature Number: SNAU200
September 2016

2SNAU200–September 2016
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Table of Contents
Contents
1 Introduction......................................................................................................................... 3
2 Evaluation Board Kit Contents............................................................................................... 3
3 Quick Start.......................................................................................................................... 4
3.1 Quick Start Description.................................................................................................. 5
4 PLL Loop Filters and Loop Parameters................................................................................... 7
4.1 PLL1 Loop Filter.......................................................................................................... 7
4.2 PLL2 Loop Filter.......................................................................................................... 7
5 Default TICS Pro Modes for the LMK04208.............................................................................. 8
6 Using TICS Pro to Program the LMK04208.............................................................................. 8
6.1 Start TICS Pro Application.............................................................................................. 8
6.2 Select Device ............................................................................................................. 8
6.3 Setup and Confirm Communications .................................................................................. 8
6.4 Restoring a Default Mode............................................................................................... 9
6.5 Program/Load Device.................................................................................................... 9
6.6 Visual Confirmation of Frequency Lock ............................................................................... 9
6.7 Enable Clock Outputs.................................................................................................. 10
7 Evaluation Board Inputs and Outputs ................................................................................... 11
8 Recommended Test Equipment ........................................................................................... 14
9 Schematics........................................................................................................................ 15
10 Bill of Materials .................................................................................................................. 20
Appendix A TICS Pro Usage ........................................................................................................ 22
A.1 Communication Setup Window...................................................................................... 22
A.2 CLKins and PLLs Page............................................................................................... 23
A.3 Clock Outputs Page................................................................................................... 24
A.4 User Controls Page ................................................................................................... 25
A.5 Raw Registers Page .................................................................................................. 26
A.6 Burst Mode Page...................................................................................................... 27
Appendix B Typical Phase Noise Performance Plots ...................................................................... 28
B.1 VCXO Phase Noise 122.88 MHz ................................................................................... 29
B.2 Clock Output Phase Noise Measurements ........................................................................ 30

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LMK04208 User’s Guide
MICROWIRE is a trademark of Texas Instruments.
User's Guide
SNAU200–September 2016
LMK04208 User’s Guide
1 Introduction
This user's guide describes how to set up and operate the LMK04208 evaluation module (EVM). The
LMK04208 is the industry's highest performance clock conditioner with JEDEC JESD204B support.
2 Evaluation Board Kit Contents
The evaluation board kit includes what is shown in Table 1.
Table 1. EVM Contents
SV601293 -001
Evaluation Board (1) LMK04208 Evaluation Board
USB Communications (1) USB2ANY

Laptop or PC
4 to 5 V
3
4Program with TICS Pro
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CLKin1*
Reference clock from
signal generator or other
external source.
122.88 MHz (Default)
2
Power
Reference
CLKout5*
LVPECL
CLKout5
CLKin0
CLKin0*
These SMAs not populated by default.
With PCB change, can be used for reference input for
single PLL mode.
CLKout1* LVDS or LVCMOS CLKout1 Vcc
CLKout4*
LVDS or
LVCMOS
CLKout4
D1, LD_TP
Status_LD pin
10 pin cable
OSCout* LVDS or LVCMOS OSCout
CLKout0
LVPECL
CLKout0*
D4, Holdover_TP
Status_Holdover pin
1
Default is LDO to IC.
Do not connect 4 to 5 V
direct to IC (typical 3.3 V)
USB2ANY
Programming
Connection
OSCin
OSCin*
USB2ANY
USB Cable
122.88 MHz VCXO
CLKin1_IND
Place 270 ohm on R46 to connect
CLKin0_IND
Place 270 ohm on R47 to connect
SYNC_TP
All CLKout and OSCout outputs are capable of
LVDS, LVPECL, and LVCMOS output formats.
However the output format suited to default
PCB configuration (if emitter resistors are
placed for LVPECL) is identified above.
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3 Quick Start
Figure 1. Quick Start Diagram

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3.1 Quick Start Description
The LMK04208 EVM allows full verification of the device functionality and performance specifications. To
quickly set up and operate the board with basic equipment, refer to the quick start procedure below and
test setup shown in Figure 1.
1. Connect a voltage of 4.5 volts to the Vcc SMA connector or terminal block. Device operates at 3.3 V
using onboard LP3878-ADJ LDO. VCXO operates at 3.3 V using onboard LP5900 LDO.
2. Connect a reference clock to the CLKin1 port from a signal generator or other source. Use 122.88 MHz
for default. Exact frequency and input port (CLKin0/CLKin1) depends on programming.
3. Connect uWire (MICROWIRE) header to a computer using USB2ANY.
4. Program the device with TICS Pro. TICS Pro is available for download at: http://www.ti.com/tool/TICS
Pro. After starting TICS Pro.
(a) Choose LMK04208 from the “Select Device" →"Clock Generator/Jitter Cleaner (Dual Loop)” Menu.
(b) Open the Communication Setup window by click "USB Communications →Interface".
• Confirm that USB2ANY is selected.
• Select specific USB2ANY interface to use. click 'Identify' to confirm selected USB2ANY and
valid communications to USB2ANY by blinking LED.
• If LMK04208EVM or USB2ANY available, the software may be run in DemoMode for evaluation
and generation of register programming data.
• Press Close to exit Communication Setup.
(c) From menu bar click "Default configuration" to select a default mode. For the quick start use,
“CLKin1 122.88 MHz, 122.88 MHz VCXO”
(d) Click "Write All Registers" or press Ctrl-L to load all registers. Alternatively from menu bar click
"USB communications" →"Write All Registers."
5. Measurements may be made at an active CLKout port via its SMA connector. Default configuration
configures CLKout4
3.1.1 CLKout Page Description
Figure 2. Clock Outputs Page CLKout Path Description Diagram
1. CLKoutX_DDLY for controlling digital delay. Programmed delay value takes effect on SYNC of divider.
2. CLKoutX_HS for finer resolution of digital delay. Advances waveform ½ device clock cycles, -0.5 to
digital delay.
3. CLKoutX_DIV, divider for the output channel.
4. CLKoutX_ADLY, Analog delay if enabled with #5.
5. CLKoutX_ADLY_SEL, Analog delay select.
6. CLKoutX_TYPE, clock output format.
7. NO_SYNC_CLKoutX, when checked, output will never be SYNCed or held in SYNC.
8. Clock output identifier.
9. Calculated clock output frequency.
10. CLKoutX_PD, power down the entire CLKoutX group.

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3.1.2 TICS Pro Tips
• Mousing over controls shows help in the "Context" window to bottom left of screen.
• In bottom left of screen is displayed a "General" help for the page. After context help has been
displayed, click this tab to view again.
• To enable read back for LMK04208, a 0-Ωresistor must be placed at R59, this shares
Status_Holdover for use as read back. R59 is located just below the red D4 Status_Holdover LED.

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4 PLL Loop Filters and Loop Parameters
In jitter cleaning applications that use a cascaded or dual PLL architecture, the first PLL’s purpose is to
substitute the phase noise of a low-noise oscillator (VCXO or crystal resonator) for the phase noise of a
“dirty” reference clock. The first PLL is typically configured with a narrow loop bandwidth in order to
minimize the impact of the reference clock phase noise. The reference clock consequently serves only as
a frequency reference.
The loop filters on the LMK04208 evaluation board are setup using the approach above. The loop filter for
PLL1 has been configured for a narrow loop bandwidth (< 100 Hz). Table 2 and Table 3 contain the
parameters for PLL1 and PLL2 for using the default VCXO.
TI’s Clock Design Tool can be used to optimize PLL phase noise/jitter for given specifications. See:
http://www.ti.com/tool/clockdesigntool.
4.1 PLL1 Loop Filter
(1) Loop Bandwidth and Phase Margin is a function of Kφ, Kvco, N as well as loop components. Changing Kφand N by device
programming will change the loop bandwidth.
Table 2. PLL1 Loop Filter Parameters for VCXO with 8 kHz/V Tuning Sensitivity(1)
PLL1 using 122.88 MHz VCXO (Epson VG-4513CA-122.8800M-GFCT3)
Loop Bandwidth 20 Hz Phase Margin 50˚
Kφ(Charge Pump) 100 µA Tuning Sensitivity (KVCO)8 kHz/V
Reference Clock Frequency 122.88 MHz Phase Detector Freq 1.024 MHz
PLL Total N 120 VCXO Frequency 122.88 MHz
(PLL1 feedback and PLL2
reference)
Loop Filter Components C1_VCXO = 150 nF C2_VCXO_0603 = 1 µF R2_VCXO = 22 kΩ
4.2 PLL2 Loop Filter
(1) Loop Bandwidth is a function of Kφ, Kvco, N as well as loop components. Changing Kφand N will change the loop bandwidth.
Table 3. PLL2 Loop Filter Parameters using Integrated VCO(1)
PLL2 using internal VCO
Loop Bandwidth 320 kHz Phase Margin 84˚
Kφ(Charge Pump) 3.2 mA Tuning Sensitivity (KVCO)27 MHz/V
Reference Clock Frequency 122.88 MHz Phase Detector Freq 122.88 MHz
PLL Total N 24 VCO Frequency 2949.12 MHz
Loop Filter Components C1_VCO = 0.022 nF C2_VCO = 18 nF Integrated C3 and C4 = 0.01 nF
R2_VCO = 0.56 kΩIntegrated R3 and R4 = 200 Ω

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5 Default TICS Pro Modes for the LMK04208
TICS Pro saves the state of the selected LMK04208 device when exiting the software. To ensure a
common starting point, the following modes listed in Table 4 may be restored by clicking “Mode” and
selecting the appropriate device configuration.
Table 4. Default TICS Pro Modes for the LMK04208
Default TICS Pro Mode Device Mode CLKin Frequency OSCin Frequency
CLKin1 122.88 MHz, OSCin
122.88 MHz Dual PLL, Internal VCO 122.88 MHz 122.88 MHz
CLKin0 122.88 MHz, Dual
Loop 0-delay, 122.88 MHz
VCXO
Dual PLL 0-delay, Internal
VCO 122.88 MHz 122.88 MHz
Figure 3. Selecting a Default Mode for the LMK04208 Device
6 Using TICS Pro to Program the LMK04208
This section will demonstrate how to use TICS Pro. Making measurements with the LMK04208 device will
serve as an example. For more information on using TICS Pro, refer to Appendix A and TICS Pro
instructions, "Help" →"TICS Pro User Manual."
Before proceeding, be sure to follow the instructions in Section 3 to ensure proper connections.
6.1 Start TICS Pro Application
Click “Start” →“Programs” →“Texas Instruments” →“TICS Pro” →“TICS Pro”
The TICS Pro program is installed by default to the TICS Pro application group.
6.2 Select Device
Click “Select Device" →"Clock Generator/Jitter Cleaner (Dual Loop)" →"LMK04208”
Upon start, TICS Pro will load the last used device. To load a different device, click “Select Device” from
the menu bar, then select the subgroup and finally, the device to load. For this example, the LMK04208 is
chosen.
6.3 Setup and Confirm Communications
If not already plugged in, connect USB2ANY interface. Click "USB communications" →"Interface"
Ensure USB2ANY is selected in the Communication Setup window. Press the Identify button to confirm
desired USB2ANY is selected by observing blinking LED. Other instances of TICS Pro can be used at the
same time, but if a USB2ANY is used in one application, in cannot be used in the second and may not
show up.

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6.4 Restoring a Default Mode
Click “Mode” →“CLKin1 122.88 MHz, 122.88 MHz VCXO”; then press Ctrl+L.
Figure 4. Setting the Default Mode for LMK04208
For the purpose of this walkthrough, a default mode will be loaded to ensure a common starting point.
This is important because when TICS Pro is closed, it remembers the last settings used for a particular
device. Again, remember to press Ctrl+L as the first step after loading a default mode.
6.5 Program/Load Device
Provided the communication settings are correct, press the “Ctrl+L” shortcut or click “Keyboard Controls”
→“Load Device” from the menu to program the device to the current state of the newly loaded LMK04208
file.
Figure 5. Loading the Device
Once the device has been initially loaded, TICS Pro will automatically program changed registers so it is
not necessary to reload the device upon subsequent changes in the device configuration. It is possible to
disable this functionality by ensuring there is no checkmark by the “Options” →“AutoUpdate.”
Because a default mode will be restored in the next step, this step isn’t really needed but included to
emphasize the importance of pressing “Ctrl+L” to load the device at least once after starting TICS Pro,
restoring a mode, or restoring a saved setup using the File menu.
See TICS Pro instructions by clicking "Help" →"TICS Pro User Manual." This contains information on
troubleshooting communications.
6.6 Visual Confirmation of Frequency Lock
After a default mode is restored and loaded, LED D1 will illuminate when PLL1 and PLL2 are locked to the
reference clock applied to CLKin1. This assumes LD_MUX = PLL1 & PLL2 DLD and LD_TYPE = Output
(Push-Pull).

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6.7 Enable Clock Outputs
While the LMK04208 offers programmable clock output buffer formats, the evaluation board is shipped
with pre-configured output terminations to match the default buffer type for each output.
To measure Phase noise at one of the clock outputs, for example CLKout0:
1. Click on the Clock Outputs page,
2. Uncheck “Powerdown” in the Clock output box to enable the channel. (10)
3. Set the following as needed:
(a) Digital Delay value (1)
(b) Clock Divider value (3)
(c) Analog Delay Select and Analog Delay Value, if desired (4 and 5). Analog delay will add to noise
floor of output.
Figure 6. Setting Digital Delay, Clock Divider, Analog Delay and Output Format
4. Depending on the configured output type, the clock output SMAs can be interfaced to a test instrument
with a single-ended 50-Ωinput as follows.
(a) For LVDS:
(i) A balun (like ADT2-1T or high quality Prodyn BIB-100G) is recommended for differential-to-
single-ended conversion.
(b) For LVPECL:
(i) A balun can be used, or
(ii) One side of the LVPECL signal can be terminated with a 50-Ωload and the other side can be
run single-ended to the instrument.
5. The phase noise may be measured with a spectrum analyzer or signal source analyzer.

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7 Evaluation Board Inputs and Outputs
Table 5 contains descriptions of the inputs and outputs for the evaluation board. Unless otherwise noted,
the connectors described can be assumed to be populated by default. Additionally, some applicable TICS
Pro programming controls are noted for convenience.
Table 5. Description of Evaluation Board Inputs and Outputs
CONNECTOR NAME SIGNAL TYPE,
INPUT/OUTPUT DESCRIPTION
Populated:
CLKout0, CLKout0*,
CLKout1, CLKout1*,
CLKout4, CLKout4*,
CLKout5, CLKout5*
Analog,
Output Clock outputs with programmable output buffers.
Default output terminations on the evaluation board are shown below:
Clock Output Default Board Termination
CLKout0 240 Ωemitter resistor, LVPECL
CLKout1 open, LVDS/LVCMOS
CLKout2 240 Ωemitter resistor, LVPECL
CLKout3 240 Ωemitter resistor, LVPECL
CLKout4 open, LVDS/LVCMOS
CLKout5 240 Ωemitter resistor, LVPECL
Not Populated:
CLKout2, CLKout2*,
CLKout3, CLKout3*
Each CLKout has a programmable LVDS, LVPECL, or LVCMOS output buffer. The
output buffer type can be selected in TICS Pro on the Clock Outputs page via the
CLKoutX_TYPE control.
All clock outputs are AC-coupled to allow safe testing with RF test equipment.
If an output is programmed to LVCMOS, each output can be independently
configured (normal, inverted, or off/tri-state). Best performance/EMI reduction is
achieved by using a complementary output mode like Norm/Inv. It is NOT
recommended to use Norm/Norm or Inv/Inv mode.
Populated:
OSCout, OSCout*
Analog,
Output Buffered output of OSCin port.
The output terminations on the evaluation board are shown below.:
OSC Output Default Board Termination
OSCout open, LVDS/LVCMOS
OSCout has a programmable LVDS, LVPECL, or LVCMOS output buffer. The
output buffer type can be selected in TICS Pro on the Clock Outputs page via the
OSCout_TYPE control.
OSCout is AC-coupled to allow safe testing with RF test equipment.
If OSCout is programmed as LVCMOS, each output can be independently
configured (normal, inverted, inverted, and off/tri-state). Best performance/EMI
reduction is achieved by using a complementary output mode like Norm/Inv. It is
NOT recommended to use Norm/Norm or Inv/Inv mode.
Populated:
Vcc
Power,
Input Main power supply input for the evaluation board. The LMK04208 contains internal voltage regulators for the VCO, PLL and other
internal blocks. The clock outputs do not have an internal regulator, so a clean
power supply with sufficient output current capability is required for optimal
performance.
On-board LDO regulators and 0 Ωresistor options provide flexibility to supply and
route power to various devices. See the schematics in section Section 9 for more
details.
Apply power to either Vcc SMA or J1, but not both.
Populated:
J1 Power,
Input Alternative power supply input for the evaluation board using two unshielded wires (Vcc and GND).
Apply power to either Vcc SMA or J1, but not both.
Not Populated:
VccVCXO/Aux
Power,
Input Optional Vcc input to power the VCXO circuit if separated voltage rails are needed. The VccVCXO/Aux input can power these circuits directly or supply the on-board
LDO regulators. 0 Ωresistor options provide flexibility to route power.
This connector is on the bottom of the PCB.

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Table 5. Description of Evaluation Board Inputs and Outputs (continued)
CONNECTOR NAME SIGNAL TYPE,
INPUT/OUTPUT DESCRIPTION
Populated:
CLKin0, CLKin0*,
FBCLKin*/CLKin1*
Analog,
Input Reference Clock Inputs for PLL1 (CLKin0, CLKin1) CLKin0/CLKin0* is configured by default for a differential reference clock input from
a 50-ohm source.
FBCLKin*/CLKin1* is configured by default for a single-ended reference clock input
from a 50-ohm source using a 3 dB pad for termination which is recommended for
high speed inputs. The unused input pin (FBCLKin/CLKin1) is connected to GND
with a 0.1 µF.
CLKin1 is the default reference clock input selected in TICS Pro. The clock input
selection mode can be programmed on the CLKins and PLLs page via the Clock
Inputs control.
CLKin1 as External Feedback Input (FBCLKin) for 0-Delay
CLKin1 is shared for use with FBCLKin as an external feedback clock input to PLL1
for 0-delay mode.
CLKin1 as Fin for external VCO or Clock Distribution mode
CLKin1 be used as an RF Input (Fin) for External VCO for PLL2 or for an input in
Clock Distribution mode.
Not Populated:
OSCin, OSCin*
Analog,
Input OSCin is the feedback clock input to PLL1 and reference clock input to PLL2. The onboard VCXO drives OSCin by default for dual loop operation.
By default the differential output of the LVPECL VCXO (U8) or the single-ended
output of the onboard VCXO (U2) drives the OSCin input of the device. When using
a single ended VCXO the OSCin* port is driven and the non-inverting OSCin input
of the device is connected to GND with 0.1 µF.
An external VCXO may be optionally attached via these SMA connectors with minor
modification to the components going to the OSCin/OSCin* pins of device. This is
useful if the VCXO footprint does not accommodate the desired VCXO device or if
the user desires to use the LMK04208 in single loop mode. It is also necessary to
connect the Vtune input of the VCXO to the CPout1.
A single-ended or differential signal may be used to drive the OSCin/OSCin* pins
and must be AC coupled. If operated in single-ended mode, the unused input must
be connected to GND with 0.1 µF.
Refer to the LMK04802 datasheet section “Electrical Characteristics” for PLL2
Reference Input (OSCin) specifications (literature number SNAS684).
Test point:
VTUNE1_TP Analog, Input Tuning voltage monitor for the loop filter for PLL1.
Test point:
VTUNE2_TP Analog, Input Tuning voltage monitor for the loop filter for PLL2.
Test points:
DATA
CLK
LE
CMOS,
Input 10-pin header for MICROWIRE™ programming interface and programmable logic
I/O pins for the LMK04208.
Populated:
uWire
10-pin header for SPI programming interface and programmable logic I/O pins for
the LMK04208.
The programmable logic I/O signals accessible through this header include: SYNC,
Status_LD, Status_Holdover, Status_CLKin0, and Status_CLKin1. These logic I/O
signals also have dedicated SMAs and test points.
Test point:
LD_TP
CMOS,
Input/Output Programmable status output pin. By default, set to output the digital lock detect status signal for PLL1 & PLL2 DLD.
In the default TICS Pro modes, LED D1 will illuminate green when PLL1 and PLL2
lock is detected by the LMK04208 (output is high) and turn off when lock is lost
(output is low).
Status_LD pin 33
The status output signal for the Status_LD pin can be selected on the User
Controls page via the LD_MUX and LD_TYPE controls.
For debugging purposes, it is suggested to set LD_MUX/Status_LD to output
PLL1 DLD and HOLDOVER_MUX/Status_Holdover to output PLL2 DLD
individually. In holdover mode PLL1 DLD will normally be low but may flicker
high momentarily.

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Table 5. Description of Evaluation Board Inputs and Outputs (continued)
CONNECTOR NAME SIGNAL TYPE,
INPUT/OUTPUT DESCRIPTION
Test point:
Holdover_TP
CMOS,
Input/Output Programmable status output pin. By default, set to output the digital lock detect status signal for PLL2.
In the default TICS Pro modes, LED D4 will illuminate red when Holdover mode is
engaged (output is high) and turn off when holdover is disengaged (output is low).
Status_Holdover pin
27
The status output signal for the Status_Holdover pin can be selected on the User
Controls page via the HOLDOVER_MUX and HOLDOVER_TYPE controls.
For debugging purposes, it is suggested to set LD_MUX/Status_LD to output
PLL1 DLD and HOLDOVER_MUX/Status_Holdover to output PLL2 DLD
individually. In holdover mode PLL1 DLD will normally be low but may flicker
high momentarily.
Test points:
CLKin0_SEL_TP
CLKin1_SEL_TP
CMOS,
Input/Output Programmable status I/O pins. By default, set as input pins for controlling input clock switching of CLKin0 and CLKin1 if Pin Select mode is enabled by
CLKin_Select_MODE.
These inputs will not be functional because CLKin_SEL_MODE is set to 0 (CLKin0
Manual) by default in the User Controls page in TICS Pro. To enable input clock
switching, CLKin_SEL_MODE must be 3 and Status_CLKinX_TYPE must be 0 to 2
(pin enabled as an input).
Input Clock Switching – Pin Select Mode
When CLKin_Select_MODE is 3 and CLKin_Sel_INV = 0, the Status_CLKinX pins
select which clock input is active as follows:
Status_CLKin1 Status_CLKin0 Active Clock
0 0 CLKin0
0 1 CLKin1
1 0 Reserved
1 1 Holdover
Test point:
SYNC_TP
CMOS,
Input/Output Programmable status I/O pin. By default, set as an input pin for synchronizing the clock outputs with a fixed and known phase relationship between each clock output
selected for SYNC. A SYNC event also causes the digital delay values to take
effect.
A physical SYNC pin transition may be emulated by toggling the SYNC_POL_INV
bit.
Populated:
SYNC
SYNC pin can hold outputs in a low state, depending on system configuration
(NO_SYNC_CLKoutX bits). SYNC_POL_INV adjusts for active low or active high
control.
A SYNC event can also be programmed by toggling the SYNC_POL_INV bit in the
User Controls page in TICS Pro.

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8 Recommended Test Equipment
Power Supply
The Power Supply should be a low noise power supply, particularly when the devices on the board are
being directly powered (onboard LDO regulators bypassed).
Phase Noise / Spectrum Analyzer
To measure phase noise and RMS jitter, an Agilent E5052 Signal Source Analyzer is recommended. An
Agilent E4445A PSA Spectrum Analyzer with the Phase Noise option is also usable although the
architecture of the E5052 is superior for phase noise measurements. At frequencies less than 100 MHz
the local oscillator noise of the E4445A is too high and measurements will reflect the E4445A’s internal
local oscillator performance, not the device under test.
Oscilloscope
To measure the output clocks for AC performance, such as rise time or fall time, propagation delay, or
skew, it is suggested to use a real-time oscilloscope with at least 1 GHz analog input bandwidth (2.5+
GHz recommended) with 50-Ωinputs and 10+ Gsps sample rate. To evaluate clock synchronization or
phase alignment between multiple clock outputs, it is recommended to use phase-matched, 50-Ωcables
to minimize external sources of skew or other errors/distortion that may be introduced if using oscilloscope
probes.

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9 Schematics
Figure 7. Power Supply

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Figure 8. LMK04208

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Figure 9. Digital

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Figure 10. Inputs

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Figure 11. Clock Outputs

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10 Bill of Materials
Table 6. LMK04208EVM BOM
Item Designator Qty Description PartNumber Manufacturer
1 !PCB 1 Printed Circuit Board SV601293 Any
2 C1, C2, C8, C9, C12,
C14, C18, C21, C23 9 CAP, CERM, 0.1uF, 16V, +/-10%, X7R, 0603 C0603C104K4RACTU Kemet
3 C1_VCO 1 CAP, CERM, 22 pF, 50 V, +/- 5%, C0G/NP0,
0603 C0603C220J5GACTU Kemet
4 C1_VCXO 1 CAP, CERM, 0.15 µF, 25 V, +80/-20%, Y5V,
0603 C0603C154Z3VACTU Kemet
5 C2_VCO 1 CAP, CERM, 0.018 µF, 100 V, +/- 10%,
X7R, 0603 C0603C183K1RACTU Kemet
6 C2_VCXO_0603 1 CAP, CERM, 1 µF, 25 V, +/- 10%, X7R,
0603 C0603C105K3RACTU Kemet
7 C3 1 CAP, CERM, 10µF, 10V, +/-20%, X5R, 0805 C0805C106M8PACTU Kemet
8 C3_VCXO, C20 2 CAP, CERM, 100pF, 50V, +/-5%, C0G/NP0,
0603 C0603C101J5GACTU Kemet
9 C4, C32, C34 3 CAP, CERM, 2200pF, 50V, +/-10%, X7R,
0603 C0603C222K5RACTU Kemet
10 C5 1 CAP, CERM, 82pF, 50V, +/-10%, C0G/NP0,
0603 C0603C820K5GACTU Kemet
11 C10, C15, C16, C19,
C30, C38, C39, C47,
C48, C49, C50, C51,
C52, C53, C54, C55,
C57, C58, C59, C60,
C63, C69, C78, C81
24 CAP, CERM, 0.1uF, 25V, +/-5%, X7R, 0603 C0603C104J3RACTU Kemet
12 C22 1 CAP, CERM, 0.1 µF, 16 V, +/- 10%, X7R,
0603 C0603C104K4RACTU Kemet
13 C31, C36 2 CAP, CERM, 2pF, 50V, +/-12.5%, C0G/NP0,
0603 C0603C209C5GACTU Kemet
14 C33 1 CAP, CERM, 1000pF, 50V, +/-5%,
C0G/NP0, 0603 C0603C102J5GACTU Kemet
15 C37, C61, C67, C73,
C86 5 CAP, CERM, 10uF, 10V, +/-10%, X5R, 0805 C0805C106K8PACTU Kemet
16 C56, C65, C72, C75 4 CAP, CERM, 0.1uF, 25V, +/-10%, X7R,
0603 C0603C104K3RACTU Kemet
17 C64, C71 2 CAP, CERM, 1uF, 10V, +/-10%, X5R, 0603 C0603C105K8PACTU Kemet
18 C83 1 CAP, CERM, 4.7uF, 10V, +/-10%, X5R,
0603 C0603C475K8PACTU Kemet
19 C84 1 CAP, CERM, 2200pF, 100V, +/-5%, X7R,
0603 06031C222JAT2A AVX
20 C85 1 CAP, CERM, 1 µF, 16 V, +/- 10%, X7R,
0603 C1608X7R1C105K080A CTDK
21 C88 1 CAP, CERM, 0.01 µF, 25 V, +/- 5%,
C0G/NP0, 0603 C0603H103J3GACTU Kemet
22 C91, C92, C94, C96 4 CAP, CERM, 0.47uF, 25V, +/-10%, X7R,
0603 GRM188R71E474KA12 DMuRata
23 CLKin0, CLKin0*,
CLKout0, CLKout0*,
CLKout1, CLKout1*,
CLKout4, CLKout4*,
CLKout5, CLKout5*,
FBCLKin*/CLKin1*,
OSCout, OSCout*,
Vcc
14 Connector, End launch SMA, 50 ohm, SMT 142-0701-806 Emerson Network
Power
24 D1 1 LED, Green, SMD SML-LX2832GC-TR Lumex
25 D2, D3, D4 3 LED, Red, SMD SML-LX2832IC-TR Lumex