Texas Instruments TPS7H2211EVM User manual

EVM User's Guide: TPS7H2211EVM TPS7H2211-SEP
TPS7H2211EVM Evaluation Module (EVM)
Description
The TPS7H2211EVM demonstrates the operation
of a single TPS7H2211 eFuse (Radiation Tolerant/
Hardened Plastic). The board provides footprints that
can be populated with additional components to allow
for testing of customized configurations, such as
parallel or redundant eFuses.
Features
• Flexible configuration options, including single-
and parallel-device circuits
• Customizable soft start, enable threshold,
undervoltage threshold, and capacitance
The EVM is populated for a single-device configuration. The footprints on the bottom half of the board can be populated if a parallel-
device configuration is desired.
TPS7H2211EVM Board
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1 Evaluation Module Overview
1.1 Introduction
The TPS7H2211EVM is the Evaluation Module (EVM) for the plastic package option of the TPS7H2211 and
provides a platform to electrically evaluate the features. This user’s guide provides details about the EVM,
including the configuration, schematics, and BOM.
The EVM is designed to be used across the entire input voltage and output current range of the TPS7H2211
while providing flexibility in configuring the device under different conditions. By default, the device in the
EVM is configured as shown in TPS7H2211EVM Default Configuration. To configure the device in a different
configuration, please refer to the TPS7H2211 data sheet to calculate the values of the passives around the
device that needs to be changed.
1.2 Kit Contents
• EVM board (1)
• EVM Kit User Guide (1)
1.3 Specification
Figure 1-1. Default Configuration Simplified Schematic
Table 1-1. TPS7H2211EVM Default Configuration
Specification Value Description
Input Voltage
VIN
12 V Falls within the recommended device input voltage range
of 4.5 V to 14 V.
Output Current
IOUT
0 to 3.5 A Does not exceed maximum device continuous current of
3.5 A per device.
EN Turn-on Voltage
VINEN_RISE
7.4 V Typical EN turn-on and turn-off values.
Set by:
R3 (RTOP_EN) = 100 kΩ
R4 (RBOT_EN) = 9.31 kΩ
EN Turn-off Voltage
VINEN_FALL
6.1 V
OVP Enter Voltage
VINOVP_RISE
13.5 V Typical OVP enter and exit values.
Set by:
R2 (RTOP_OVP) = 100 kΩ
R5 (RBOT_OVP) = 9.31 kΩ
OVP Exit Voltage
VINOVP_FALL
13.4 V
Soft Start Time
tSS
approx. 10
ms
Typical time to go from 10% to 90% of the final voltage.
Set by:
C13 (CSS) = 68 nF
More detailed information about the default EVM configuration can be found in Figure 4-1 and Table 4-1.
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1.3.1 Alternate Board Configurations
If a custom configuration is desired, then users need to refer to the TPS7H2211 data sheet to calculate the
values of the passive components around the device and note any operational requirements.
In addition to the default EVM configuration, this user's guide provides an example for how the TPS7H2211EVM
can be configured for parallel operation. The enable (EN) and overvoltage protection (OVP) specifications for the
parallel configuration are the same as what is used for the default configuration. However, this configuration is
capable of providing up to double the output current compared to the default configuration.
Table 1-2. TPS7H2211EVM Parallel Configuration
Specification Value Description
Input Voltage
VIN
13 V Falls within the recommended device input voltage range
of 4.5 to 14 V.
Output Current
IOUT
0 to 7 A Does not exceed maximum device continuous current of
3.5 A per device.
EN Turn-on Voltage
VINEN_RISE
7.4 V Typical EN turn-on and turn-off values.
Set by:
R3 (RTOP_EN) = 100 kΩ
R4 (RBOT_EN) = 9.31 kΩ
R15 populated
EN Turn-off Voltage
VINEN_FALL
6.1 V
OVP Enter Voltage
VINOVP_RISE
13.5 V Typical OVP enter and exit values.
Set by:
R2 (RTOP_OVP) = 100 kΩ
R5 (RBOT_OVP) = 9.31 kΩ
R17 populated
OVP Exit Voltage
VINOVP_FALL
13.4 V
Soft Start Time
tSS
approx. 10.9
ms
Typical time to go from 10% to 90% of the final voltage.
Set by:
C13 (CSS) = 68 nF
C28 (CSS) = 68 nF
R16 populated
More detailed information about the parallel EVM configuration can be found in Figure 4-2 and Table 4-2.
1.4 Device Information
The TPS7H2211 is a single-channel eFuse that provides reverse current protection, overvoltage protection, and
a configurable rise time to minimize inrush current (soft start). The device contains P-channel MOSFETs that
operate over an input voltage range of 4.5 V to 14 V and supports a maximum continuous current of 3.5 A. The
device is controlled by an on and off input (EN), that is capable of interfacing directly with low-voltage control
signals. Overvoltage protection and soft start are programmable with few external components through the OVP
and SS pins.
• Data sheet: TPS7H2211-SP and TPS7H2211-SEP Radiation-Hardness-Assured (RHA) 14-V, 3.5-A eFuse
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2 Hardware
2.1 EVM Connectors and Test Points
Figure 2-1. TPS7H2211EVM 3D Rendering (Top)
Table 2-1. Summary of Connectors and Test Points
Reference Designator Function
J3, J5 (pins 3 & 4) VIN1
Input Voltage and Current for U1
J8, J5 (pins 1 & 2) GND
J12, J14 (pins 1 & 2) VIN2
Input Voltage and Current for U2
J17, J14 (pins 3 & 4) GND
J4, J13, J6 (pins 3 & 4), J15 (pins 3 & 4) VOUT
Output Voltage and Current for Board
J9, J18, J6 (pins 1 & 2), J15 (pins 1 & 2) GND
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Table 2-1. Summary of Connectors and Test Points (continued)
Reference Designator Function
J1, TP1, TP2 VIN1
Test Point
J10, TP12, TP13 VIN2
J2, J11, TP3, TP4, TP14, TP15 VOUT
TP5, TP6, TP10, TP11, TP16, TP17,
TP21, TP22
GND
TP8 SS1
TP19 SS2
TP7 EN1
TP18 EN2
TP9 OVP1
TP20 OVP2
J7 VIN1-EN1-GND
Shunt for mode selection
J16 VIN2-EN2-GND
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3 Implementation Results
Test results are shown for both the default configuration and the parallel configuration shown in this document.
For each configuration, the following tests were performed:
1. Startup
2. Shutdown
3. OVP Assertion
4. OVP Deassertion
3.1 Default Configuration Results
The results shown in Figure 3-1 through Figure 3-4 were observed using the TPS7H2211EVM in the default
configuration with VIN = 12 V.
Figure 3-1. Default Configuration: Start Up
Figure 3-2. Default Configuration: Shutdown
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Figure 3-3. Default Configuration: Assertion of OVP Due to Input Voltage
Figure 3-4. Default Configuration: Deassertion of OVP Due to Input Voltage
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3.2 Parallel Configuration Results
The results shown in Figure 3-5 through Figure 3-8 were observed using the TPS7H2211EVM in the parallel
configuration shown in this document with VIN = 13 V.
Figure 3-5. Parallel Configuration: Start Up
Figure 3-6. Parallel Configuration: Shutdown
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Figure 3-7. Parallel Configuration: Assertion of OVP due to Input Voltage
Figure 3-8. Parallel Configuration: Deassertion of OVP due to Input Voltage
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4 Hardware Design Files
4.1 Schematic
Figure 4-1 shows the default TPS7H2211EVM schematic. Figure 4-2 is the schematic for the parallel configuration of the EVM shown in this document.
J3
GND GND
J4
0.1uF
C6
1
2 3 4 5
J1
GND
10uF
C5
GND
TP9
1
2 3 4 5
J2
0.1uF
C21
10uF
C20
J13
1
2 3 4
5
J11
VOUT
VOUT
J12
GND
1
2 3 4
5
J10
1
2
3
J7
SH-J1
GND
EN_1 SS_1
EN_1
EN_2
SS_1
SS_2
TP18
GND
TP20
1
2
3
J16
SH-J2
EN_2 SS_2
GND
GND GND
0
R7
0
R6
0
R8
0
R9
0.1uF
C12
10uF
C11
0.1uF
C27
10uF
C26
0
R15
0
R17
0
R16
(4.5V-14V)
(4.5V-14V)
0.1uF
C14
0.1uF
C15
0.1uF
C29
0.1uF
C30
1
2
3
4
J14
1
2
3
4
J5
10.0k
R1
10.0k
R10
150uF
C7
150uF
C8
150uF
C9 150uF
C1
150uF
C2
150uF
C3
150uF
C22
150uF
C23
150uF
C24 150uF
C16
150uF
C17
150uF
C18
10uF
C10 10uF
C4
10uF
C19
10uF
C25
68nF
C13
68nF
C28
TP5 TP6
TP17TP16
TP4TP3TP2TP1
TP8
TP19
TP12 TP13 TP14 TP15
TP7
OVP_1OVP_1
TP11
TP10
TP22
TP21
OVP_2
OVP_2
OVP_2
OVP_1
100k
R2
9.31k
R4
9.31k
R5
100k
R11
9.31k
R14
9.31k
R13
J8
J18
J9
J17
1
2
3
4
J15
1
2
3
4
J6
100k
R3
100k
R12
VIN
1
VIN
2
VIN
3
VIN
4
VIN
5
VIN
6
VIN
7
VIN
8
VIN
9
VIN
10
VOUT 23
VOUT 24
VOUT 25
VOUT 26
VOUT 27
VOUT 28
VOUT 29
VOUT 30
VOUT 31
VOUT 32
EN
12
OVP
13
SS 22
Therma l_Pa d 33
NC
11
NC
14
NC
16
NC
17
NC
18
NC
19
NC
20
NC
21
GND 15
TPS7H2211MDAPTSEP
U1
GND
VIN
1
VIN
2
VIN
3
VIN
4
VIN
5
VIN
6
VIN
7
VIN
8
VIN
9
VIN
10
VOUT 23
VOUT 24
VOUT 25
VOUT 26
VOUT 27
VOUT 28
VOUT 29
VOUT 30
VOUT 31
VOUT 32
EN
12
OVP
13
SS 22
Therma l_Pa d 33
NC
11
NC
14
NC
16
NC
17
NC
18
NC
19
NC
20
NC
21
GND 15
TPS7H2211MDAPTSEP
U2
GND
VIN1
VIN2
Figure 4-1. TPS7H2211EVM Default Schematic
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