Texas Instruments SLAU039 User manual

Evaluation Board for the
TLC320AD50C DSP Analog
Interface Circuit
2000 Mixed Signal Products
User’s Guide
SLAU039

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Copyright 2000, Texas Instruments Incorporated

Notational Conventions
iii
Read This First
Preface
Read This First
About This Manual
This user’s guide discusses the design, use, and performance of the
TLC320AD50 Evaluation Module.
How to Use This Manual
This document contains the following chapters:
- Chapter 1 – Introduction
- Chapter 2 – AD50-EVM Design and Construction
- Chapter 3 – Setting Up the AD50-EVM
- Chapter 4 – Results Obtained With AD50 EVM
- Appendix A –Installing the AD50-EVM
- Appendix B –Programmable Logic
- Appendix C –Converting DSK+ Software for the AD50-EVM
Notational Conventions
This document uses the following conventions.
- Program listings, program examples, and interactive displays are shown
in a special typeface similar to a typewriter’s. Examples use a bold
version of the special typeface for emphasis; interactive displays use a
bold version ofthe special typeface to distinguish commands that you
enter from items that the system displays (such as prompts, command
output, error messages, etc.).
Here is a sample program listing:
0011 0005 0001 .field 1, 2
0012 0005 0003 .field 3, 4
0013 0005 0006 .field 6, 3
0014 0006 .even

Running Title—Attribute Reference
iv
Here is an example of a system prompt and a command that you might
enter:
C: csr –a /user/ti/simuboard/utilities
- In syntax descriptions, the instruction, command, or directive is in a bold
typefacefontandparametersareinan italictypeface .Portionsofasyntax
that are in bold should be entered as shown; portions of a syntax that are
in
italics describe the type of information that should be entered. Here is
an example of a directive syntax:
.asect ” section name ”, address
.asectisthedirective.Thisdirectivehastwoparameters,indicatedby sec-
tionname
and address .Whenyou use .asect, thefirstparameter must be
anactualsectionname,enclosedindoublequotes;thesecondparameter
must be an address.
- Square brackets ( [and ]) identify an optional parameter. If you use an
optional parameter, you specify the information within the brackets; you
don’t enter the brackets themselves. Here’s an example of an instruction
that has an optional parameter:
LALK 16–bit constant [, shift]
TheLALKinstruction hastwoparameters.Thefirstparameter, 16-bitcon-
stant , is required. The second parameter, shift , is optional. As this syntax
shows,ifyou usetheoptionalsecondparameter, youmustprecedeitwith
a comma.
Square brackets are also used as part of the pathname specification for
VMS pathnames; in this case, the brackets are actually part of the path-
name (they are not optional).
- Braces( {and} )indicatealist.Thesymbol|(readas or )separatesitems
within the list. Here’s an example of a list:
{ * | *+ | *– }
This provides three choices: *, *+, or *–.
Unless the list is enclosed in square brackets, you must choose one item
from the list.
- Some directives can have a varying number of parameters. For example,
the .byte directive can have up to 100 parameters. The syntax for this di-
rective is:
.byte
value
1
[, ... , value
n
]
This syntax shows that .byte must have at least one value parameter, but
you have the option of supplying additional value parameters, separated
by commas.

Related Documentation From Texas Instruments
v
Read This First
Related Documentation From Texas Instruments
TLC320AD50C Data Manual, Literature number SLAS131
Data Acquisition Data Book, Literature number SLAD001
Data Converter Selection Guide, Literature number SLABE05
Operational Amplifiers Data Book Volume A, Literature number SLYD011
Operational Amplifiers Data Book Volume B, Literature number SLYD012
Rail-to-Rail Operational Amplifier Selection Guide,
Literature number SLOBE02
Single Supply Operational Amplifier Selection Guide,
Literature number SLOBE03
Mixed Signal Analog CD-ROM, Literature number SLYC005
TMS320C54x CPU and Peripherals, Literature number SPRU131
TMS320C54x Algebraic Instruction Set, Literature number SPRU179
TMS320C54x DSKplus User’s Guide, Literature number SPRU191
Much useful software is available from the TI Internet site. The main TI Web
site is at
http://www.ti.com/
Information on the DSK+ is at
http://www.ti.com/sc/docs/dsps/tools/c54x/c54xdskp.htm
DSK+ software can be downloaded from
http://www.ti.com/sc/docs/dsps/tools/c54x/softsupp.htm

vi

Running Title—Attribute Reference
vii
Chapter Title—Attribute Reference
Contents
1 Introduction 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Scope of User’s Guide 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Block Diagram of AD50-EVM 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Special Considerations When Using Sigma-Delta Converters 1-4. . . . . . . . . . . . . . . . . . . . .
1.3.1 Advantages 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.2 Disadvantages 1-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 AD50-EVM Design and Construction 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 PCB Construction 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Power Supply 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 System Clock 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Reset 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 Serial Port Interfacing 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6 Analog Input 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.1 Preamp Design 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.2 Input Stage Design 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.3 Op Amp Selection 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.4 Antialiasing Filter 2-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7 Analog Output 2-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Setting Up the AD50-EVM 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Setting Up the AD50-EVM With the DSK+ 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Setting Up the AD50-EVM in Stand-Alone Mode 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Configuring the Serial Interface 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 Programming the AD50 Registers 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5 Sine-Wave Generator and Loopback Program 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Results Obtained With AD50 EVM 4-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 ADC Results 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 DAC Results 4-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A Installing the AD50-EVM A-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.1 Board Outline Drawing With Jumper Locations on the AD50 EVM A-2. . . . . . . . . . . . . . . . .
A.2 Connecting the AD50-EVM to the DSK+ A-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.3 Parts List A-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.4 Circuit Diagrams A-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.5 PCB Diagrams A-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Running Title—Attribute Reference
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B Programmable Logic B-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B.1 DSK+ Mode B-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B.2 Stand-Alone Mode B-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B.3 Logic Compiler Listing B-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C Converting DSK+ Software for the AD50-EVM C-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Running Title—Attribute Reference
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Contents
Figures
1–1 AD50-EVM Block Diagram 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–3 AD50-EVM Input Stage 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–4 AD50-EVM Antialiasing Filter Options 2-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–5 AD50-EVM Differential to Single-Ended Output Converter 2-9. . . . . . . . . . . . . . . . . . . . . . . . . .
4–1 AD50-EVM ADC Distortion Measurement at 8 ksps 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–2 AD50-EVM ADC Distortion Measurement at 20 ksps 4-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–3 AD50-EVM DAC Distortion Measurement at 8 ksps 4-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–4 AD50-EVM DAC Distortion Measurement at 20 ksps 4-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–1 Diagram of the AD50-EVM A-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Running Title—Attribute Reference
x
Tables
2–1 Sampling Frequencies for Various MCLK and Register 4 Values 2-4. . . . . . . . . . . . . . . . . . . . .
A–1 Jumper Positions A-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–2 Control and Serial Connections A-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–3 Analog Input/Output Connectors A-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B–1 AD50-EVM Registers B-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-1
Introduction
Introduction
Thisuser’sguidediscussesthedesignoftheAD50-EVMevaluationboardand
its use to demonstrate the performance of the TLC320AD50C (AD50) analog
interface circuit.
The TLC320AD50C provides high-resolution low-speed signal conversion
from digital-to-analog (D/A) and from analog-to-digital (A/D) using oversam-
pling sigma-delta technology. This device consists of two serial synchronous
conversion paths (one for each data direction) and includes an interpolation
filter before the DAC and a decimation filter after the ADC. Other overhead
functionsprovideon-chiptimingandcontrol.Thesigma-deltaarchitecturepro-
duceshigh-resolutionanalog-to-digitalanddigital-to-analogconversionatlow
system speeds and low cost.
The options and the circuit configurations of this device can be programmed
through the serial interface. The options include reset, power down, commu-
nicationsprotocol,serialclockrate,signalsamplingrate,gaincontrol,andtest
mode.
Topic Page
1.1 Scope of User’s Guide 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Block Diagram of AD50-EVM 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Special Considerations When Using Sigma-Delta Converters 1-4. . . . .
Chapter 1

Scope of User’s Guide
1-2
The TLC320AD50 is an analog interface circuit (AIC) with many features that
make it suitable for DSP-based applications
- Single 5-V supply or dual (5-V analog and 3.3-V digital) supplies
- 16-bit resolution sigma-delta ADC and DAC
- 85 dB (min) signal to noise
- Inherent antialiasing filtering and sin(x)/x compensation
- High input impedance
- Supports up to 4 devices on one serial interface
- Low operating power (175 mW max)
- Power down mode ( 20 mW max )
- Small package size
1.1 Scope of User’s Guide
ThisapplicationnotediscussesthedesignoftheAD50-EVMevaluationboard
and its use to demonstrate the performance of the TLC320AD50C (AD50)
analoginterfacecircuit.Theresultscomefrommeasurementsonasmallnum-
ber of samples. For specifications refer to the datasheet.
TheAD50-EVMhastwoAD50devicesforstereooperation.TwoAD50-EVMs
canbeconfiguredasafour-channelsystemusingasingleserialinterface.The
AD50-EVMcanbeinterfaceddirectlytotheDSK+DSPstarterkitorothersys-
tems which have a compatible synchronous serial interface.
The objective was to design a development board (the AD50-EVM) which
would allow prospective users of the AD50 to determine its capabilities with
a minimum effort. The board can be directly connected to the low cost
TMS320C54xDSPstarterkit(DSK+),ortoanyothersystemwithacompatible
synchronous serial interface. Directly compatible DSP devices include
TMS320C2x, C2xx, C3x, C5x, C54x and C6xxx.
An example program for the DSK+ development system allows the board to
be used as a sine-wave generator, or to output on the DAC samples read in
from the ADC. In this echo mode signal processing functions such as filtering
can easily be included. The AD50-EVM board was also interfaced to a
TMS320C25 development board, which was used to transfer analog data to
a personal computer running real-time FFT spectrum analysis software. This
system was used to prepare the ADC and DAC FFT spectrograms shown in
this user’s guide.

Block Diagram of AD50-EVM
1-3
Introduction
1.2 Block Diagram of AD50-EVM
Figure 1–1 shows the block diagram of the AD50-EVM evaluation
board.
Figure 1–1.AD50-EVM Block Diagram
Preamp Level Shift and
Differential
Conversion
Antialiasing
Filter
Preamp Level Shift and
Differential
Conversion
Antialiasing
Filter
Low Pass
Filter
Single Ended
Conversion
Low Pass
Filter
TLC320AD50C
AIC
Serial Interface
Powerdown
FC
Oscillator
AIC
TLC320AD50C
Serial Interface
Powerdown
FC
Programmable
Logic
Audio In
Audio Out
DSP Bus
Audio Out
Audio In
Single Ended
Conversion
The input signal is first buffered and optionally amplified by the preamp stage
before being level-shifted and converted to a differential pair of signals. The
externalantialiasingfilterisasimplecontinuoustimefiltertoremoveRFnoise.
The output from the codec is converted to a single ended signal and is filtered
to remove high frequency noise.
A negative power supply is generated on the AD50-EVM to allow for dc
coupledinputandoutputsignals. The clocksignalforthecodeccanbe gener-
ated by an oscillator on the board or from an external clock. The sampling fre-
quency is set using the programmable clock divider within the AD50. The
AD50 FC, RESET, and POWERDOWN signals can be controlled via a soft-
ware programmable register.

Special Considerations When Using Sigma-Delta Converters
1-4
1.3 Special Considerations When Using Sigma-Delta Converters
Sigma-delta analog-to-digital converters typically consist of an analog modu-
lator (fourth order in the case of the AD50) followed by a digital filter section.
The modulator contains a 1-bit ADC (a comparator) which produces a 1-bit
wide data stream, which is applied to the input of the digital filter. It is also ap-
plied to the input of a 1-bit DAC, the output of which is fed back to the input of
the modulator. The 1-bit ADC is clocked much faster than the desired output
samplingfrequency(FS),(64×FSfortheAD50)andthelargeamountofquan-
tizationnoisegeneratedisuniformlyspreadoverawiderangeoffrequencies.
A noise-shaping filter within the analog modulator reduces the noise in the
pass-band, increasing it elsewhere. A low-pass digital filter then removes the
unwantedhighfrequencyquantizationnoiseandthesignalisresampledatthe
desired output frequency.
Thesigma-delta DAC in the AD50 consists of a digital interpolating filter oper-
ating at 256 ×FSfollowed by a 1-bit DAC and a second-order modulator. The
digital filter removes most of the image frequencies, that would otherwise be
presentattheoutputofaconventionalDAC.Thisavoidstheneedforahigh-or-
der analog low-pass reconstruction filter. Separate sin(x)/x compensation is
not needed, as this is inherent in the DAC architecture.
Sigma-delta converters have several advantages and a few disadvantages
relative to other types of ADC which are summarized below.
1.3.1 Advantages
- Sigma-delta conversion is inherently linear because there is no reference
resistorchainasinflashorsuccessive approximation converters. Thisre-
sults in extremely low distortion.
- Inherent monotonicity
- No missing codes
- Antialias filtering is inherent within sigma-delta converters. This greatly
simplifies their application, because only a simple external RC filter is re-
quired at the input of the ADC to achieve the necessary alias rejection.
- ThedigitalfilterswhichformanintegralpartoftheADCandDACareusu-
allyofthefiniteimpulseresponsetype,whichgivesalinearphasecharac-
teristic with high stability.
- Thecutofffrequencyofthedigitalfiltersautomatically tracks the sampling
rate.
- DACanti-imagefilteringisgreatlysimplified because an internal digitalfil-
ter attenuates image frequencies. A simple analog filter is sufficient to re-
move HF noise.
- No need for sin(x)/x compensation.
- Thesigma-deltaarchitectureiscompatiblewithdense,low-cost,digitalIC
processes.

Special Considerations When Using Sigma-Delta Converters
1-5
Introduction
1.3.2 Disadvantages
- The digital filters in sigma-delta converters introduce into the conversion
processatimedelaythatmakesthemunsuitableforsomecontrolapplica-
tions. The AD50 ADC has a delay of 17 samples and the DAC has an 18
sample delay.
- It is not practical to multiplex several inputs to a single sigma-delta ADC
exceptatverylowrates,becauseeachchannelwouldbecorruptedbythe
earlier samples from other channels still propagating through the digital
filter. Although the AD50 has an input multiplexer, this is only for selecting
oneoranotherinput,notfor interleaving twoinputchannelsontoonedata
stream.
- Audio band converters are optimized for ac signals and a small dc offset
may be present.
- Spurious low level tones can sometimes occur at very low input signal
levels, especially if clock signals at Fs/2 are allowed to couple into the
reference voltage pins. Such tones can be identified because their
frequency is affected by small changes in dc offset.

1-6

2-1
AD50-EVM Design and Construction
AD50-EVM Design and Construction
This chapter discusses the printed-circuit board design considerations for the
AD50-EVM.
Topic Page
2.1 PCB Construction 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Power Supply 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 System Clock 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Reset 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 Serial Port Interfacing 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6 Analog Input 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7 Analog Output 2-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 2

PCB Construction
2-2
2.1 PCB Construction
The AD50-EVM printed-circuit board is constructed of 4 layers, with ground
and power planes sandwiched between the top and bottom signal-carrying
layers. This minimizes the coupling of RF noise into the system by providing
very low impedance to power and ground, and by shielding signal tracks. The
AD50isavailableintwosurface-mountpackages,theDWandPT.ThePThas
a smaller footprint size and is much thinner (only 1.6 mm high). It has 48 pins
at a pitch of 0.5 mm, making it very suitable for PCMCIA and other miniature
applications.Howeveritisdifficultto handsolder,andforprototype evaluation
the use of the DW package is recommended. This package has 28 pins at a
pitchof1.27mm(0.05inch)andsoismucheasiertohandle.Surface-mounted
components were used except for the connectors, which through-hole con-
nectors offering robustness.
Theprinted-circuitboardisthesamesizeastheDSK+board.TheAD50-EVM
and the DSK+ can be stacked one above the other using inter-board links. Ei-
therboardcanbeontop,butplacingtheAD50-EVMontopgivesbetteraccess
to the EVM test points.
A separate connector has been provided for interfacing to systems other than
the DSK+. This brings out the SCLK, FS, DIN, DOUT, and RESET signals.
Eachsignalisinterleavedwithagroundconductorintheribboncable,allowing
a longer cable length without crosstalk. Nevertheless, this cable should be as
shortas reasonably possible, since ringing in the unterminated cable may be-
comeexcessiveforlengthsgreaterthan3feet.TominimizeRFemissions,the
cableshouldbeshielded, with the shield connected tothegroundplane at the
groundpointprovidedadjacenttopins1and2oftheconnector.Thisconnector
must not be used simultaneously with the connections around the edge of the
AD50-EVM board that are specifically intended for the DSK+.
For the best signal-to-noise ratio, it is often recommended that the
ground plane be split into separate analog and digital sections, joined
together in only one place with the split passing under the AD50 pack-
agebetweenitsanaloganddigitalgroundpins.Thesplitpreventsdigi-
tal noise currents from inducing noise voltages in the analog ground of
the device. The DSK+ has ground and power pins along both edges of
the board, making the use of split ground planes ineffective. Instead
shortbreaks were inserted on theground plane to separate theanalog
and digital grounds and reduce the common impedance

Power Supply
2-3
AD50-EVM Design and Construction
2.2 Power Supply
The AD50-EVM board requires only +5 Vdc; a –5-Vdc supply for some of the
op-ampsis generated on the board using aCMOS 7660 charge pump phase-
lockedtotheframesyncoutputoftheAD50.Phase-locking minimizestherisk
ofaudiblebeats betweenthesamplingclockandthe7660clock.The OSCpin
of the 7660 is coupled to the master FSD with a 22 pF capacitor. This method
allows the 7660 oscillator to free-run when there is no frame sync, ensuring
that the negative power is always maintained, even when the AD50 is held in
reset.The7660dividesthesignalontheOSCpinby2internally,ensuringthat
thechargepumpoperatesata50%dutycycle,evenwithagrosslyasymmetric
input such as that provided by frame sync. Not all negative supply generators
contain a divider. Check before using any other type.
ThedigitalpartoftheAD50canbeoperatedat 3.3V. Users wishing to investi-
gate this should remove R16 and R36 and connect 3.3 V power to L_VD and
R_VD.
2.3 System Clock
When the AD50-EVM is used in standalone mode, in conjunction with a
separateDSPsystem,acrystaloscillatormustbefittedtothesocketprovided.
A frequency of 10.24 MHz is suggested, as this will allow standard sampling
frequencies such as 10, 16, and 20 kHz to be achieved by programming the
AD50 clock divider and phase-locked loop. Table 2–1 shows the sampling
frequencies that can be selected for a number of master clock frequencies.
Frequencies shown in brackets are above the maximum sampling frequency
specified for the AD50.
In standalone mode the AD50-EVM can be clocked at frequencies up to
22.579 MHz. However, when used in conjunction with the DSK+ the upper
frequency is limited by the maximum clock rate of the TMS320C542 DSP
device. The 10.24 MHz oscillator supplied with the AD50-EVM will drive the
TMS320C542ontheDSK+at40.96MHz,whichisonly slightly higher than its
maximum operating frequency of 40.00 MHz. However, at room temperature
this should not cause any problems, because the TMS320C542 is tested by
TI at 40.00 MHz over the temperature range 0-70 _ C. The authors have
successfully operated a DSK+ in conjunction with an AD50-EVM at MCLK
frequenciesfrom4MHzto13MHzatroomtemperature,butthismaynotwork
with all DSK+ units. Alternatively, the DSK+ and AD50-EVM clocks can be
separatedbyremovingresistorR80 from theAD50-EVMboardandasuitable
oscillatorinstalledoneachboard.(Ifthismodificationismade,3and4channel
modes will not work correctly because all the AD50s must have an identical
MCLK.RemovingR80preventsthe clock from being transmittedbetweenthe
boards.)
It is important to ensure that only one oscillator is used in the system (except
as described above), otherwise results will be unpredictable. No damage will
be caused, however, as current limiting resistors are provided on the output
of each oscillator. Electrically it makes no difference whether the oscillator is
fitted to the DSK+, or to the first or second AD50-EVM board.

Reset
2-4
Table 2–1.Sampling Frequencies for Various MCLK and Register 4 Values
Reg 4, Bit 7 Reg 4, Bits 6–4 8.192 MHz 10.000 MHz 10.240 MHz 11.2896 MHz
0 (default) 8 kHz 9.765 kHz 10 kHz 11.025 kHz
1(64 kHz) (78.125 kHz) (80 kHz) (88.2 kHz)
2(32 kHz) (39.063kHz) (40 kHz) (44.1 kHz)
bit 7 = 0 321.333 kHz (26.042 kHz) (26.666 kHz) (29.4 kHz)
PLL on 416 kHz 19.531 kHz 20 kHz 22.05 kHz
512.8 kHz 15.625 kHz 16 kHz 17.64 kHz
610.666 kHz 13.021 kHz 13.333 kHz 14.7 kHz
79.1432 kHz 11.161 kHz 11.429 kHz 12.601 kHz
02 kHz 2.441 kHz 2.500 kHz 2.756 kHz
116 kHz 19.531 kHz 20 kHz 22.05 kHz
28 kHz 9.766 kHz 10 kHz 11.025 kHz
bit 7 = 1 35.333 kHz 6.510 kHz 6.666 kHz 7.35 kHz
PLL off 44 kHz 4.883 kHz 5 kHz 5.513 kHz
53.2 kHz 3.906 kHz 4 kHz 4.41 kHz
62.666 kHz 3.255 kHz 3.333 kHz 3.675 kHz
70.798 kHz 2.79 kHz 2.857 kHz 3.15 kHz
2.4 Reset
Inalloperatingmodes the AD50-EVM is resetwhenthepower is switched on.
InDSK+modeitisalsoresetwhentheDSK+itselfisreset.Theprogrammable
logic on the AD50-EVM is configured so that in the reset state all the AD50s
are powered down and in slave mode and that the AC01 on the DSK+ is pow-
eredupasnormal.ThismeansthatevenwithoneortwoAD50-EVMsattached
to a DSK+ system, all the DSK+ demonstration software works normally with
the AC01 AIC.
To use one or more AD50s it is necessary to program bits 0-3 of I/O address
0. Bit 0 controls the reset state of the AD50s. Bit 0 = 0 resets all AD50s and
bit0 = 1 allowsthem to run. Bits 1, 2, and3 are encoded tocontrol the number
of AD50s that are powered up (see Table B–1 for details). Note that no provi-
sion has been made to operate the AD50s and the AC01 together. This is be-
cause their control registers are incompatible and it would be difficult to pre-
vent bus conflicts on the serial interface.
Theresetpinsareconnectedtoboththe SERIAL and CONTROL cable head-
ers for use in standalone mode (see Table A–2 for pinouts).