Texas Instruments ADS131M04 User manual

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ADS131M04 Evaluation Module
User's Guide
SBAU332A–March 2019–Revised June 2019
ADS131M04 Evaluation Module
This user's guide describes the characteristics, operation, and use of the ADS131M04 evaluation module
(EVM). This kit is an evaluation platform for the ADS131M04, which is a 4-channel, simultaneously-
sampling, 24-bit, delta-sigma (ΔΣ) analog-to-digital converter (ADC). The ADS131M04 offers wide
dynamic range and internal calibration features, making the device excellent for energy metering, power
quality, protection relay, and circuit breaker applications.
The ADS131M04EVM eases the evaluation of the device with hardware, software, and computer
connectivity through the universal serial bus (USB) interface. This user's guide includes complete circuit
descriptions, schematic diagrams, and a bill of materials. Throughout this document, the abbreviation EVM
and the term evaluation module are synonymous with the ADS131M04EVM. The following related
documents are available through the Texas Instruments web site at www.ti.com.
Table 1. Related Documentation
Device Literature Number
ADS131M04 SBAS890

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Contents
1 EVM Overview ............................................................................................................... 4
2 EVM Analog Interface....................................................................................................... 5
3 Digital Interface .............................................................................................................. 8
4 Power Supplies............................................................................................................. 10
5 ADS131M04EVM Initial Setup............................................................................................ 11
6 ADS131M04EVM Operation.............................................................................................. 14
7 ADS131M04EVM Bill of Materials, PCB Layout, and Schematic.................................................... 21
List of Figures
1 System Connection for Evaluation ........................................................................................ 4
2 Input Terminal Blocks and Headers (Schematic)........................................................................ 5
3 Input Terminal Blocks and Headers (PCB)............................................................................... 6
4 CLKIN External Clock (PCB)............................................................................................... 7
5 ADS131M04EVM Jumper Default Settings............................................................................. 11
6 ADS131M04 Software Installation Prompts ............................................................................ 12
7 Device Driver Installation Wizard Prompts.............................................................................. 12
8 LabVIEW Run-Time Engine Installation................................................................................. 13
9 ADS131M04EVM GUI Folder Post-Installation......................................................................... 14
10 ADS131M04EVM Hardware Setup and LED Indicators .............................................................. 14
11 Launch the EVM GUI Software........................................................................................... 15
12 EVM GUI Global Input Parameters...................................................................................... 16
13 Register Map Configuration............................................................................................... 17
14 Time Domain Display Tool Options...................................................................................... 18
15 Spectral Analysis Tool..................................................................................................... 19
16 Histogram Analysis Tool .................................................................................................. 20
17 Top Silkscreen.............................................................................................................. 24
18 Top Layer ................................................................................................................... 24
19 Ground Layer 1............................................................................................................. 24
20 Ground Layer 2............................................................................................................. 25
21 Bottom Layer................................................................................................................ 25
22 Bottom Silkscreen.......................................................................................................... 25
23 ADS131M04EVM Hardware Schematic................................................................................. 26
24 ADS131M04EVM Main Schematic....................................................................................... 27
List of Tables
1 Related Documentation..................................................................................................... 1
2 Analog Input Terminal Blocks, J1–J4 ..................................................................................... 6
3 Analog Input Jumper Connection, JP1–JP4 ............................................................................. 7
4 CLKIN External Clock Options............................................................................................. 7
5 PHI Connector Pin Functions .............................................................................................. 8
6 Digital Header Pins.......................................................................................................... 9
7 LaunchPad™ Pin Functions................................................................................................ 9
8 Default Settings............................................................................................................. 11
9 ADS131M04EVM Bill of Materials ....................................................................................... 21

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Trademarks
LaunchPad, BoosterPack are trademarks of Texas Instruments.
Windows is a registered trademark of Microsoft.
LabVIEW is a trademark of National Instruments.
All other trademarks are the property of their respective owners.

PHI Board
A-to-Micro-B USB
Cable
ADS131M04EVM
Included in kit
Signal
Source
ADS131M04
EVM GUI
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1 EVM Overview
The ADS131M04EVM is a platform for evaluating the performance of the ADS131M04, which is a 4-
channel, simultaneously-sampling, 24-bit, ΔΣ ADC. The evaluation kit includes the ADS131M04EVM
board and the precision host interface (PHI) controller board that enables the accompanying computer
software to communicate with the ADC over the USB for data capture and analysis.
The ADS131M04EVM board includes the ADS131M04 ADC and all the peripheral analog circuits and
components required to extract optimum performance from the ADC.
The PHI board primarily serves three functions:
• Provides a communication interface from the EVM to the computer through a USB port
• Provides the digital input and output signals necessary to communicate with the ADS131M04
• Supplies power to all active circuitry on the ADS131M04EVM board
1.1 ADS131M04EVM Kit
The ADS131M04 evaluation module kit includes the following features:
• Hardware and software required for diagnostic testing as well as accurate performance evaluation of
the ADS131M04 ADC
• USB powered—no external power supply is required
• The PHI controller that provides a convenient communication interface to the ADS131M04 ADC over
USB 2.0 (or higher) for power delivery as well as digital input and output
• Easy-to-use evaluation software for 64-bit Microsoft Windows®7, Windows 8, and Windows 10
operating systems
• The software suite includes graphical tools for data capture, histogram analysis, and spectral analysis.
This suite also has a provision for exporting data to a text file for post-processing.
Figure 1 illustrates an example system setup for evaluation.
Figure 1. System Connection for Evaluation
1.2 ADS131M04EVM Board
The ADS131M04EVM board includes the following features:
• External signal source from differential pair headers
• Options to use external analog and digital power supplies
• Serial interface header for easy connection to the PHI controller
• Pin connections to monitor digital signals with a logic analyzer
• Onboard ultra-low noise low-dropout (LDO) regulator for excellent 3.3-V, single-supply regulation of all
analog circuits

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2 EVM Analog Interface
The ADS131M04EVM is designed for easy interfacing with analog sources. This section covers the details
of the front-end circuit including jumper configuration for different input test signals and board connectors
for signal sources.
2.1 ADC Analog Input Signal Path
Analog inputs to the EVM can be connected to either the terminal blocks or to the header pins associated
with each ADC channel. The 3x2 100-mil headers for each channel allow the user to configure the inputs
differentially depending on the signal to be measured. The screw terminal blocks can interface directly
with the leads of an external sensor input. Figure 2 shows the signal chain used for all four input channels
on the EVM and is used to describe the supported input options in Figure 3,Table 2, and Table 3.
External voltage inputs can be applied to J1 pins 1 and 3. For single-ended inputs, install a jumper on
either JP1[1-2] or JP1[5-6] to connect an input to the EVM ground. If the external voltage is applied
through a series resistor, R1 or R2 can be used to form a resistor divider by installing JP1[3-4] to support
higher voltage measurements. Input jumper connections are described in Table 2. Similarly, R17 and R18
can be installed to form a resistor divider with the series 49.9-Ωresistors on each input. An input must not
be applied such that the voltage on the input pins of the ADS131M04 exceeds the absolute maximum
ratings. See the ADS131M04 data sheet for details.
R1 and R2 also present a 2-kΩdifferential load when all jumpers on JP1 are uninstalled. This load acts as
a burden resistor for a current transformer (CT) input. For single-ended measurements, the unused end of
the transformer secondary side can be tied to ground by installing the appropriate jumper on JP1.
R9, R10, and C9 form a differential low-pass filter with a –3-dB cutoff frequency of 1.594 MHz. The series
impedance is kept relatively low in order to maintain adequate total harmonic distortion (THD)
performance.
Figure 2. Input Terminal Blocks and Headers (Schematic)

J1
Pin 1
Pin 2
Pin 3
J2
Pin 1
Pin 2
Pin 3
J3
Pin 1
Pin 2
Pin 3
J4
Pin 1
Pin 2
Pin 3
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Figure 3. Input Terminal Blocks and Headers (PCB)
Table 2. Analog Input Terminal Blocks, J1–J4
Terminal Block Pin Function ADS131M04 Input Pin
J1 1 Channel 0 positive input AIN0P 2 EVM ground AGND and DGND
3 Channel 0 negative input AIN0N
J2 1 Channel 1 positive input AIN1P 2 EVM ground AGND and DGND
3 Channel 1 negative input AIN1N
J3 1 Channel 2 positive input AIN2P 2 EVM ground AGND and DGND
3 Channel 2 negative input AIN2N
J4 1 Channel 3 positive input AIN3P 2 EVM ground AGND and DGND
3 Channel 3 negative input AIN3N

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Table 3. Analog Input Jumper Connection, JP1–JP4
Jumper Position Description
JP1
Connection for channel 0 analog inputs
[1-2] Short positive input to ground
[3-4] Connect both inputs to ground via 1-kΩresistors (default)
[5-6] Short negative input to ground
JP2
Connection for channel 1 analog inputs
[1-2] Short positive input to ground
[3-4] Connect both inputs to ground via 1-kΩresistors (default)
[5-6] Short negative input to ground
JP3
Connection for channel 2 analog inputs
[1-2] Short positive input to ground
[3-4] Connect both inputs to ground via 1-kΩresistors (default)
[5-6] Short negative input to ground
JP4
Connection for channel 3 analog inputs
[1-2] Short positive input to ground
[3-4] Connect both inputs to ground via 1-kΩresistors (default)
[5-6] Short negative input to ground
2.2 ADC External Clock (CLKIN) Options
The ADS131M04 requires a continuous, free-running external master clock at the CLKIN pin for normal
operation. The onboard complementary metal oxide semiconductor (CMOS) crystal oscillator (Y1)
provides the nominal 8.192-MHz clock frequency used in the high-resolution (HR) mode of the device.
Two D flip-flops (U3) divide the Y1 clock output to produce clock frequencies of 4.096 MHz and 2.048
MHz to support the low-power (LP) mode and very-low-power (VLP) mode, respectively.
Install a jumper in the appropriate position on the JP6 header shown in Figure 4 to provide selectable
clock frequency options. An external clock frequency can also be provided to any even-numbered pin on
JP6 when the jumper is uninstalled. TI also recommends powering down Y1 by installing JP5 when
providing an external clock. When using an external clock, ground must be shared between the external
clock source and the EVM ground. The external clock must adhere to the frequency and amplitude limits
outlined in the ADS131M04 data sheet. Table 4 lists the JP6 jumper settings for the clock input selections.
In addition to jumper settings, each of the power modes requires configuration register settings outlined in
Section 6.1.
Figure 4. CLKIN External Clock (PCB)
Table 4. CLKIN External Clock Options
J13 Jumper Setting Clock Frequency Description
[1-2] 8.192 MHz Nominal clock for high-resolution mode (default)
[3-4] 4.096 MHz Nominal clock for low-power mode
[5-6] 2.048 MHz Nominal clock for very-low-power mode

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3 Digital Interface
As noted in Section 1, the EVM interfaces with the PHI and communicates with the computer over the
USB. There are two devices on the EVM with which the PHI communicates: the ADS131M04 ADC (over
SPI) and the EEPROM (over I2C). The EEPROM comes pre-programmed with the information required to
configure and initialize the ADS131M04EVM platform. When the hardware is initialized, the EEPROM is
no longer used.
3.1 SPI Communication
The ADS131M04EVM supports limited interface modes as detailed in the ADS131M04 data sheet. The
ADS131M04 uses an SPI-compatible interface to configure the device and retrieve conversion data. SPI
communication on the ADS131M04 is performed in frames. Each SPI communication frame consists of
several words. The word size is configurable as either 16 bits, 24 bits (default), or 32 bits by programming
the WLENGTH[1:0] bits in the MODE register.
Additionally, the DRDY pin indicates when conversion data are available to be read by the master. The
DRDY_SEL[1:0] bits, DRDY_HIZ bit, and the DRDY_FMT bit in the MODE register control the behavior of
the DRDY pin.
For this EVM not all modes and functions for this SPI communication are supported. Functions not
supported are disabled in the EVM GUI software. For more information about the SPI communication, see
the ADS131M04 data sheet.
3.2 Connection to the PHI
The ADS131M04EVM board communicates with the PHI through a shrouded, 60-pin connector, J5. There
are two round standoffs next to J5 with Phillips-head screws. To connect the PHI to the EVM, remove the
screws, attach the PHI to the EVM, and replace the screws into the standoffs. The screws secure the
EVM to the PHI and ensures the connection between the boards.
Table 5 lists the different PHI connection and their functions.
Table 5. PHI Connector Pin Functions
PHI Connector Pin Name PHI Connector Pin Function
EVM_RAW_5V J5[2] Power-supply source for the analog section of the EVM
GND J5[3] Ground
SYNC/RESET J5[10] Conversion synchronization or system reset for the
ADS131M04; active low
DIN J5[18] Serial data input for the ADS131M04
CLK J5[20] Master clock input for the ADS131M04
CS J5[22] Chip select for the ADS131M04; active low
SCLK J5[24] Serial data clock for the ADS131M04
SCLK J5[28] Serial data clock for the ADS131M04
DRDY J5[30] Data ready for the ADS131M04; active low
DOUT J5[36] Serial data output for the ADS131M04
EVM_DVDD J5[50] Power-supply source for the digital section of the EVM
SDA J5[56] I2C serial data for the EEPROM used to identify the EVM
SCL J5[58] I2C serial clock for the EEPROM used to identify the EVM
EVM_ID_PWR J5[59] Power-supply source for the EEPROM used to identify the EVM
GND J5[60] Ground

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3.3 Digital Header
In addition to the PHI, the EVM has a header connected to the digital lines that can be used to connect a
logic analyzer or oscilloscope. This placement allows for easy access to the digital communications.
Header J6 is connected to the digital lines between the ADS131M04 and the PHI connector. Table 6
describes the digital header pins.
Table 6. Digital Header Pins
ADS131M04 Pin Name Digital Header Pin
SYNC/RESET J6[1]
DIN J6[2]
CLK J6[3]
CS J6[4]
SCLK J6[5]
DRDY J6[6]
DOUT J6[7]
GND J6[8]
3.4 LaunchPad™ Connectors
On the bottom side of the ADS131M04EVM board is a set of unpopulated surface-mount connectors (J7
and J8). When populated, these devices can be used to connect to a TI LaunchPad™ directly as a typical
BoosterPack™ plug-in module.
Connectors J7 and J8 are a set of 10x2, 100 mil connectors. As shown in Table 7, the pin numbers for J7
and J8 map to the pin numbers for a standard 40-pin LaunchPad™ connector.
Table 7. LaunchPad™ Pin Functions
ADS131M04EVM Connection ADS131M04EVM (J7, J8) LaunchPad™ Connection
+3.3V J8[1] Pin 1
SCLK J8[7] Pin 7
DOUT J7[14] Pin 14
DIN J7[12] Pin 15
GND J7[2] Pin 20
+5V J8[2] Pin 21
GND J8[4] Pin 22
DRDY J7[7] Pin 37
CS J7[5] Pin 38
SYNC/RESET J7[3] Pin 39
CLK J7[1] Pin 40

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4 Power Supplies
The PHI provides multiple power-supply options for the EVM, derived from the USB supply of the
computer.
The EEPROM on the ADS131M04EVM uses a 3.3-V power supply generated directly by the PHI. The
analog supply of the ADC is powered by the LP5907 onboard the EVM, which is a low-noise linear
regulator that uses the 5-V supply on the PHI to generate a cleaner 3.3-V output. The 3.3-V supply to the
digital section of the ADC is provided directly by an LDO on the PHI.
The power supply for each active component on the EVM is bypassed with a ceramic capacitor placed
close to that component. Additionally, the EVM layout uses thick traces or large copper fill areas, where
possible, between bypass capacitors and their loads to minimize inductance along the load current path.
As mentioned previously in Section 1, power to the EVM is supplied by the PHI through connector J5. For
information about PHI pins and the power connections, see Table 5.
With modifications, the user may use external supplies for either AVDD or DVDD. AVDD can be driven
externally by moving the jumper on JP9 to the left. This placement disconnects 3V3_LDO from AVDD.
Power can then be applied through the AVDD test point at TP2 or through 3V3_LP if connector J8 is
installed. DVDD can be driven externally from the DVDD test point at TP1 if R45 is removed from the
EVM.

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5 ADS131M04EVM Initial Setup
This section explains the initial hardware and software setup procedure that must be completed for
properly operating the ADS131M04EVM.
5.1 Default Jumper Settings
After unpacking, the EVM is already configured with the default jumper settings. Figure 5 shows the
locations for the default jumpers.
Figure 5. ADS131M04EVM Jumper Default Settings
The default position of the JP6 jumper is across [1-2] at the top. JP6 sets the onboard oscillator frequency
to 8.192 MHz, used for the ADS131M04 in high-resolution mode. The default connection for JP9 is to the
left, so that the linear regulator is powering the system using 5 V from the PHI controller.
The default settings, as listed in Table 8, includes no jumpers installed at JP5, JP7, and JP8. When
installed, JP5 disables the onboard oscillator, JP7 enables the EEPROM for write, and JP8 disables the
linear regulator.
Table 8. Default Settings
Jumper Position Function
JP1, JP2, JP3, JP4 [3-4] Sets common-mode to ground for device inputs
JP5 Not installed Disables on-board oscillator
JP6 [1-2] Oscillator frequency select, 8.192MHz
JP7 Open Disables write for EEPROM
JP8 Not installed Disables linear regulator power
JP9 [1-2] Selects device power from linear regulator
5.2 EVM Graphical User Interface (GUI) Software Installation
Download the latest version of the EVM GUI installer from the Tools and Software folder of the
ADS131M04EVM and run the GUI installer to install the EVM GUI software on your computer.
CAUTION
Manually disable any antivirus software running on the computer before
downloading the EVM GUI installer onto the local hard disk. Depending on the
antivirus settings, an error message may appear or the installer. The exe file
can be deleted.

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Accept the license agreements and follow the on-screen instructions shown in Figure 6 to complete the
installation.
Figure 6. ADS131M04 Software Installation Prompts
As a part of the ADS131M04EVM GUI installation, a prompt with a Device Driver Installation (as shown in
Figure 7) appears on the screen. Click Next to proceed.
Figure 7. Device Driver Installation Wizard Prompts

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NOTE: A notice may appear on the screen stating that Windows cannot verify the publisher of this
driver software. Select Install this driver software anyway.
The ADS131M04EVM requires the LabVIEW™ run-time engine and may prompt for the installation of this
software, as shown in Figure 8, if not already installed.
Figure 8. LabVIEW Run-Time Engine Installation

INSTALL
D2 D1
D5
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Verify that C:\Program Files (x86)\Texas Instruments\ADS131M04EVM is as shown in Figure 9 after these
installations.
Figure 9. ADS131M04EVM GUI Folder Post-Installation
6 ADS131M04EVM Operation
The following instructions are a step-by-step guide to connecting the ADS131M04EVM to the computer
and evaluating the performance of the ADS131M04:
1. Connect the ADS131M04EVM to the PHI. Install the two screws as indicated in Figure 10.
2. Use the provided USB cable to connect the PHI to the computer.
• LED D5 on the PHI lights up, indicating that the PHI is powered up
• LEDs D1 and D2 on the PHI start blinking to indicate that the PHI is booted up and communicating
with the PC; Figure 10 shows the resulting LED indicators
Figure 10. ADS131M04EVM Hardware Setup and LED Indicators

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3. Figure 11 shows how to launch the ADS131M04EVM GUI software.
Figure 11. Launch the EVM GUI Software

1. Information Area
2. Pages
4. Interface
Configuration
5. Clock and
Sampling Rate
3. Single
Commands
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6.1 EVM GUI Global Settings for ADC Control
Although the EVM GUI does not allow direct access to the levels and timing configuration of the ADC
digital interface, the EVM GUI does give users high-level control over virtually all functions of the
ADS131M04 including interface modes, sampling rate, and number of samples to be captured. Figure 12
identifies the input parameters of the GUI (as well as their default values) through which the various
functions of the ADS131M04 can be exercised.
Figure 12. EVM GUI Global Input Parameters
There are four pages available in the ADS131M04EVM GUI. The information area displays the results of
each of the pages. Each of these pages display a different control or measurement of the device. The
Register Map Config page is used to read and write to the registers of the device. The Time Domain
Display page is used to collect a set of data from the device and display the result. The Spectral Analysis
page can determine the FFT of the collected data, and the Histogram Analysis page shows a histogram of
the collected data and displays basic statistics of the result.
The Single Commands section allows for direct control of the device for three basic functions. First the
Reset button sends a signal to the SYNC/RESET pin to reset the device. The Standby button puts the
device into a low-power state in which all channels are disabled, and the reference and other non-
essential circuitry are powered down. The Wakeup button exits the standby mode.
The Interface Configuration options in this pane allows the user to choose from different frame word sizes
available on the ADS131M04. This section also sets the data rate by setting the oversampling ratio (OSR)
in the ADC. Finally, this section may used to set the power modes in the registers. The ADS131M04 can
be set to high-resolution, low power, and very-low power modes in conjunction with the jumper settings of
JP6 for the CLKIN pin, as outlined in Table 4. This information is also discussed in Section 2.2.
The Clock and Sampling Rate section allows the user to specify a target SCLK frequency (in Hz) and the
GUI tries to match this frequency as closely as possible by changing the PHI PLL settings, but the
achievable frequency may differ from the target value entered. This section also displays the sampling
rate of the ADC as controlled by the OCR.
The GUI is switched between hardware mode and simulation mode by checking and unchecking the
Connected to Hardware box in the top right area of the screen at any time.

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6.2 Register Map Configuration Tool
The register map configuration tool allows the user to view and modify the registers of the ADS131M04.
This tool can be selected, as indicated in Figure 13, by clicking on the Register Map Config radio button at
the Pages section of the left pane. On power-up, the values on this page correspond to the Host
Configuration Settings that enable ADC sampling at the maximum sampling rate specified for the ADC.
The register values can be edited by double-clicking the corresponding value field. If interface mode
settings are affected by the change in register values, this change reflects on the left pane immediately.
The changes in the register value reflect on the AD131M04 device on the ADS131M04EVM based on the
Update Mode selection, as described in Section 6.1.
Figure 13. Register Map Configuration
Section 6.3 through Section 6.5 describe the data collection and analysis features of the ADS131M04EVM
GUI.

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6.3 Time Domain Display Tool
The time domain display tool allows visualization of the ADC response to a given input signal. This tool is
useful for both studying the behavior and debugging any gross problems with the ADC or drive circuits.
The user can trigger a capture of the data of the selected number of samples from the ADS131M04EVM,
as per the current interface mode settings indicated in Figure 14 by using the Capture button. The sample
indices are on the x-axis and there are two y-axes showing the corresponding output codes as well as the
equivalent analog voltages based on the specified reference voltage. Switching pages to any of the
Analysis tools described in the subsequent sections causes calculations to be performed on the same set
of data.
Figure 14. Time Domain Display Tool Options

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6.4 Spectral Analysis Tool
The spectral analysis tool, shown in Figure 15, is intended to evaluate the dynamic performance (SNR,
THD, SFDR, SINAD, and ENOB) of the ADS131M04 ADC through single-tone sinusoidal signal FFT
analysis using the 7-term Blackman-Harris window setting.
Figure 15. Spectral Analysis Tool
The FFT tool includes windowing options that are required to mitigate the effects of non-coherent
sampling (this discussion is beyond the scope of this document). The 7-Term Blackman Harris window is
the default option and has sufficient dynamic range to resolve the frequency components of up to a 24-bit
ADC. The None option corresponds to not using a window (or using a rectangular window) and is not
recommended.

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6.5 Histogram Tool
Noise degrades ADC resolution and the histogram tool can be used to estimate effective resolution, which
is an indicator of the number of bits of ADC resolution losses resulting from noise generated by the
various sources connected to the ADC when measuring a DC signal. The cumulative effect of noise
coupling to the ADC output from sources such as the input drive circuits, the reference drive circuit, the
ADC power supply, and the ADC itself is reflected in the standard deviation of the ADC output code
histogram that is obtained by performing multiple conversions of a DC input applied to a given channel.
As shown in Figure 16, the histogram corresponding to a DC input is displayed on clicking the Capture
button.
Figure 16. Histogram Analysis Tool