Texas Instruments TLK1501 User manual

TLK1501 Serdes EVM Kit
Setup and Usage
June 2000 Mixed Signal Products
User’s Guide
SLLU008

IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TIdeemsnecessarytosupport thiswarranty. Specifictestingofallparameters ofeachdevice isnotnecessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICALAPPLICATIONS.INCLUSIONOFTIPRODUCTSINSUCHAPPLICATIONSISUNDERSTOODTO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TIassumes noliabilityforapplicationsassistance orcustomer productdesign. TIdoes notwarrantorrepresent
thatanylicense,eitherexpressorimplied,isgrantedunderanypatentright,copyright,maskworkright,orother
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Copyright 2000, Texas Instruments Incorporated

Notational Conventions
iii
Read This First
Preface
Read This First
About This Manual
This manual should be used to determine how to set up and use the TLK1501
evaluation module in order to evaluate the TLK1501 device.
How to Use This Manual
This document contains the following chapters:
- Chapter 1 — Introduction
- Chapter 2 — TLK1501 EVM Board Configuration
- Chapter 3 — PCB Construction and Characteristics
- Appendix A — Schematics, Board Layouts, and Suggested Optics and
Cable Assembly Specifications
- Appendix B — NetLight1417K4A 1300 nm Laser 2.5 Gbits/s
SpeedBlasterTransceiver data sheet
Notational Conventions
This document uses the following conventions.
- Program listings, program examples, and interactive displays are shown
in a special typeface similar to a typewriter’s. Examples use a bold
version of the special typeface for emphasis; interactive displays use a
bold version of the special typeface to distinguish commands that you
enter from items that the system displays (such as prompts, command
output, error messages, etc.).
Here is a sample program listing:
0011 0005 0001 .field 1, 2
0012 0005 0003 .field 3, 4
0013 0005 0006 .field 6, 3
0014 0006 .even
Here is an example of a system prompt and a command that you might
enter:
C: csr –a /user/ti/simuboard/utilities

Trademarks
iv
-
In syntax descriptions, the instruction, command, or directive is in a bold
typefacefontandparametersareinan italictypeface .Portionsofasyntax
that are in bold should be entered as shown; portions of a syntax that are
in
italics describe the type of information that should be entered. Here is
an example of a directive syntax:
.asect ”
section name ”, address
.asectisthedirective.Thisdirectivehastwoparameters,indicatedby sec-
tionname and address .Whenyou use .asect, thefirstparameter must be
anactualsectionname,enclosedindoublequotes;thesecondparameter
must be an address.
- Square brackets ( [and ]) identify an optional parameter. If you use an
optional parameter, you specify the information within the brackets; you
don’t enter the brackets themselves. Here’s an example of an instruction
that has an optional parameter:
LALK
16–bit constant [, shift]
TheLALKinstruction hastwoparameters.Thefirstparameter, 16-bitcon-
stant , is required. The second parameter, shift , is optional. As this syntax
shows,ifyou usetheoptionalsecondparameter,youmustprecedeit with
a comma.
Square brackets are also used as part of the pathname specification for
VMS pathnames; in this case, the brackets are actually part of the path-
name (they are not optional).
- Braces( {and} )indicatealist.Thesymbol|(readas or )separatesitems
within the list. Here’s an example of a list:
{ * | *+ | *– }
This provides three choices: *, *+, or *–.
Unless the list is enclosed in square brackets, you must choose one item
from the list.
- Some directives can have a varying number of parameters. For example,
the .byte directive can have up to 100 parameters. The syntax for this di-
rective is:
.byte value
1
[, ... , value
n
]
This syntax shows that .byte must have at least one value parameter, but
you have the option of supplying additional value parameters, separated
by commas.
Trademarks
TI is a trademark of Texas Instruments Incorporated.
NetLight and SpeedBlaster are trademarks of Lucent Technologies Inc.

Running Title—Attribute Reference
v
Chapter Title—Attribute Reference
Contents
1 Introduction 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Introduction 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 TLK1501 EVM Kit Contents 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 TLK1501 EVM Board Configuration 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Typical Test and Setup Configurations 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Optical Interfacing and Configuration 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 PCB Construction and Characteristics 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A Schematics, Board Layouts, and Suggested Optics and Cable
Assembly Specifications A-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B NetLight1417K4A 1300 nm Laser 2.5 Gbits/s SpeedBlasterTransceiver B-1. . . . . . . . . .

Running Title—Attribute Reference
vi
Figures
2–1 TLK1501 Serial Loop-Back Test Configuration 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–2 TLK1501 Serial Loop-Back Test Configuration 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–3 TLK1501 Serial PRBS BERT Test Configuration 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–4 TLK1501 Serial PRBS BERT Test Configuration 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–5 Optical Interface Configuration 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–6 TLK1501EVM to Laser Module Configuration 2-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–1 TLK1501 EVM Layer Construction 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–1 TLK1501 EVM Transceiver Schematic A-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–2 Optical Transceiver Schematic A-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–3 Top Layer 1 A-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–4 GND Layers 2 and 5 A-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–5 Power Plane 1 A-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–6 Bottom Layer 6 A-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–7 Bottom Layer 7 A-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–8 Top Layer 1 1-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–9 Detail of Top Layer 1 1-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–10 GND Layers 2 and 5 1-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–11 Detail of GND Layers 2 and 5 1-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–12 Power Plane 1 1-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–13 Detail of Power Plane 1 1-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–14 Bottom Layer 6 1-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–15 Detail of Bottom Layer 6 1-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–16 Bottom Layer 6 1-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–17 Detail of Bottom Layer 6 1-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tables
2–1 Default Transceiver Board Configuration as Shipped 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–2 Configuration Changes Necessary for DC-Coupling of the High-Speed Signals 2-2. . . . . . . .
3–1 TLK1501 EVM TTL Bus PCB Transmission Line Characteristics 3-2. . . . . . . . . . . . . . . . . . . .
3–2 TLK1501 Differential Pair PCB Transmission Line Characteristics 3-2. . . . . . . . . . . . . . . . . . .
A–1 TLK1501 EVM Transceiver Bill of Materials A-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-1
Introduction
Introduction
The Texas Instruments (TI) TLK1501 serdes evaluation module (EVM) board
is used to evaluate the TLK1501 device(VQFP) and associated optical inter-
face (NetLight) for point-to-point data transmission applications.
The board enables the designer to connect 50 Ωparallel buses to both
transmitter and receiver connectors. The TLK1501, using high speed PLL
technology, serializes, encodes (8b/10b) and transmits data along one
differential pair. The receiver part of the device deserializes, decodes and
presents data on the parallel bus. The high speed (up to 1.6 Gbps) data lines
interface to four 50-Ωcontrolled-impedance SMA connectors. The designer
can either use this copper interface directly or loop back to the laser module
section for an optical interface(not provided).
Topic Page
1.1 Introduction 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 1

Introduction
1-2
1.1 Introduction
Theboard can be used to evaluate device parameters while acting as a guide
for high-speed board layout. The evaluation board can be used as daughter
boards that are plugged into new or existing designs. Since the TLK1501
operatesoverawide rangeoffrequencies,thedesignerswill needtooptimize
theirdesign for the frequency of interest. Additionally, the designers may wish
to use buried transmission lines and provide additional noise attenuation and
EMI suppression to optimize their end product.
Asthefrequencyofoperationincreases,theboarddesignermusttakespecial
care to ensure that the highest signal integrity is maintained. To achieve this,
theboard’simpedanceiscontrolledto50Ωforboththehigh-speeddifferential
serial and parallel data connections. In addition, impedance mismatches are
reduced by designing the component pad size to be as close as possible to
the width of the connecting transmission lines. Vias are minimized and, when
necessary, placed as close as possible to the device drivers. Since the board
contains both serial and parallel transmission lines, care was taken to control
both impedance and trace length mismatch (board skew).
Overall, the board layout is designed and optimized to support high-speed
operation. Thus, understanding impedance control and transmission line
effects are crucial when designing high-speed boards.
Some of the advanced features offered by this board include:
- PCB (printed-circuit board) is designed for high-speed signal integrity.
- Flexibility–The PCB can be configured for copper or optical interfaces.
- SMA and parallel fixtures are easily connected to test equipment.
- All input/output signals are accessible for rapid prototyping.
- Analoganddigitalpowerplanescanbesuppliedthroughseparatebanana
jacks for isolation or can be combined using ferrite bridging networks.
- Series termination resistors provide parallel RD outputs.
- Onboard capacitors provide ac-coupling of high-speed signals.
1.2 TLK1501 EVM Kit Contents
- TLK1501 EVM board
- TLK1501 EVM kit documentation (This document)

2-1
TLK1501 EVM Board Configuration
TLK1501 EVM Board Configuration
The TLK1501 EVM board gives the developer various options for operation,
manyofwhicharejumperselectable.Otheroptionscanbeeithersolderedinto
the EVM or connected through input connectors.
The TX and RX parallel connectors, J1–J4 of Figures 8 and 10 in Appendix A,
provide a connection for both transmitted and received data. The reference
clock is supplied through SMA connector J8 and jumper J5 must be installed
between pins 1 and 2. A direct clock connection can also be made to J5 pins
1 and 3. The high-speed serial data is transmitted through J13 and J14 SMA
connectors. The received recovered clock (RX_CLK) is output through J15
header. Received data connects through SMA connectors J17 and J23 on the
RX side of the board. Header J7 provides static signals (normally pulled high)
to configure the device for different modes of operation. The J20 header
indicates the optical transmitter has detected a signal and J21 allows the
operator to disable the optical transceiver.
The power planes are split three ways to provide power for different parts of
the board. This prevents coupling of switching noise between the analog and
digital sections of the TLK1501 and provides voltage isolation for the laser
section. The laser section of the board requires 3.3 volts and is energized
throughtheVCC connector.The VDD and VDDA connectorsrequire 2.5 volts
and are joined together by a removable ferrite bead L3 that is installed in the
defaultconfiguration.Thus,onlytheVDDconnectionisnecessarytoenergize
the TLK1501 device in the default configuration. In all sections of the board,
thegroundplanesarecommonandeachgroundplaneistiedtogetheratevery
component ground connection. For a detailed schematic and layout see
TLK1501EVM Schematic , Optical Transceiver Schematic and Board Layer
Stack-up in Appendix A.
Topic Page
2.1 Typical Test and Setup Configurations 2–3. . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Optical Interfacing and Configuration 2–7. . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 2

2-2
Theboardisnormallydeliveredinadefaultconfigurationthatrequiresexternal
clock and data inputs. The TLK1501 is shipped with jumpers for default
operation. Table 2–1 shows the default configuration for sending data.
Table 2–1.Default Transceiver Board Configuration as Shipped
Designator Function Condition
J5 GTX CLK SEL Jumper installed – Provides a method of supplying an input clock to
the board
J7 TESTEN Jumper installed (Logic 0)
Disables the TLK1501 test mode
J7 PRBSEN Jumper installed (Logic 0)
Disables the TLK1501 PRBS internal production test mode
J7 LCKREFN Jumper not installed (Logical 1)
Locks to received clock
J7 ENABLE Jumper not installed (Logical 1)
Enables the device for normal operation
J7 TXER Jumper installed (Logic 0)
Puts the TLK1501 in a state to transmit TX bus data
J7 LOOPEN Jumper installed (Logic 0)
Disables the TLK1501 internal loop back mode
J7 TXEN Jumper not installed (Logical 1)
Puts the TLK1501 in a state to transmit TX bus data
L3 VDD– bridge –VDDA Joins VDD and VDDA power planes
C24, C25 TX ac-coupling
capacitors These capacitors (normally installed) are provided to ac-couple the transmitted signal.
C22, C23 RX ac-coupling
capacitors These capacitors (normally installed) are provided to ac-couple the received signal
Note: For details, see TLK1501 data sheet
Table 2–2.Configuration Changes Necessary for DC Coupling of the High Speed Signals
Designator Function Condition or Changes Necessary for DC Coupling
C24, C25 TX ac-coupling
capacitors Install zero ohm resistors
C22, C23 TX ac-coupling
capacitors Install zero ohm resistors.
R34 RX bias resistor Install zero ohm resistor.
R33 RX bias resistor Uninstall resistor (open circuit)
R37, R38 TX termination
network Uninstall resistors (open circuit) – Termination and pullup is achieved at the receiver. Differential swing is increased.

Typical Test and Setup Configurations
2-3
TLK1501 EVM Board Configuration
2.1 Typical Test and Setup Configurations
The following configurations are used to evaluate and test the TLK1501
transceiver. The first configuration is a serial loopback of the high-speed
signals shown in Figure 2–1. The serial loopback allows the designer to
evaluate most of the functions of both transmitter and receiver sections of the
TLK1501 device. To test a system, a parallel bit error rate tester (BERT)
generates a predefined parallel bit pattern. The pattern is connected to the
transmitter through parallel connectors TD0–TD15. Additionally, two control
pins TX_ER and TX_EN are configured by the BERT for valid data
transmission (TX_ER low and TX_EN high). The TLK1501 device encodes,
serializes, and presents the data on the high-speed serial pair. The serial TX
data is then looped back to the receiver side and the device deserializes,
decodes,andpresentsthe dataonthereceivesideRD0–RD15.Thedataand
indication bits (RX_DV andRX_ER) are received by the BERT and compared
against the transmitted pattern and monitored for valid data and errors. If any
biterrorsarereceived,abiterrorrateisevaluatedattheparallelreceiveBERT.
Figure 2–1.TLK1501 Serial Loop-Back Test Configuration
TX_EN
TX Data Out 0-17 18 bits
Parallel BERT
Frequency = 30-80 MHz
CLK IN
RX Data In 0-17 18 bits
Receiver BERT
GTX_CLK
TD 0-15
TX_EN
TX_ER
RD 0-15
RX_ER
RX_DV
RX CLK
TX+
RX–
RX+
TX–
(Asynchronous to BERT)
EXT INPUT
HP8133A
Pulse Generator
Channel 1
O/P
GND
LOOPEN
TX_ER
ENABLE
LCKREFN
PRBSEN
TESTEN
GND
J7
TLK1501EVM
Evaluation Board
Jumper Selection
CLK OUT

Typical Test and Setup Configurations
2-4
If a parallel BERT is not available, the designer can take advantage of the
built-in test mode of the device, see Figure 2–2. If the designer asserts the
PRBSENpin highthisresultsinapseudorandombit patterntobetransmitted.
ThispinalsoputsthereceiverinamodetodetectavalidPRBSpattern.Avalid
pattern is indicated by the PRBSPASS pin indicating high. This test only
validatesthehigh-speedserialportionofthedeviceandsysteminterconnects.
The PRBS pattern is compatible with most serial BERT test equipment. This
function allows the operator to isolate and test the transmitter and receiver
independently. A typical configuration is shown in Figure 2–3. The dashed
linesrepresentoptionalconnectionsthatcanbemademonitoringeyepatterns
and measuring jitter.
Figure 2–2.TLK1501 Serial Loop-Back Test Configuration
Channel 1
TDS820 Digital
Oscilloscope
TX_EN
GTX_CLK
PRBS
2^7-1 TX–
RX–
RX+
TX+
GND
LOOPEN
TX_ER
ENABLE
LCKREFN
PRBSEN
TESTEN
GND
J7
TLK1501EVM
Evaluation Board
RD 0-15
PRBS_PASS
PRBS 2^7-1
CH1
HP83480 or
Tek 11801
Trigger
CH2
Digital
Oscilloscope
EXT
INPUT
HP8133A
Pulse Generator
Channel 1
O/P
TRIGGER
OUT
Jumper Selection

Typical Test and Setup Configurations
2-5
TLK1501 EVM Board Configuration
Figure 2–3.TLK1501 Serial PRBS BERT Test Configuration
Channel 1
TDS820 Digital
Oscilloscope
TX_EN
GTX_CLK
PRBS
2^7-1 TX–
RX–
RX+
TX+
GND
LOOPEN
TX_ER
ENABLE
LCKREFN
PRBSEN
TESTEN
GND
J7
TLK1501EVM
Evaluation Board
RD 0-15
PRBS_PASS
PRBS 2^7-1
CH1
HP83480 or
Tek 11801
Trigger
CH2
Digital
Oscilloscope
EXT
INPUT
HP8133A
Pulse Generator
Channel 1
O/P
TRIGGER
OUT
Data In
Serial BERT
HP7004A 3 Gbps
CLK OUT
Transmitter BERT
Receiver BERT
Data Out
Data Out
CLK/20
Jumper Selection
A board-to-board communication link is a practical method of evaluating the
TLK1501 in a system-like environment as shown in Figure 2–4. A Parallel
BERT or a logic analyzer can be used to provide and monitor signals to and
fromthetransceiverpairs. The BERTwouldneedto configuretheTX_ERand
TX_EN signals for data transmission before any data is sent. On the receive
sidetheRX_ERandRX_DVcanmonitorthedeviceforerrors.BothGTX_CLK
sources must have the same frequency within 200 PPM for asynchronous
operation. Synchronous operation can be achieved by using either the BERT
or a synchronized pulse generator to supply both boards with GTX_CLK
inputs.

Typical Test and Setup Configurations
2-6
Figure 2–4.TLK1501 Serial PRBS BERT Test Configuration
TX_EN
GTX_CLK
TX_EN
TX_ER
TX+
RX–
RX+
TX–
GND
LOOPEN
TX_ER
ENABLE
LCKREFN
PRBSEN
TESTEN
GND
J7
TLK1501EVM #1
Evaluation Board EVM1
PRBS Disabled
RD 0-15
EVM #1
TX Data Out 0-17
Parallel BERT
Frequency = 30-80 MHz
CLK IN
RX Data In 0-17 18 bits
Receiver BERT
Transmitter BERT
CLK Out
18 bits
TD 0-15
GTX_CLK
RX–
RD 0-15
TD 0-15
RX_CLK
RX_ER
Rx_DV
TLK1501EVM #2
Evaluation Board EVM2
PRBS Disabled
TX–
RX+
TX+
Synchronous
Asynchronous
Board configued to
send IDLE pattern:
TX_EN = 0
TX_ER = 0
Jumper Selection
TX_EN
GND
LOOPEN
TX_ER
ENABLE
LCKREFN
PRBSEN
TESTEN
GND
J7
EVM #2
EXT INPUT
HP8133A
Pulse Generator
Channel 1
O/P
Trigger
16 bits
2 bits
Channel
1
(Asynchronous to BERT)

Optical Interfacing and Configuration
2-7
TLK1501 EVM Board Configuration
2.2 Optical Interfacing and Configuration
An interface between the TLK1501EVM and an optical transceiver can be
achieved in many ways, depending on the design of the optics module and its
associated interface circuitry. Direct connection is achieved only if the optical
interface supports the current mode logic levels of the TLK1501 device (VDD
– 1 V). If the optics module does not support or can not be biased to the CML
levelsthen ac-coupling must beused. Both ac- and dc-coupling schemes are
shown in Figure 2–5. The
Laser Module Section of the EVM is configured as
anac-coupledoptics module. The boardisshipped with an ac-coupledoutput
and all that is required is external loopback cabling.
Figure 2–5.Optical Interface Configuration
50 Ω
TLK1501 TX
VDD
CMLDC bias levels
voltage ≈(VDD-1 V) Optical Module
DC Coupling
50 Ω
TLK1501 TX
VCC
Biased to CML Levels Optical Module
AC Coupling
50 Ω
VDD
Biased to PECL Levels
50 Ω
The Laser Module Section is isolated from the rest of the board and requires
external loopback as shown in Figure 2–6. This makes for a versatile system
where the laser can be connected independently to other EVM systems.

Optical Interfacing and Configuration
2-8
TLK2500 EVM Board Configuration
Figure 2–6.TLK1501 EVM to Laser Module Configuration

3-1
PCB Construction and Characteristics
PCB Construction and Characteristics
The PCB characteristics are calculated and based on the layer construction
and trace width of the board. This should be useful in determining the proper
interface to the EVM and establishing system timing.
Chapter 3

3-2
Table 3–1.TLK1501 EVM TTL Bus PCB Transmission Line Characteristics
Device
Pin No./Des. Connector Pin Label Trace Width (inches) Length (inches) Capacitance (pF) Inductance (nH) Impedance (Ω)Line Delay (ps)
62 – TXD0 TD0 0.0118 1.887 5.2 14.1 51.9 272.1
63 – TXD1 TD1 0.0118 1.884 5.2 14.1 51.9 271.7
64 – TXD2 TD2 0.0118 1.904 5.3 14.3 51.9 274.7
2 – TXD3 TD3 0.0118 1.898 5.3 14.2 51.9 273.7
3 – TXD4 TD4 0.0118 1.903 5.3 14.2 51.9 274.4
4 – TXD5 TD5 0.0118 1.899 5.3 14.2 51.9 273.8
6 – TXD6 TD6 0.0118 1.901 5.3 14.2 51.9 274.1
7 – TXD7 TD7 0.0118 1.906 5.3 14.3 51.9 274.8
10 – TXD8 TD8 0.0118 1.860 5.2 13.9 51.9 268.2
11 – TXD9 TD9 0.0118 1.908 5.3 14.3 51.9 275.1
12 – TXD10 TD10 0.0118 1.884 5.2 14.1 51.9 271.7
14 – TXD11 TD11 0.0118 1.912 5.3 14.3 51.9 275.7
15 – TXD12 TD12 0.0118 1.903 5.3 14.2 51.9 274.4
16 – TXD13 TD13 0.0118 1.910 5.3 14.3 51.9 275.4
17 – TXD14 TD14 0.0118 1.911 5.3 14.3 51.9 275.6
19 – TXD15 TD15 0.0118 1.901 5.3 14.2 51.9 274.1
51 – RXD0 RD0 0.0118 1.814 5.0 13.6 51.9 26.6
50 – RXD1 RD1 0.0118 1.804 5.0 13.5 51.9 260.3
49 – RXD2 RD2 0.0118 1.802 5.0 13.5 51.9 259.9
47 – RXD3 RD3 0.0118 1.862 5.2 13.9 51.9 268.5
46 – RXD4 RD4 0.0118 1.866 5.2 14.0 51.9 269.1
45 – RXD5 RD5 0.0118 1.876 5.2 14.0 51.9 270.5
44 – RXD6 RD6 0.0118 1.880 5.2 14.1 51.9 271.1
42 – RXD7 RD7 0.0118 1.865 5.2 14.0 51.9 268.9
40 – RXD8 RD8 0.0118 1.860 5.2 13.9 51.9 268.2
39 – RXD9 RD9 0.0118 1.860 5.2 13.9 51.9 268.2
37 – RXD10 RD10 0.0118 1.863 5.2 13.9 51.9 268.6
36 – RXD11 RD11 0.0118 1.872 5.2 14.0 51.9 269.9
35 – RXD12 RD12 0.0118 1.816 5.0 13.6 51.9 261.9
34 – RXD13 RD13 0.0118 1.855 5.2 13.9 51.9 267.5
32 – RXD14 RD14 0.0118 1.809 5.0 13.9 51.9 260.9
31 – RXD15 RD15 0.0118 1.821 5.1 13.6 51.9 262.9
Note: All values presented in this table are theoretical calculated values and may not reflect actual measured parameters.
Table 3–2.TLK1501 Differential Pair PCB Transmission Line Characteristics
Device
Pin No. Connector Pin No. Trace Width (inches) Length (inches) Impedance (Ω)Line Delay (ps)
60 – DOUTTXP TXP 0.025 2.390 51.2 347.5
59 – DOUTTXN TXP 0.025 2.363 51.2 343.6
54 – DINRXP RXP 0.025 2.889 51.2 420.1
53 – DINRXN RXN 0.025 2.883 51.2 419.2
Note: All values presented in this table are theoretical calculated values and may not reflect actual measured parameters.

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PCB Construction and Characteristics
Figure 3–1.TLK1501 EVM Layer Construction
Layer 1 Top 50 Ω
GND1
14 Mil
Layer 2 5 Mil
Layer 3 VDD1
VDD2
21 Mil
Layer 4 05 Mil
Layer 5
Solder 50 Ω
GND2
07 Mil
Layer 6
Notes:
1) All cores consist of 1 oz. Cu.
2) Trace width
A) 25 mils (for 50 ΩLayer 1)
B) 11.8 mils (for 50 ΩLayer 6)
3) Overall board thickness is 62 mils ±5 mil
4) Copper and solder mask adds approximately 10 mils to the overall board thickness.
5) Impedance is 50 Ω±5%
6) Material is G-Tek. Dielectric constant = 3.9
7) For overall thickness: add 1.2 to 1.4 mils for each metal layer in the stack-up.

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