Texas Instruments TSW6011EVM User manual

Quick Start Guide
SLWU070B–February 2010–Revised June 2010
TSW6011EVM
This document outlines the basic steps and functions that are required for the proper operation of the
TSW6011 evaluation module (EVM) system. The TSW6011EVM is a single RX channel board that can be
used to demonstrate a TRF371125 integrated direct downconversion receiver interfacing to an ADS5282
octal analog-to-digital converter (ADC). This guide helps the user to evaluate the performance of various
modes of operation of the TSW6011EVM. Throughout this document, the term evaluation module and the
abbreviation EVM are synonymous with the TSW6011EVM.
Contents
1 Overview ..................................................................................................................... 2
1.1 EVM Frequency Configuration Options ......................................................................... 2
1.2 TSW6011EVM Block Diagram ................................................................................... 2
1.3 Digital Processing Block Diagram ............................................................................... 3
2 Software Installation ........................................................................................................ 5
2.1 Installation Instructions ............................................................................................ 5
3 EVM Test Configuration .................................................................................................... 5
3.1 Test Equipment ..................................................................................................... 5
3.2 Calibration ........................................................................................................... 6
4 Board Bring Up .............................................................................................................. 6
4.1 Power Up ............................................................................................................ 6
4.2 Basic RF Test ...................................................................................................... 7
4.3 Software Operation ................................................................................................ 8
4.4 Device Initialization ................................................................................................ 9
4.5 Digital Processing Block Functions ............................................................................ 13
5 TR371125 Register Definitions .......................................................................................... 14
5.1 Register 1 .......................................................................................................... 14
5.2 Register 2 .......................................................................................................... 14
5.3 Register 3 .......................................................................................................... 14
5.4 Register 5 .......................................................................................................... 14
Appendix A ....................................................................................................................... 15
List of Figures
1 TSW6011EVM System Block Diagram .................................................................................. 3
2 FPGA Digital Processing Block Diagram ................................................................................ 4
3 TSW6011EVM Board Top View .......................................................................................... 7
4 TSW6011EVM Software GUI Front Panel............................................................................... 8
5 GUI Communication Error ................................................................................................. 8
6 ADS5282 Control Panel.................................................................................................... 9
7 TR371125 Control Panel ................................................................................................. 10
8 Test Tone From DAC5672 Output ...................................................................................... 11
9 Digital Processing Control Panel........................................................................................ 12
10 Test Tone After IQ Correction and DC Offset Compensation ...................................................... 13
MATLAB is a registered trademark of The MathWorks.
All other trademarks are the property of their respective owners.
1
SLWU070B–February 2010–Revised June 2010 TSW6011EVM
Copyright © 2010, Texas Instruments Incorporated

Overview www.ti.com
1 Overview
The TSW6011EVM board provides options to send an input RF signal directly to the TR371125 or through
one or two low-noise amplifiers (LNAs) by moving two resistors. Additionally, there is an option to drive
two of the ADCs with an external source. This source can be single-ended (board default through a
transformer) or a differential signal (from a TRF3711xxEVM, for example). There also is an option to
bypass the onboard oscillator with an external source. The EVM contains a TRF371125, an ADS5282 for
data conversion, an FPGA for digital processing, a CDCE62005 for system clocks, and a DAC5672A to
allow for data evaluation using just a spectrum analyzer.
1.1 EVM Frequency Configuration Options
The TR371125 device is inherently broadband; however, the radio frequency (RF) and local oscillator (LO)
inputs require differential signals which are achieved with the use of RF baluns. This EVM can be
configured with a different balun to facilitate operation in the desired band. The default configuration
includes 2-GHz baluns for both inputs. Table 1 summarizes the TRF3711xx device frequency options and
lists the recommended balun for each device.
Table 1. TRF3711xx Device Frequencies and Recommended Baluns(1)
Frequency Device Recommended Balun
700 MHz TRF371125 Murata LDB21897M05C
880 MHz TRF371125 Murata LDB21881M05C
940 MHz TRF371125 Murata LDB21942M05C
1740 MHz TRF371125, TRF371135 Murata LDB211G8005C
1950 MHz TRF371125, TRF371135 Murata LDB211G9005C
2025 MHz TRF371125, TRF371135 Murata LDB211G9005C
2500 MHz TRF371125, TRF371135 Murata LDB212G4005C
3550 MHz TRF371125, TRF371135 Johanson 3600BL14M050E
5400 MHz TRF371135 Johanson 5400BL15B050E
(1) There is considerable overlap in the operating frequency range of the TRF3711xx family of devices.
Refer to the specific device data sheet and compare performance parameters at the frequencies of
interest to select the best part for a particular application.
1.2 TSW6011EVM Block Diagram
The TSW6011EVM system block diagram is shown in Figure 1.
Output data can also be analyzed through the use of two other outputs. One output is a connector which
provides unprocessed CMOS digital data. This interface has an RC network on every data and clock
signal to allow the user to plug an Agilent-style logic analyzer pod directly to the connector.
Another option for capturing data is to use a TSW1200EVM data capture card from Texas Instruments.
Connector J21 on the TSW6011 contains unprocessed LVDS data that can be received by a TSW1200
device. The LVDS input connector on the TSW1200 plugs directly into J21 of the TSW6011. This interface
can be used to capture data from all four of the ADCs used by this design. The FPGA reformats the
output to unsigned binary data, which is required by the TSW1200.
2TSW6011EVM SLWU070B–February 2010–Revised June 2010
Copyright © 2010, Texas Instruments Incorporated

BAL
BAL
GC1
GC2
3
2
2
T2
Q_EXT
TRF3
SERIAL
ADC 1
SERIAL
ADC 2
SERIAL
ADC 3
SERIAL
ADC 4
SERIAL
ADC5 -8
X12
I_IF
Q_IF
ADS5282
FPGA
CHA_I
CHA_Q
CHB_I
CHB_Q
DAT1
DAT2
SER_DAT
LCLK
ADC_CLK
20 HI -SPEED
SER_DAT
14 DATA
CLK
FRAME
BAL DAC
OUT
14 DAC
DAC5672
CLOCK GEN
1P/N
EXT REF IN
0P
2P/N
CDCF620
LNA
EXT LO
ADC_CLK
61.44 MHz
[50 - 67.2 MHz] FPGA_CLK = 2 x ADC_CLK
2
T1
2
I_EXT
SPI
3
NC CHC/D_IQ
ACD_CLK
2
2
2
2
8
RF_IN
RF_IN
(OPT)
EXT CLK IN EXT REF OUT
TCXO
3
SPI
SPI
3
USB
USB
XFC SPI
3P
LCLK
GC2
RF_IN
(OPT)
LDO REGULATORS
TPS76718
TPS76733
TPS76033
TPS76750
TPS70445
+3.3V
+5V
+1.8V
+1.2V
15.36 MHz
30.72 MHz
www.ti.com Overview
Figure 1. TSW6011EVM System Block Diagram
1.3 Digital Processing Block Diagram
The FPGA receives the digital data from the ADCs and converts it from serial to parallel format. The data
are then split into two paths. One path converts the data back to unsigned serial data and determines
which ADC output to route to the LVDS connector. The other path either bypasses or goes through the I/Q
correction block (currently not available). From there, the data is interpolated by 2, processed through a
finite impulse response (FIR) filter, then mixed to fS/4 (30.72 MHz). The output rate of the DAC is at
122.88 MHz, and the ADC sample rate is at 61.44 MHz.
The FPGA allows the user to perform the following functions:
• Select TR371125 or SMA data to be processed
• Enable or disable the LVDS and CMOS data outputs
• Bypass the IQ correction algorithm (algorithm to be added by end of 2Q 2010)
• Program ADC, CDC, and TR371125 registers
• Provide dc offset correction to remove LO image
• Set the LNA gain
• Provide attenuation setting for TRF371125
3
SLWU070B–February 2010–Revised June 2010 TSW6011EVM
Copyright © 2010, Texas Instruments Incorporated

x2 Interpolation
0.5dB Step
Gain Control
IQ Correction
Gain
GUI
.
.
.
1 2 3 4
42 43
Unsigned 6-bit
(0 ~ 42) for
Gain Selection
[5:0]
LUT
0.5dB step
Digital Gain
Processing
(-3 ~ 18dB)
I [15:0]
Q [15:0]
x2
Interpolation
I [15:0]
Q [15:0]
I [13:0]
Q [13:0]
I/Q Offset
Correction Quadrature
Mixing
(Fs/4) I [13:0]
Q [13:0]
IQ
Correction
DC Offset
Compensation
IQ
Adaption
Coeff_In
0
1
Coeff_Out
Rounding
By 15-bit
I [32:0]
Q [32:0]
I [17:0]
Q [17:0]
I [15:0]
Q [15:0]
0
1
1 0
IQ Correction block Selection
DC offset compensation Selection
Continue/Bypass mode Selection
Default Coefficient Setting
01
SERDES FIFO
SERDES FIFO
ADC Path Selection
I [11:0]
Q [11:0]
4-Bit
Extention
44
2-MSB
Reduction FIFO
I [13:0]
Q [13:0]
Interleaved IQ
(122.88Msps)
IQ [13:0]
CMOS
output
DAC
(DAC5672)
TRF3711
Internal PLL
of FPGA
122.88MHz
Clock signal
61.44MHz
15.36MHz
61.44MHz
61.44MHz
122.88MHz
122.88MHz
External
Input
44
I/Q
Differential
Parallel IQ
(61.44Msps)
0 1
16'd0
Selection from GUI
24 24
12 12
61.44MHz
737.28MHz
(61.44 * 12)
Main signal
Control signal
122.88MHz
Gain Selection
Saturation
To 14-bit
ADC
(ADS5282, 12-bit)
122.88MHz
Overview www.ti.com
The FPGA digital processing block diagram is shown in Figure 2.
Figure 2. FPGA Digital Processing Block Diagram
4TSW6011EVM SLWU070B–February 2010–Revised June 2010
Copyright © 2010, Texas Instruments Incorporated

www.ti.com Software Installation
2 Software Installation
2.1 Installation Instructions
Step 1. On the CD provided with the EVM kit, copy the MCRinstaller.exe and
TSW6011GUI_setup_1p00.exe programs to the local drive on the host PC.
Step 2. Click on the MCRinstaller.exe on the host PC to install the required MATLAB®runtime library.
Step 3. Next, run the setup file called TSW6011GUI_setup_1p00.exe. Follow the on-screen
instructions.
Step 4. Once installed, go to the following directory: C:\TSW6011GUI. To start the GUI, double-click
on the TSW6011_control_panel.exe program.
3 EVM Test Configuration
3.1 Test Equipment
The following equipment is required to operate the TSW6011:
●6-VDC power supply (provided)
●Signal generator for input signal (Agilent E4438C or equivalent)
●Signal generator for LO signal (Agilent E4438C or equivalent)
●Spectrum analyzer (Agilent E4440A or equivalent)
●Programming computer
●USB cable (provided)
●RF cables
5
SLWU070B–February 2010–Revised June 2010 TSW6011EVM
Copyright © 2010, Texas Instruments Incorporated

Board Bring Up www.ti.com
3.2 Calibration
The RF cables must be good quality because of the high-frequency signals.
• Measure the insertion loss of the RF input cable and use this value to compensate for the desired input
power.
• Measure the insertion loss of the LO input cable and use this value to compensate for the desired LO
power.
NOTE: Approximately 1 dB of insertion loss for the input traces and balun is on the printed-circuit
board (PCB).
4 Board Bring Up
4.1 Power Up
• Plug one end of the provided +6-VDC power supply to a 110-VAC to 120-VAC source and the output
to J9. (See the board top-view drawing as shown in Figure 3.)
Verify that the jumpers are configured as follows:
JP1: Pins 1 and 2 (applies power to TR371125 Chip_EN input pin).
JP2: Pins 2 and 3 (disables LNA power regulator U13).
JP3: Pins 1 and 2 (enables USB to parallel interface device power regulator U21).
SJP1: Pins 2 and 3 (selects SMA J1 to be the RF input source to the TRF371125).
SJP2: Pins 1 and 2 (selects LNA U2 output).
SJP3: Open (used to select source for LNA U2 GAIN_SEL input).
SJP4: Pins 2 and 3 (enables primary reference source Y2 for the CDCE62005).
SJP5: Open. (used to select source for LNA U8 GAIN_SEL input).
SJP6: Pins 2 and 3 (selects CDCE62005 power down source).
SJP7: Pins 1 and 2 (disables CDCE62005 AUX_IN source Y4).
SJP8: Pins 1 and 2 (selects DAC5672 SLEEP input source).
SJP9: Pins 1 and 2 (selects USB to parallel interface device power source).
SJP10: Pins 2 and 3 (selects DAC5672 input clock source).
• Note that the following LE's are now illuminated:
– D6: +6V power present
– D1: CDC is locked to reference source
– D10: USB powered up
– D11: FPGA is configured
– D7: TR371125 enabled
– D3: DAC input data enabled
– D12: DAC enabled
(This is the board default power-up mode.)
• Plug the USB cable into the host PC and connector J7 on the TSW6011.
• When plugging in the USB cable for the first time, the user is be prompted to install the USB drivers.
– When a pop-up screen opens, select Continue Downloading.
– Follow the on-screen instructions to install the USB drivers.
– If needed, the USB drivers can be accessed in the following directory:
C:\TSW6011GUI\FTD245_Drivers\
6TSW6011EVM SLWU070B–February 2010–Revised June 2010
Copyright © 2010, Texas Instruments Incorporated

www.ti.com Board Bring Up
4.2 Basic RF Test
Follow these steps to perform a basic RF test.
Step 1. Inject a LO signal at J4 at a frequency of 2150 MHz at 0 dBm. Compensate for RF cable
losses, including about 1 dB for input balun and transmission line losses.
Step 2. Since the board default configuration bypasses the two LNAs, inject an RF signal at J1 at
2153 MHz at –15 dBm. Compensate for cable loss, including about 1 dB for input
transmission line losses and balun.
Step 3. Connect a spectrum analyzer to J6.
Step 4. Set up the spectrum analyzer as follows:
• Set span to 20 MHz
• Set center frequency to 30.72 MHz
• Set reference level to –10 dBm
• Set attenuation to 15 dB
• Set sweep time to 2.5 ms
• Set RBW to 300 kHz
• Set VBW to 1 MHz
Figure 3. TSW6011EVM Board Top View
7
SLWU070B–February 2010–Revised June 2010 TSW6011EVM
Copyright © 2010, Texas Instruments Incorporated

BAL
GC1
GC2GC2
2
2
Q_EXT
I_IF
Q_IF
CHA_I
CHA_Q
CHB_I
CHB_Q
DAT1
DAT2
SER_DAT
LCLK
ADC_CLK
20 SERIAL
LVDS DATA
14 CMOS
IQ DATA
DAC
OUT
14
CDCE62005
1P/N
EXT REF IN
0P
2P/N
LNA1
EXT LO
ADC_CLK
61.44 MHz FPGA_CLK = 2 x ADC_CLK
2
T1
2
I_EXT
SPISPI
NC CHC/D_IQ
ACD_CLK
RF_IN
RF_IN
(OPT)
EXT CLK IN EXT REF OUT
TCXO
3
SPI
SPI
3
USB
XFC
SPI
3P
GC2
RF_IN
(OPT)
LDO REGULATORS
TPS76718
TPS76733
TPS76033
TPS76750
TPS70445
+3.3V
+5V
+1.8V
+1.2V
30.72 MHz
ADS5282
2
2
2
2
2
USB
DAC5672
BAL
TRF371125
Digital
Processing
LNA2
3 3
T2
BAL
SERIAL
SERIAL
SERIAL
SERIAL
SERIAL
LCLK
ADC[5]
ADC[2]
ADC[1]
ADC[...]
ADC[6]
[50 MHz to 672. MHz]
Board Bring Up www.ti.com
4.3 Software Operation
When the GUI first starts, the front control panel appears as shown in Figure 4.
Figure 4. TSW6011EVM Software GUI Front Panel
To enable the GUI, the user must click on the button labeled Connect in the upper left-hand corner. If
communication between the GUI and TSW6011 is successful, the button changes to display Disconnect.
Clicking on this button again disconnects the GUI, and the button displays Connect once more. If there is
a problem with the connection, an error message appears, as shown in Figure 5.
Figure 5. GUI Communication Error
If this message appears, make sure the USB cable is installed, the USB drivers are installed, and verify
that the board is powered up. If this problem persists, unplug the USB cable from the EVM, then
reconnect it. If this procedure does not correct the problem, close the GUI and reboot the host computer.
8TSW6011EVM SLWU070B–February 2010–Revised June 2010
Copyright © 2010, Texas Instruments Incorporated

www.ti.com Board Bring Up
4.4 Device Initialization
• Click on the GUI button labeled ADS5282. This opens the ADS5282 control panel as shown in
Figure 6.
Figure 6. ADS5282 Control Panel
• When the control panel opens, the ADS5282 is initialized by the software automatically. The TSW6011
routes external signals from the SMAs to ADC channels 1 and 2. The TR371125 outputs are routed to
channels 5 and 6. Channels 3, 4, 7, and 8 are not used. The following sequence is performed every
time this GUI window is opened:
– Reset the device.
– Power up ADC Channels 1, 2, 5, and 6. Power down ADC channels 3, 4, 7, and 8.
– Set the serial output stream to send MSB first.
– Set the data format to twos complement.
– Set the input clock to differential mode.
• To power down any of the four channels, click on the respective box in the Power Down column.
• To activate the respective channel Low Noise Suppression, click on the box.
• To issue a device reset, click on the Reset ADC button.
• Click on the Xin the upper right-hand corner to close the panel.
9
SLWU070B–February 2010–Revised June 2010 TSW6011EVM
Copyright © 2010, Texas Instruments Incorporated

Board Bring Up www.ti.com
Click on the TRF3711 button of the GUI to open the TR371125 control panel as shown in Figure 7.
Figure 7. TR371125 Control Panel
• When the control panel opens, the TR371125 is initialized by the software automatically. The default
settings are those shown in the control panel when it opens. Every time this panel is opened, the
default values are loaded. This process is reported by the message in red: DEFAULTS RE-LOADED
(as shown in Figure 7).
• Click on the BB Gain field and set the gain to 5.
• Click the Filter Bypass checkbox to bypass the TR371125 LPF internal filter.
10 TSW6011EVM SLWU070B–February 2010–Revised June 2010
Copyright © 2010, Texas Instruments Incorporated