Texas Instruments LMX1204EVM User manual

User’s Guide
LMX1204EVM User's Guide
ABSTRACT
The LMX1204EVM is designed to evaluate the performance of LMX1204. This board consists of an LMX1204
device and an integrated USB2ANY programmer.
The LMX1204 is an ultra-low additive-jitter RF buffer, divider, and multiplier, with integrated SYSREF generation
capability. The device can buffer RF frequencies up to 12.8 GHz, multiply RF outputs up to 6.4 GHz, and
divide outputs by up to 8 GHz. A separate auxiliary clock divider can be used for FPGAs or other logic ICs.
Each RF output (and the logic clock) is paired with a complementary SYSREF output with picosecond-precision
delay-tuning capability, and can be operated as a generator (with synchronization capability across multiple
devices) or as a repeater. The device runs from a single 2.5-V supply, and is programmed by a digital SPI
interface from a 1.8-V, 2.5-V, or 3.3-V bus controller.
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Table of Contents
1 First-Time Setup......................................................................................................................................................................3
1.1 Evaluation Module Contents.............................................................................................................................................. 3
1.2 Evaluation Setup Requirements.........................................................................................................................................3
2 EVM Connections................................................................................................................................................................... 4
2.1 Connection Diagram.......................................................................................................................................................... 4
2.2 Power Supply..................................................................................................................................................................... 4
2.3 Reference Clock.................................................................................................................................................................4
2.4 Output Connections........................................................................................................................................................... 5
2.5 Programming Interface.......................................................................................................................................................5
3 Feature Evaluation..................................................................................................................................................................8
3.1 Buffer, Divider, and Multiplier Modes..................................................................................................................................8
3.2 SYSREF Generation........................................................................................................................................................ 11
3.3 SYSREF Delay Generators..............................................................................................................................................13
4 Schematic..............................................................................................................................................................................14
5 PCB Layout and Layer Stack-Up.........................................................................................................................................16
5.1 PCB Layer Stack-Up........................................................................................................................................................ 16
5.2 PCB Layout...................................................................................................................................................................... 17
6 Bill of Materials..................................................................................................................................................................... 21
A Troubleshooting................................................................................................................................................................... 23
B USB2ANY Firmware Upgrade..............................................................................................................................................25
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1 First-Time Setup
1.1 Evaluation Module Contents
Included within each evaluation kit is:
• One LMX1204 EVM prototype board (HSDC097E1) with integrated USB2ANY controller
• One USB cable
1.2 Evaluation Setup Requirements
At a minimum, evaluation of the buffer mode requires:
• A DC power supply capable of 2.5 V, 2 A
• A high-quality signal source, such as an SMA100B
• A spectrum analyzer or signal analyzer
• A PC with a USB port, running Windows 7 or a more recent version of Windows
• Texas Instruments Clocks and Synthesizers TICS Pro software
Full evaluation requires the following additional hardware:
• A high-speed 4-CH oscilloscope capable of resolving 5-ps step size for SYSREF delay tuning
• A 2-CH arbitrary function generator or other pulse source capable of outputting complementary LVDS pulses
and DC levels (1.25 V ± 0.2 V, differential, into 100-Ω DC load) for triggering SYSREF, SYNCing the dividers,
and determining SYSREF windowing values
• A phase noise analysis system capable of measuring at up to 12.8 GHz
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2 EVM Connections
2.1 Connection Diagram
2-CH Arbitrary
Func

on Generator
1.3V ± 0.2V
High-Quality Signal
Generator
800MHz, +6dBm
Power Supply
2.5V, 2A
4-CH High Speed
Oscilloscope
50

50

GND
50

GND
50

GND
Signal Analyzer
Balun
50

GND
50

50

50

50

50

50

50

GND
50

50

GND
PC with TICS Pro
and device pro

le
installed
50-

termina

ons on unused outputs are op

onal.
Unused outputs can be disabled in soware.
Figure 2-1. EVM Connection Diagram
2.2 Power Supply
Apply 2.5 V to the J27 header. The acceptable supply voltage range at the board is 2.4 V to 2.6 V, and the
device can draw up to 1.3 A during operation, so IR drop in supply cables can be non-negligible. Furthermore,
enabling or disabling various system functions can change the device current by 50% or more. It may be helpful
to attach a multimeter or remote supply sensing leads to the supply voltage test points TP2 and TP3 to ensure
the board voltage is within the acceptable range during operation.
2.3 Reference Clock
Connect the CLKINP SMA connector to a high-quality signal source such as an SMA100B signal generator. Both
CLKIN inputs are terminated internally with 50 Ω to AC-GND (that is, GND connection is formed by an internal
capacitor), so no external termination is required or recommended. The other CLKINN SMA connector may be
optionally installed beforehand so the input can be driven differentially, provided a suitable balun or differential
clock source is available.
The default EVM profile configures the device to evaluate the buffer, multiplier, and divider modes with an
800-MHz CLKIN. This frequency can be modified per the operating range of each functional element if desired.
This EVM setup guide and related plots assume 800-MHz CLKIN.
If a suitable input source is available, connect the SYSREF input SMAs to a differential output source such
as an arbitrary function generator. The EVM connections for the SYSREF input are DC-coupled and provide
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internal 100-Ω termination with several biasing options. At POR, the EVM automatically applies a weak 1.3-V
common mode bias to the SYSREFREQ pins. However, the default EVM profile configures the SYSREF input
for DC-coupled input. In DC-coupled mode, the common mode bias on the SYSREFREQ pins must be
between 1 V and 2 V. The input common mode requirements can be fulfilled with a standard LVDS output
buffer.
For evaluating SYNC mode and SYSREF windowing, it is critical to have a SYSREFREQ input source capable
of consistently meeting setup and hold requirements for a single cycle of the input clock. This can become very
challenging at higher frequencies where setup and hold requirements can be < 50 ps. Another device capable of
picosecond-precision timed pulses, such as LMX2820 or LMX2594, could be used as a reference input to both
CLKIN and SYSREF for evaluating these features.
2.4 Output Connections
Connect any of the CLKOUT SMA connectors to a signal analyzer. All CLKOUT connections are AC-coupled at
the LMX1204EVM and can be connected directly to RF instruments with 0VDC requirements; an additional DC
block is not required. The unused CLKOUT SMA connector must be terminated with a 50-Ω load, or a differential
connection may be used if a balun with a suitable frequency range is available.
If additional hardware such as a high-speed oscilloscope and phase noise analyzer are available, they may also
be connected to the output SMA connectors. Recommended oscilloscope connections include one CLKOUT and
one SYSREF output from the same channel, as well as the one LOGICLK and one LOGISYS output.
Other unused CLKOUT SMA connectors should be terminated with 50-Ω single-ended or 100-Ω differential load,
or alternately should be disabled in software, to minimize unterminated output effects on performance.
2.5 Programming Interface
After the 2.5-V power supply has been connected and power has been applied to the EVM, connect the USB
cable from the PC to the EVM. The USB interface will provide the necessary power to enable the onboard
USB2ANY controller. A firmware update may be required; if prompted, see Appendix B for more details.
Run TICS Pro software and open the device profile:
1. From the top-menu, click Select Device → Clock Distribution with Divider → LMX1204
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2. The device's Main Page will load. The default profile is configured for 800-MHz buffer mode.
3. From the top-menu, click USB communications → Interface. Ensure that the selected interface is
USB2ANY and that the correct controller is selected. To confirm controller selection, click the Identify
button to blink the onboard green communications LED several times in rapid succession; the LED will
return to solid green once completed. After confirming the USB2ANY connection, close the interface window.
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4. Ensure that the main window now shows the USB2ANY connection over SPI.
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3 Feature Evaluation
The following sections describe evaluation of the device features, including buffer mode, multiplier mode, and
divider mode; SYSREF generation and pulse output; SYSREF delay adjustment; SYSREF windowing; and
divider synchronization.
3.1 Buffer, Divider, and Multiplier Modes
From the top-menu, click Default Configuration → 800MHz Buffer Mode. This will automatically load the buffer
mode profile.
Figure 3-1. Loading the Default Configuration
If termination is not applied on all output pins, manually disable the unused outputs using the CHx_EN
fields (to completely power down unused channels) or the CLKOUTx_EN, SYSOUTx_EN, and LOGICLK_EN/
LOGISYS_EN fields (to power down output buffers only). Powering down unused channels greatly reduces
current consumption, and for the logic clocks in particular can reduce spurious interference.
After the profile is loaded and any changes required have been made, the signal analyzer should see an
800-MHz signal at around +6-dBm single-ended, or +9-dBm differential.
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Figure 3-2. 800-MHz Buffer Mode Signal Analyzer Plot
To activate the multiplier or the divider, change the CLK_MUX field to specify divider or multiplier modes, and
change the CLK_DIV and CLK_MULT fields to specify the frequency scaling factor. To ensure the device cleanly
enters each mode, first the desired configuration should be prepared in the GUI, then from the User Controls
page the device should be reset by toggling the RESET field, and finally the registers should be reloaded using
the USB Communications → Write All Registers menu option, or by pressing the accelerator keys CTRL + L.
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Figure 3-3. 3200-MHz Multiplier x4 Mode Signal Analyzer Plot
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Figure 3-4. 200-MHz Divide-by-4 Mode Signal Analyzer Plot
3.2 SYSREF Generation
The SYSREF generation circuit includes a SYSREF pre-divider and post-divider, a pulser with programmable
pulse quantity, and a repeater mode bypass. The SYSREF generator modes re-time the SYSREF signal to the
output clock, ensuring the SYSREF output is close to the falling edge of the clock output with default delay
settings. Repeater mode timing is solely determined by the propagation delay of the device.
To activate the SYSREF generation circuit, the following conditions must be satisfied:
• SRREQ_MODE field must be set to SYSREFREQ mode
• SYSREF_MODE field must be set to the appropriate condition: Continuous, Pulser, or Repeater
• In generator modes (continuous or pulser), FINTERPOLATOR % FSYSREF = 0 must be ensured.
• SYSREF_DLY_BYP field must be configured appropriately for generator or repeater modes (a GUI autoset
condition normally ensures this whenever SYSREF_MODE is set)
• SRREQ_VCM field should be set to DC-coupled mode for continuous or pulsed generator output. In repeater
mode output, the SYSREF input may be AC- or DC-coupled and SRREQ_VCM should be set accordingly.
• For continuous mode, a HIGH signal must be seen on SYSREFREQ pins continuously. For pulsed generator
mode, a LOW→HIGH transition must be seen on SYSREFREQ pins to trigger the pulser. For repeater mode,
the output will follow the input state.
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Figure 3-5. 800-MHz Buffer Mode With SYSREF
The SYSREF generator frequency is based on the CLKIN frequency, but the re-timing happens at the output
frequency; consequently, the SYSREF generator still matches to the falling edge of the clock input even for
multiplier and divider modes.
Figure 3-6. 3200-MHz Multiplier Mode With CLKOUT, LOGICLK, and SYSREF
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3.3 SYSREF Delay Generators
In generator modes, the SYSREF can be delayed by picosecond-size steps to more closely meet setup and hold
requirements for high-frequency clock outputs. A delay divider, SYSREF_DLY_DIV, generates the interpolator
frequency fINTERPOLATOR, which is usually in the range of 400 MHz to 800 MHz. This interpolator frequency is
further subdivided into 512 delay codes, allowing approximately 2.5-ps to 5-ps delay steps across most of the
CLKIN frequency range.
Each channel has its own delay codes which can be entered. The delay code algorithm is documented in
the data sheet. To simplify delay calculation, the GUI provides an estimated relative delay: enter the relative
delay, and the GUI will calculate the correct step values to achieve the requested delay as closely as possible.
Alternately, the register-based delay fields can be stepped through or programmed to achieve the same result.
Figure 3-7. SYSREF Delay, in 5-Code Steps
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4 Schematic
Figure 4-1. Schematic - LMX1204
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Figure 4-2. Schematic - USB2ANY
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5 PCB Layout and Layer Stack-Up
5.1 PCB Layer Stack-Up
The top layer is 1-oz. copper.
Top layer
RO4350B (Er = 3.66)
RF GND layer
FR4 (Er = 4.2)
FR4 (Er = 4.2)
Bottom layer
62 mil
Signal GND layer
10 mil
Figure 5-1. PCB Layer Stack-Up
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5.2 PCB Layout
Figure 5-2. PCB Layer Plot - Top Layer
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Figure 5-3. PCB Layer Plot - Layer 2 (RF GND)
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Figure 5-4. PCB Layer Plot - Layer 3 (Signal GND)
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Figure 5-5. PCB Layer Plot - Bottom Layer
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