Texas Instruments CC430F6137 User manual

ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
CC430F5137, CC430F5135, CC430F5133
www.ti.com SLAS554H –MAY 2009–REVISED SEPTEMBER 2013
MSP430™ SoC With RF Core
Check for Samples: CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125,CC430F5137,CC430F5135,CC430F5133
1FEATURES
23• True System-on-Chip (SoC) for Low-Power – Embedded Emulation Module (EEM)
Wireless Communication Applications • High-Performance Sub-1-GHz RF Transceiver
• Wide Supply Voltage Range: Core
3.6 V Down to 1.8 V – Same as in CC1101
• Ultralow-Power Consumption: – Wide Supply Voltage Range: 2.0 V to 3.6 V
– CPU Active Mode (AM): 160 µA/MHz – Frequency Bands: 300 MHz to 348 MHz,
– Standby Mode (LPM3 RTC Mode): 2.0 µA 389 MHz to 464 MHz, and 779 MHz to
928 MHz
– Off Mode (LPM4 RAM Retention): 1.0 µA – Programmable Data Rate From 0.6 kBaud
– Radio in RX: 15 mA, 250 kbps, 915 MHz to 500 kBaud
• MSP430 System and Peripherals – High Sensitivity (–117 dBm at 0.6 kBaud,
– 16-Bit RISC Architecture, Extended –111 dBm at 1.2 kBaud, 315 MHz,
Memory, up to 20-MHz System Clock 1% Packet Error Rate)
– Wake Up From Standby Mode in Less – Excellent Receiver Selectivity and Blocking
Than 6 µs Performance
– Flexible Power-Management System With – Programmable Output Power Up to
SVS and Brownout +12 dBm for All Supported Frequencies
– Unified Clock System With FLL – 2-FSK, 2-GFSK, and MSK Supported as
– 16-Bit Timer TA0, Timer_A With Five Well as OOK and Flexible ASK Shaping
Capture/Compare Registers – Flexible Support for Packet-Oriented
– 16-Bit Timer TA1, Timer_A With Three Systems: On-Chip Support for Sync Word
Capture/Compare Registers Detection, Address Check, Flexible Packet
– Hardware Real-Time Clock (RTC) Length, and Automatic CRC Handling
– Two Universal Serial Communication – Support for Automatic Clear Channel
Interfaces Assessment (CCA) Before Transmitting (for
– USCI_A0 Supports UART, IrDA, SPI Listen-Before-Talk Systems)
– USCI_B0 Supports I2C, SPI – Digital RSSI Output
– 12-Bit Analog-to-Digital Converter (ADC) – Suited for Systems Targeting Compliance
With Internal Reference, Sample-and-Hold, With EN 300 220 (Europe) and
and Autoscan Features (CC430F613x and FCC CFR Part 15 (US)
CC430F513x Only) – Suited for Systems Targeting Compliance
– Comparator With Wireless M-Bus Standard EN
13757‑‑4:2005
– Integrated LCD Driver With Contrast
Control for up to 96 Segments – Support for Asynchronous and
(CC430F61xx Only) Synchronous Serial Receive or Transmit
Mode for Backward Compatibility With
– 128-Bit AES Security Encryption and Existing Radio Communication Protocols
Decryption Coprocessor •Table 1 Summarizes Family Members
– 32-Bit Hardware Multiplier • For Complete Module Descriptions, See the
– Three-Channel Internal DMA CC430 Family User's Guide (SLAU259)
– Serial Onboard Programming, No External
Programming Voltage Needed
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2MSP430 is a trademark of Texas Instruments.
3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2009–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
CC430F5137, CC430F5135, CC430F5133
SLAS554H –MAY 2009–REVISED SEPTEMBER 2013 www.ti.com
APPLICATIONS
• Wireless Analog and Digital Sensor Systems
• Heat Cost Allocators
• Thermostats
• AMR or AMI Metering
• Smart Grid Wireless Networks
DESCRIPTION
The Texas Instruments CC430 family of ultralow-power microcontroller system-on-chip (SoC) with integrated RF
transceiver cores consists of several devices featuring different sets of peripherals targeted for a wide range of
applications. The architecture, combined with five low-power modes, is optimized to achieve extended battery life
in portable measurement applications. The device features the powerful MSP430 16-bit RISC CPU, 16-bit
registers, and constant generators that contribute to maximum code efficiency.
The CC430 family provides a tight integration between the microcontroller core, its peripherals, software, and the
RF transceiver, making these true SoC solutions easy to use as well as improving performance.
The CC430F61xx series are microcontroller SoC configurations that combine the excellent performance of the
state-of-the-art CC1101 sub-1-GHz RF transceiver with the MSP430 CPUXV2, up to 32KB of in-system
programmable flash memory, up to 4KB of RAM, two 16-bit timers, a high-performance 12-bit analog-to-digital
converter (ADC) with eight external inputs plus internal temperature and battery sensors on CC430F613x
devices, a comparator, universal serial communication interfaces (USCIs), a 128-bit AES security accelerator, a
hardware multiplier, a DMA, a real-time clock (RTC) module with alarm capabilities, an LCD driver, and up to
44 I/O pins.
The CC430F513x series are microcontroller SoC configurations that combine the excellent performance of the
state-of-the-art CC1101 sub-1-GHz RF transceiver with the MSP430 CPUXV2, up to 32KB of in-system
programmable flash memory, up to 4KB of RAM, two 16-bit timers, a high performance 12-bit ADC with six
external inputs plus internal temperature and battery sensors, a comparator, universal serial communication
interfaces (USCIs), a 128-bit AES security accelerator, a hardware multiplier, a DMA, an RTC module with alarm
capabilities, and up to 30 I/O pins.
Typical applications for these devices include wireless analog and digital sensor systems, heat cost allocators,
thermostats, metering (AMR or AMI), and smart grid wireless networks.
Table 1 summarizes the available family members.
For complete module descriptions, see the CC430 Family User's Guide (SLAU259).
2Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: CC430F6137 CC430F6135 CC430F6127 CC430F6126 CC430F6125 CC430F5137
CC430F5135 CC430F5133

ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
CC430F5137, CC430F5135, CC430F5133
www.ti.com SLAS554H –MAY 2009–REVISED SEPTEMBER 2013
Table 1. Family Members(1)(2)
USCI
Program Package
Channel A: Channel B:
Device SRAM (KB) Timer_A(3) LCD_B(4) ADC12_A(4) Comp_B I/O
(KB) Type
UART, LIN, SPI, I2C
IrDA, SPI
8 ext,
CC430F6137 32 4 5, 3 96 seg 1 1 8 ch. 44 64 RGC
4 int ch.
8 ext,
CC430F6135 16 2 5, 3 96 seg 1 1 8 ch. 44 64 RGC
4 int ch.
CC430F6127 32 4 5, 3 96 seg 1 1 n/a 8 ch. 44 64 RGC
CC430F6126 32 2 5, 3 96 seg 1 1 n/a 8 ch. 44 64 RGC
CC430F6125 16 2 5, 3 96 seg 1 1 n/a 8 ch. 44 64 RGC
6 ext,
CC430F5137 32 4 5, 3 n/a 1 1 6 ch. 30 48 RGZ
4 int ch.
6 ext,
CC430F5135 16 2 5, 3 n/a 1 1 6 ch. 30 48 RGZ
4 int ch.
6 ext,
CC430F5133 8 2 5, 3 n/a 1 1 6 ch. 30 48 RGZ
4 int ch.
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 5, 3 would represent two instantiations of Timer_A, the first
instantiation having 5 and the second instantiation having 3 capture compare registers and PWM output generators, respectively.
(4) n/a = not available
Copyright © 2009–2013, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: CC430F6137 CC430F6135 CC430F6127 CC430F6126 CC430F6125 CC430F5137
CC430F5135 CC430F5133

RAM
4kB
2kB
Power
Mgmt
LDO
SVM/SVS
Brownout
SYS
TA0
5 CC
Registers
EEM
(S: 3+1)
RTC_A
Comp_B
Flash
32kB
16kB
SMCLK
ACLK
MDB
MAB
XOUTXIN
Spy-Bi-
Wire
CRC16
Bus
Cntrl
Logic
MAB
MDB
MAB
MDB
MCLK
USCI_A0
(UART,
IrDA, SPI)
USCI_B0
(SPI, I2C)
LCD_B
96
Segments
1,2,3,4
Mux
I/O Ports
P1/P2
2x8 I/Os
PA
1x16 I/Os
P1.x/P2.x
2x8
I/O Ports
P3/P4
2x8 I/Os
PB
1x16 I/Os
P3.x/P4.x
2x8
I/O Ports
P5
1x8 I/Os
P5.x
1x8
AES128
Security
En-/De-
cryption
RF_XOUTRF_XIN
RF_NRF_P
TA1
3 CC
Registers
MODEM
RF/ANALOG
TX & RX
Frequency
Synthesizer
CPU Interface
Packet
Handler
Digital RSSI
Carrier Sense
PQI / LQI
CCA
Sub-1GHz
Radio
(CC1101)
MPY32
ADC12
(32kHz) (26MHz)
Unified
Clock
System
CPUXV2
incl. 16
Registers
JTAG
Interface
DMA
Controller
3 Channel
Port
Mapping
Controller
Watch-
dog
REF
Voltage
Reference
ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
CC430F5137, CC430F5135, CC430F5133
SLAS554H –MAY 2009–REVISED SEPTEMBER 2013 www.ti.com
CC430F613x Functional Block Diagram
4Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: CC430F6137 CC430F6135 CC430F6127 CC430F6126 CC430F6125 CC430F5137
CC430F5135 CC430F5133

RGC PACKAGE
(TOP VIEW)
CC430F613x
P3.7/PM_SMCLK/S17 P2.0/PM_CBOUT1/PM_TA1CLK/CB0/A0
17
64
P3.6/PM_RFGDO1/S16 P2.1/PM_TA1CCR0A/CB1/A1
18
63
P3.5/PM_TA0CCR4A/S15 P2.2/PM_TA1CCR1A/CB2/A2
19
62
P2.3/PM_TA1CCR2A/CB3/A3
P3.4/PM_TA0CCR3A/S14
20
61
P2.4/PM_RTCCLK/CB4/A4/VREF-/VeREF-
P3.3/PM_TA0CCR2A/S13
21
60
P2.5/ /CB5/A5PM_SVMOUT /VREF+/VeREF+
P3.2/PM_TA0CCR1A/S12
22
59
DVCC
P4.4/S6
29
52
RST/NMI/SBWTDIO
P4.3/S5
30
51
TEST/SBWTCK
P4.2/S4
31
50
PJ.3/TCK
P4.1/S3
32
49
P2.6/PM_ACLK/CB6/A6
P3.1/PM_TA0CCR0A/S11
23
58
P2.7/ /CB7/A7PM_ADC12CLK/PM_DMAE0
P3.0/PM_CBOUT0/PM_TA0CLK/S10
24
57
AVCC
DVCC
25
56
P5.0/XIN
P4.7/S9
26
55
P5.1/XOUT
P4.6/S8
27
54
AVSS
P4.5/S7
28
53
P4.0/S2P1.0/PM_RFGDO0/S18 3316
P5.3/S1
P1.1/PM_RFGDO2/S19 3415
P5.2/S0
P1.2/PM_UCB0SOMI/PM_UCB0SCL/S20 35
14
RF_XINP1.3/PM_UCB0SIMO/PM_UCB0SDA/S21 3613
RF_XOUTP1.4/PM_UCB0CLK/PM_UCA0STE/S22 37
12
AVCC_RFDVCC 38
11
GUARD
LCDCAP/R33 45
4
PJ.0/TDO
P1.5/PM_UCA0RXD/PM_UCA0SOMI/R23 463
PJ.1/TDI/TCLK
P1.6/PM_UCA0TXD/PM_UCA0SIMO/R13/LCDREF 472
PJ.2/TMS
P1.7/PM_UCA0CLK/PM_UCB0STE/R03 48
1
AVCC_RF VCORE 3910
RF_P
P5.4/S23 409
RF_NP5.5/COM3/S24 41
8
AVCC_RFP5.6/COM2/S25 42
7
AVCC_RF
P5.7/COM1/S26 436
R_BIAS
COM0 44
5
VSS
Exposed die
attached pad
ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
CC430F5137, CC430F5135, CC430F5133
www.ti.com SLAS554H –MAY 2009–REVISED SEPTEMBER 2013
NOTE: The secondary digital functions on ports P1, P2, and P3 are fully mappable. This pinout shows only the default
mapping. See Table 9 for details.
CAUTION: The LCDCAP/R33 must be connected to VSS if not used.
Copyright © 2009–2013, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: CC430F6137 CC430F6135 CC430F6127 CC430F6126 CC430F6125 CC430F5137
CC430F5135 CC430F5133

RAM
4kB
2kB
2kB
Power
Mgmt
LDO
SVM/SVS
Brownout
TA0
5 CC
Registers
EEM
(S: 3+1)
RTC_A
Comp_B
Flash
32kB
32kB
16kB
SMCLK
ACLK
MDB
MAB
XOUTXIN
Spy-Bi-
Wire
CRC16
Bus
Cntrl
Logic
MAB
MDB
MAB
MDB
MCLK
USCI_A0
(UART,
IrDA, SPI)
USCI_B0
(SPI, I2C)
LCD_B
96
Segments
1,2,3,4
Mux
I/O Ports
P1/P2
2x8 I/Os
PA
1x16 I/Os
P1.x/P2.x
2x8
I/O Ports
P3/P4
2x8 I/Os
PB
1x16 I/Os
P3.x/P4.x
2x8
I/O Ports
P5
1x8 I/Os
P5.x
1x8
AES128
Security
En-/De-
cryption
RF_XOUTRF_XIN
RF_NRF_P
TA1
3 CC
Registers
MODEM
RF/ANALOG
TX & RX
Frequency
Synthesizer
CPU Interface
Packet
Handler
Digital RSSI
Carrier Sense
PQI / LQI
CCA
Sub-1GHz
Radio
(CC1101)
MPY32
(32kHz) (26MHz)
Unified
Clock
System
JTAG
Interface
DMA
Controller
3 Channel
SYS
Port
Mapping
Controller
Watch-
dog
REF
Voltage
Reference
CPUXV2
incl. 16
Registers
ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
CC430F5137, CC430F5135, CC430F5133
SLAS554H –MAY 2009–REVISED SEPTEMBER 2013 www.ti.com
CC430F612x Functional Block Diagram
6Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: CC430F6137 CC430F6135 CC430F6127 CC430F6126 CC430F6125 CC430F5137
CC430F5135 CC430F5133

RGC PACKAGE
(TOP VIEW)
CC430F612x
P3.7/PM_SMCLK/S17 P2.0/PM_CBOUT1/PM_TA1CLK/CB0
17
64
P3.6/PM_RFGDO1/S16 P2.1/PM_TA1CCR0A/CB1
18
63
P3.5/PM_TA0CCR4A/S15 P2.2/PM_TA1CCR1A/CB2
19
62
P2.3/PM_TA1CCR2A/CB3
P3.4/PM_TA0CCR3A/S14
20
61
P2.4/PM_RTCCLK/CB4
P3.3/PM_TA0CCR2A/S13
21
60
P2.5/ /CB5PM_SVMOUT
P3.2/PM_TA0CCR1A/S12
22
59
DVCC
P4.4/S6
29
52
RST/NMI/SBWTDIO
P4.3/S5
30
51
TEST/SBWTCK
P4.2/S4
31
50
PJ.3/TCK
P4.1/S3
32
49
P2.6/PM_ACLK/CB6
P3.1/PM_TA0CCR0A/S11
23
58
P2.7/ /CB7PM_DMAE0
P3.0/PM_CBOUT0/PM_TA0CLK/S10
24
57
AVCC
DVCC
25
56
P5.0/XIN
P4.7/S9
26
55
P5.1/XOUT
P4.6/S8
27
54
AVSS
P4.5/S7
28
53
P4.0/S2P1.0/PM_RFGDO0/S18 3316
P5.3/S1
P1.1/PM_RFGDO2/S19 3415
P5.2/S0
P1.2/PM_UCB0SOMI/PM_UCB0SCL/S20 35
14
RF_XINP1.3/PM_UCB0SIMO/PM_UCB0SDA/S21 3613
RF_XOUTP1.4/PM_UCB0CLK/PM_UCA0STE/S22 37
12
AVCC_RFDVCC 38
11
GUARD
LCDCAP/R33 45
4
PJ.0/TDO
P1.5/PM_UCA0RXD/PM_UCA0SOMI/R23 463
PJ.1/TDI/TCLK
P1.6/PM_UCA0TXD/PM_UCA0SIMO/R13/LCDREF 472
PJ.2/TMS
P1.7/PM_UCA0CLK/PM_UCB0STE/R03 48
1
AVCC_RF
VCORE
3910
RF_P
P5.4/S23 409
RF_NP5.5/COM3/S24 41
8
AVCC_RFP5.6/COM2/S25 42
7
AVCC_RF
P5.7/COM1/S26 436
R_BIAS
COM0 44
5
VSS
Exposed die
attached pad
ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
CC430F5137, CC430F5135, CC430F5133
www.ti.com SLAS554H –MAY 2009–REVISED SEPTEMBER 2013
NOTE: The secondary digital functions on ports P1, P2, and P3 are fully mappable. This pinout shows only the default
mapping. See Table 9 for details.
CAUTION: The LCDCAP/R33 must be connected to VSS if not used.
Copyright © 2009–2013, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Links: CC430F6137 CC430F6135 CC430F6127 CC430F6126 CC430F6125 CC430F5137
CC430F5135 CC430F5133

RAM
4kB
2kB
Power
Mgmt
LDO
SVM/SVS
Brownout
TA0
5 CC
Registers
EEM
(S: 3+1)
RTC_A
Comp_B
Flash
32
kB
16kB
8kB
SMCLK
ACLK
MDB
MAB
XOUTXIN
Spy-Bi-
Wire
CRC16
Bus
Cntrl
Logic
MAB
MDB
MAB
MDB
MCLK
USCI_A0
(UART,
IrDA, SPI)
USCI_B0
(SPI, I2C)
I/O Ports
P1/P2
2x8 I/Os
PA
1x16 I/Os
P1.x/P2.x
2x8
I/O Ports
P3
1x8 I/Os
P3.x
1x8
I/O Ports
P5
1x2 I/Os
P5.x
1x2
AES128
Security
En-/De-
cryption
RF_XOUTRF_XIN
RF_NRF_P
MODEM
RF/ANALOG
TX & RX
Frequency
Synthesizer
CPU Interface
Packet
Handler
Digital RSSI
Carrier Sense
PQI / LQI
CCA
Sub-1GHz
Radio
(CC1101)
MPY32
ADC12
(32kHz) (26MHz)
Unified
Clock
System
JTAG
Interface
DMA
Controller
3 Channel
SYS
Port
Mapping
Controller
Watch-
dog
REF
Voltage
Reference
CPUXV2
incl. 16
Registers
TA1
3 CC
Registers
ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
CC430F5137, CC430F5135, CC430F5133
SLAS554H –MAY 2009–REVISED SEPTEMBER 2013 www.ti.com
CC430F513x Functional Block Diagram
8Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: CC430F6137 CC430F6135 CC430F6127 CC430F6126 CC430F6125 CC430F5137
CC430F5135 CC430F5133

RGZ PACKAGE
(TOP VIEW)
12
11
4
3
2
1
10
9
8
7
6
5
13 14 15 16 17 18 19 20 21 22 23 24
25
26
27
28
29
30
31
32
33
34
35
36
48 47 46 45 44 43 42 41 40 39 38 37
P1.1/PM_RFGDO2
P1.2/PM_UCB0SOMI/PM_UCB0SCL
P1.7/PM_UCA0CLK/PM_UCB0STE
P2.0/PM_CBOUT1/PM_TA1CLK/CB0/A0
P2.1/PM_TA1CCR0A/CB1/A1
P2.2/PM_TA1CCR1A/CB2/A2
P1.3/PM_UCB0SIMO/PM_UCB0SDA
P1.4/PM_UCB0CLK/PM_UCA0STE
DVCC
VCORE
P1.5/PM_UCA0RXD/PM_UCA0SOMI
P1.6/PM_UCA0TXD/PM_UCA0SIMO
RF_XIN
RF_XOUT
AVCC_RF
GUARD
PJ.0/TDO
PJ.1/TDI/TCLK
AVCC_RF
RF_P
RF_N
AVCC_RF
AVCC_RF
R_BIAS
P2.3/PM_TA1CCR2A/CB3/A3 P2.4/PM_RTCCLK/CB4/A4/VREF-/VeREF- RST/NMI/SBWTDIO TEST/SBWTCK PJ.3/TCK PJ.2/TMS P2.5/PM_SVMOUT/CB5/A5/VREF+/VeREF+
AVCC P5.0/XIN
P5.1/XOUT AVSS
DVCC
P1.0/PM_RFGDO0
P3.7/PM_SMCLK
P3.6/PM_RFGDO1
P3.5/PM_TA0CCR4A
P3.4/PM_TA0CCR3A
P3.3/PM_TA0CCR2A
P3.2/PM_TA0CCR1A
P3.1/PM_TA0CCR0A
P3.0/PM_CBOUT0/PM_TA0CLK
DVCC
P2.7/PM_ADC12CLK/PM_DMAE0
P2.6/PM_ACLK
VSS
Exposed die
attached pad
CC430F513x
ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
CC430F5137, CC430F5135, CC430F5133
www.ti.com SLAS554H –MAY 2009–REVISED SEPTEMBER 2013
NOTE: The secondary digital functions on ports P1, P2, and P3 are fully mappable. This pinout shows only the default
mapping. See Table 9 for details.
Copyright © 2009–2013, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Links: CC430F6137 CC430F6135 CC430F6127 CC430F6126 CC430F6125 CC430F5137
CC430F5135 CC430F5133

ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
CC430F5137, CC430F5135, CC430F5133
SLAS554H –MAY 2009–REVISED SEPTEMBER 2013 www.ti.com
Table 2. CC430F613x and CC430F612x Terminal Functions
TERMINAL I/O(1) DESCRIPTION
NAME NO.
General-purpose digital I/O with port interrupt and mappable secondary function
P1.7/ PM_UCA0CLK/ 1 I/O Default mapping: USCI_A0 clock input/output; USCI_B0 SPI slave transmit enable
PM_UCB0STE/ R03 Input/output port of lowest analog LCD voltage (V5)
General-purpose digital I/O with port interrupt and mappable secondary function
P1.6/ PM_UCA0TXD/ Default mapping: USCI_A0 UART transmit data; USCI_A0 SPI slave in master out
2 I/O
PM_UCA0SIMO/ R13/LCDREF Input/output port of third most positive analog LCD voltage (V3 or V4)
External reference voltage input for regulated LCD voltage
General-purpose digital I/O with port interrupt and mappable secondary function
P1.5/ PM_UCA0RXD/ 3 I/O Default mapping: USCI_A0 UART receive data; USCI_A0 SPI slave out master in
PM_UCA0SOMI/ R23 Input/output port of second most positive analog LCD voltage (V2)
LCD capacitor connection
LCDCAP/ R33 4 I/O Input/output port of most positive analog LCD voltage (V1)
CAUTION: Must be connected to VSS if not used.
COM0 5 O LCD common output COM0 for LCD backplane
General-purpose digital I/O
P5.7/ COM1/ S26 6 I/O LCD common output COM1 for LCD backplane
LCD segment output S26
General-purpose digital I/O
P5.6/ COM2/ S25 7 I/O LCD common output COM2 for LCD backplane
LCD segment output S25
General-purpose digital I/O
P5.5/ COM3/ S24 8 I/O LCD common output COM3 for LCD backplane
LCD segment output S24
General-purpose digital I/O
P5.4/ S23 9 I/O LCD segment output S23
VCORE 10 Regulated core power supply
DVCC 11 Digital power supply
General-purpose digital I/O with port interrupt and mappable secondary function
P1.4/ PM_UCB0CLK/ 12 I/O Default mapping: USCI_B0 clock input/output; USCI_A0 SPI slave transmit enable
PM_UCA0STE/ S22 LCD segment output S22
General-purpose digital I/O with port interrupt and mappable secondary function
P1.3/ PM_UCB0SIMO/ 13 I/O Default mapping: USCI_B0 SPI slave in master out; USCI_B0 I2C data
PM_UCB0SDA/ S21 LCD segment output S21
General-purpose digital I/O with port interrupt and mappable secondary function
P1.2/ PM_UCB0SOMI/ 14 I/O Default mapping: USCI_B0 SPI slave out master in; UCSI_B0 I2C clock
PM_UCB0SCL/ S20 LCD segment output S20
General-purpose digital I/O with port interrupt and mappable secondary function
P1.1/ PM_RFGDO2/ S19 15 I/O Default mapping: Radio GDO2 output
LCD segment output S19
General-purpose digital I/O with port interrupt and mappable secondary function
P1.0/ PM_RFGDO0/ S18 16 I/O Default mapping: Radio GDO0 output
LCD segment output S18
General-purpose digital I/O with mappable secondary function
P3.7/ PM_SMCLK/ S17 17 I/O Default mapping: SMCLK output
LCD segment output S17
General-purpose digital I/O with mappable secondary function
P3.6/ PM_RFGDO1/ S16 18 I/O Default mapping: Radio GDO1 output
LCD segment output S16
General-purpose digital I/O with mappable secondary function
P3.5/ PM_TA0CCR4A/ S15 19 I/O Default mapping: TA0 CCR4 compare output or capture input
LCD segment output S15
General-purpose digital I/O with mappable secondary function
P3.4/ PM_TA0CCR3A/ S14 20 I/O Default mapping: TA0 CCR3 compare output or capture input
LCD segment output S14
General-purpose digital I/O with mappable secondary function
P3.3/ PM_TA0CCR2A/ S13 21 I/O Default mapping: TA0 CCR2 compare output or capture input
LCD segment output S13
(1) I = input, O = output
10 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: CC430F6137 CC430F6135 CC430F6127 CC430F6126 CC430F6125 CC430F5137
CC430F5135 CC430F5133

ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
CC430F5137, CC430F5135, CC430F5133
www.ti.com SLAS554H –MAY 2009–REVISED SEPTEMBER 2013
Table 2. CC430F613x and CC430F612x Terminal Functions (continued)
TERMINAL I/O(1) DESCRIPTION
NAME NO.
General-purpose digital I/O with mappable secondary function
P3.2/ PM_TA0CCR1A/ S12 22 I/O Default mapping: TA0 CCR1 compare output or capture input
LCD segment output S12
General-purpose digital I/O with mappable secondary function
P3.1/ PM_TA0CCR0A/ S11 23 I/O Default mapping: TA0 CCR0 compare output or capture input
LCD segment output S11
General-purpose digital I/O with mappable secondary function
P3.0/ PM_CBOUT0/PM_TA0CLK/ 24 I/O Default mapping: Comparator_B output; TA0 clock input
S10 LCD segment output S10
DVCC 25 Digital power supply
General-purpose digital I/O
P4.7/ S9 26 I/O LCD segment output S9
General-purpose digital I/O
P4.6/ S8 27 I/O LCD segment output S8
General-purpose digital I/O
P4.5/ S7 28 I/O LCD segment output S7
General-purpose digital I/O
P4.4/ S6 29 I/O LCD segment output S6
General-purpose digital I/O
P4.3/ S5 30 I/O LCD segment output S5
General-purpose digital I/O
P4.2/ S4 31 I/O LCD segment output S4
General-purpose digital I/O
P4.1/ S3 32 I/O LCD segment output S3
General-purpose digital I/O
P4.0/ S2 33 I/O LCD segment output S2
General-purpose digital I/O
P5.3/ S1 34 I/O LCD segment output S1
General-purpose digital I/O
P5.2/ S0 35 I/O LCD segment output S0
RF_XIN 36 I Input terminal for RF crystal oscillator, or external clock input
RF_XOUT 37 O Output terminal for RF crystal oscillator
AVCC_RF 38 Radio analog power supply
AVCC_RF 39 Radio analog power supply
RF Positive RF input to LNA in receive mode
RF_P 40 I/O Positive RF output from PA in transmit mode
RF Negative RF input to LNA in receive mode
RF_N 41 I/O Negative RF output from PA in transmit mode
AVCC_RF 42 Radio analog power supply
AVCC_RF 43 Radio analog power supply
RBIAS 44 External bias resistor for radio reference current
GUARD 45 Power supply connection for digital noise isolation
General-purpose digital I/O
PJ.0/ TDO 46 I/O Test data output port
General-purpose digital I/O
PJ.1/ TDI/ TCLK 47 I/O Test data input or test clock input
General-purpose digital I/O
PJ.2/ TMS 48 I/O Test mode select
General-purpose digital I/O
PJ.3/ TCK 49 I/O Test clock
Test mode pin – select digital I/O on JTAG pins
TEST/ SBWTCK 50 I Spy-Bi-Wire input clock
Copyright © 2009–2013, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Links: CC430F6137 CC430F6135 CC430F6127 CC430F6126 CC430F6125 CC430F5137
CC430F5135 CC430F5133

ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
CC430F5137, CC430F5135, CC430F5133
SLAS554H –MAY 2009–REVISED SEPTEMBER 2013 www.ti.com
Table 2. CC430F613x and CC430F612x Terminal Functions (continued)
TERMINAL I/O(1) DESCRIPTION
NAME NO.
Reset input active low
RST/NMI/ SBWTDIO 51 I/O Non-maskable interrupt input
Spy-Bi-Wire data input/output
DVCC 52 Digital power supply
AVSS 53 Analog ground supply for ADC12
General-purpose digital I/O
P5.1/ XOUT 54 I/O Output terminal of crystal oscillator XT1
General-purpose digital I/O
P5.0/ XIN 55 I/O Input terminal for crystal oscillator XT1
AVCC 56 Analog power supply
General-purpose digital I/O with port interrupt and mappable secondary function
P2.7/ PM_ADC12CLK/ Default mapping: ADC12CLK output; DMA external trigger input
57 I/O
PM_DMAE0/ CB7 (/A7) Comparator_B input CB7
Analog input A7 – 12-bit ADC (CC430F613x only)
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: ACLK output
P2.6/ PM_ACLK/ CB6 (/A6) 58 I/O Comparator_B input CB6
Analog input A6 – 12-bit ADC (CC430F613x only)
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: SVM output
P2.5/ PM_SVMOUT/ CB5 Comparator_B input CB5
59 I/O
(/A5/ VREF+/ VeREF+) Analog input A5 – 12-bit ADC (CC430F613x only)
Output of reference voltage to the ADC (CC430F613x only)
Input for an external reference voltage to the ADC (CC430F613x only)
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: RTCCLK output
P2.4/ PM_RTCCLK/ CB4 Comparator_B input CB4
60 I/O
(/A4/ VREF-/ VeREF-) Analog input A4 – 12-bit ADC (CC430F613x only)
Negative terminal for the ADC's reference voltage for both sources, the internal
reference voltage, or an external applied reference voltage (CC430F613x only)
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: TA1 CCR2 compare output or capture input
P2.3/ PM_TA1CCR2A/ CB3 (/A3) 61 I/O Comparator_B input CB3
Analog input A3 – 12-bit ADC (CC430F613x only)
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: TA1 CCR1 compare output or capture input
P2.2/ PM_TA1CCR1A/ CB2 (/A2) 62 I/O Comparator_B input CB2
Analog input A2 – 12-bit ADC (CC430F613x only)
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: TA1 CCR0 compare output or capture input
P2.1/PM_TA1CCR0A/CB1(/A1) 63 I/O Comparator_B input CB1
Analog input A1 – 12-bit ADC (CC430F613x only)
General-purpose digital I/O with port interrupt and mappable secondary function
P2.0/ PM_CBOUT1/ PM_TA1CLK/ Default mapping: Comparator_B output; TA1 clock input
64 I/O
CB0 (/A0) Comparator_B input CB0
Analog input A0 – 12-bit ADC (CC430F613x only)
Ground supply
VSS - Exposed die attach pad The exposed die attach pad must be connected to a solid ground plane as this is
the ground connection for the chip.
12 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: CC430F6137 CC430F6135 CC430F6127 CC430F6126 CC430F6125 CC430F5137
CC430F5135 CC430F5133

ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
CC430F5137, CC430F5135, CC430F5133
www.ti.com SLAS554H –MAY 2009–REVISED SEPTEMBER 2013
Table 3. CC430F513x Terminal Functions
TERMINAL I/O(1) DESCRIPTION
NAME NO.
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: TA1 CCR1 compare output or capture input
P2.2/ PM_TA1CCR1A/ CB2/ A2 1 I/O Comparator_B input CB2
Analog input A2 – 12-bit ADC
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: TA1 CCR0 compare output or capture input
P2.1/ PM_TA1CCR0A/ CB1/ A1 2 I/O Comparator_B input CB1
Analog input A1 – 12-bit ADC
General-purpose digital I/O with port interrupt and mappable secondary function
P2.0/ PM_CBOUT1/ PM_TA1CLK/ Default mapping: Comparator_B output; TA1 clock input
3 I/O
CB0/ A0 Comparator_B input CB0
Analog input A0 – 12-bit ADC
P1.7/ PM_UCA0CLK/ General-purpose digital I/O with port interrupt and mappable secondary function
4 I/O
PM_UCB0STE Default mapping: USCI_A0 clock input/output / USCI_B0 SPI slave transmit enable
P1.6/ PM_UCA0TXD/ General-purpose digital I/O with port interrupt and mappable secondary function
5 I/O
PM_UCA0SIMO Default mapping: USCI_A0 UART transmit data; USCI_A0 SPI slave in master out
P1.5/ PM_UCA0RXD/ General-purpose digital I/O with port interrupt and mappable secondary function
6 I/O
PM_UCA0SOMI Default mapping: USCI_A0 UART receive data; USCI_A0 SPI slave out master in
VCORE 7 Regulated core power supply
DVCC 8 Digital power supply
P1.4/ PM_UCB0CLK/ General-purpose digital I/O with port interrupt and mappable secondary function
9 I/O
PM_UCA0STE Default mapping: USCI_B0 clock input/output / USCI_A0 SPI slave transmit enable
P1.3/ PM_UCB0SIMO/ General-purpose digital I/O with port interrupt and mappable secondary function
10 I/O
PM_UCB0SDA Default mapping: USCI_B0 SPI slave in master out/USCI_B0 I2C data
P1.2/ PM_UCB0SOMI/ General-purpose digital I/O with port interrupt and mappable secondary function
11 I/O
PM_UCB0SCL Default mapping: USCI_B0 SPI slave out master in/UCSI_B0 I2C clock
General-purpose digital I/O with port interrupt and mappable secondary function
P1.1/ PM_RFGDO2 12 I/O Default mapping: Radio GDO2 output
General-purpose digital I/O with port interrupt and mappable secondary function
P1.0/ PM_RFGDO0 13 I/O Default mapping: Radio GDO0 output
General-purpose digital I/O with mappable secondary function
P3.7/ PM_SMCLK 14 I/O Default mapping: SMCLK output
General-purpose digital I/O with mappable secondary function
P3.6/ PM_RFGDO1 15 I/O Default mapping: Radio GDO1 output
General-purpose digital I/O with mappable secondary function
P3.5/ PM_TA0CCR4A 16 I/O Default mapping: TA0 CCR4 compare output or capture input
General-purpose digital I/O with mappable secondary function
P3.4/ PM_TA0CCR3A 17 I/O Default mapping: TA0 CCR3 compare output or capture input
General-purpose digital I/O with mappable secondary function
P3.3/ PM_TA0CCR2A 18 I/O Default mapping: TA0 CCR2 compare output or capture input
General-purpose digital I/O with mappable secondary function
P3.2/ PM_TA0CCR1A 19 I/O Default mapping: TA0 CCR1 compare output or capture input
General-purpose digital I/O with mappable secondary function
P3.1/ PM_TA0CCR0A 20 I/O Default mapping: TA0 CCR0 compare output or capture input
General-purpose digital I/O with mappable secondary function
P3.0/ PM_CBOUT0/ PM_TA0CLK 21 I/O Default mapping: Comparator_B output; TA0 clock input
DVCC 22 Digital power supply
P2.7/ PM_ADC12CLK/ General-purpose digital I/O with port interrupt and mappable secondary function
23 I/O
PM_DMAE0 Default mapping: ADC12CLK output; DMA external trigger input
General-purpose digital I/O with port interrupt and mappable secondary function
P2.6/ PM_ACLK 24 I/O Default mapping: ACLK output
RF_XIN 25 I Input terminal for RF crystal oscillator, or external clock input
RF_XOUT 26 O Output terminal for RF crystal oscillator
AVCC_RF 27 Radio analog power supply
(1) I = input, O = output
Copyright © 2009–2013, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: CC430F6137 CC430F6135 CC430F6127 CC430F6126 CC430F6125 CC430F5137
CC430F5135 CC430F5133

ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
CC430F5137, CC430F5135, CC430F5133
SLAS554H –MAY 2009–REVISED SEPTEMBER 2013 www.ti.com
Table 3. CC430F513x Terminal Functions (continued)
TERMINAL I/O(1) DESCRIPTION
NAME NO.
AVCC_RF 28 Radio analog power supply
RF Positive RF input to LNA in receive mode
RF_P 29 I/O Positive RF output from PA in transmit mode
RF Negative RF input to LNA in receive mode
RF_N 30 I/O Negative RF output from PA in transmit mode
AVCC_RF 31 Radio analog power supply
AVCC_RF 32 Radio analog power supply
RBIAS 33 External bias resistor for radio reference current
GUARD 34 Power supply connection for digital noise isolation
General-purpose digital I/O
PJ.0/ TDO 35 I/O Test data output port
General-purpose digital I/O
PJ.1/ TDI/ TCLK 36 I/O Test data input or test clock input
General-purpose digital I/O
PJ.2/ TMS 37 I/O Test mode select
General-purpose digital I/O
PJ.3/ TCK 38 I/O Test clock
Test mode pin – select digital I/O on JTAG pins
TEST/ SBWTCK 39 I Spy-Bi-Wire input clock
Reset input active low
RST/NMI/ SBWTDIO 40 I/O Non-maskable interrupt input
Spy-Bi-Wire data input/output
DVCC 41 Digital power supply
AVSS 42 Analog ground supply for ADC12
General-purpose digital I/O
P5.1/ XOUT 43 I/O Output terminal of crystal oscillator XT1
General-purpose digital I/O
P5.0/ XIN 44 I/O Input terminal for crystal oscillator XT1
AVCC 45 Analog power supply
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: SVM output
P2.5/ PM_SVMOUT/ CB5/ Comparator_B input CB5
46 I/O
A5/ VREF+/ VeREF+ Analog input A5 – 12-bit ADC
Output of reference voltage to the ADC
Input for an external reference voltage to the ADC
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: RTCCLK output
P2.4/ PM_RTCCLK/ CB4/ Comparator_B input CB4
47 I/O
A4/ VREF-/ VeREF- Analog input A4 – 12-bit ADC
Negative terminal for the ADC's reference voltage for both sources, the internal
reference voltage, or an external applied reference voltage
General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: TA1 CCR2 compare output or capture input
P2.3/ PM_TA1CCR2A/ CB3/ A3 48 I/O Comparator_B input CB3
Analog input A3 – 12-bit ADC
Ground supply
VSS - Exposed die attach pad The exposed die attach pad must be connected to a solid ground plane as this is
the ground connection for the chip.
14 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: CC430F6137 CC430F6135 CC430F6127 CC430F6126 CC430F6125 CC430F5137
CC430F5135 CC430F5133

BIAS
PA
RBIAS RF_XIN RF_XOUT
XOSC
LNA
0
90
FREQ
SYNTH
ADC
DEMODULATOR
PACKET HANDLER
RXFIFOTXFIFO
INTERFACE TO MCU
RADIO CONTROL
RF_P
RF_N
RC OSC
ADC
MODULATOR
ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
CC430F5137, CC430F5135, CC430F5133
www.ti.com SLAS554H –MAY 2009–REVISED SEPTEMBER 2013
Short-Form Description
Sub-1-GHz Radio
The implemented sub-1-GHz radio module is based on the industry-leading CC1101, requiring very few external
components. Figure 1 shows a high-level block diagram of the implemented radio.
Figure 1. Sub-1-GHz Radio Block Diagram
The radio features a low-IF receiver. The received RF signal is amplified by a low-noise amplifier (LNA) and
down-converted in quadrature to the intermediate frequency (IF). At IF, the I/Q signals are digitized. Automatic
gain control (AGC), fine channel filtering, demodulation bit and packet synchronization are performed digitally.
The transmitter part is based on direct synthesis of the RF frequency. The frequency synthesizer includes a
completely on-chip LC VCO and a 90° phase shifter for generating the I and Q LO signals to the down-
conversion mixers in receive mode.
The 26-MHz crystal oscillator generates the reference frequency for the synthesizer, as well as clocks for the
ADC and the digital part.
A memory mapped register interface is used for data access, configuration, and status request by the CPU.
The digital baseband includes support for channel configuration, packet handling, and data buffering.
For complete module descriptions, see the CC430 Family User's Guide (SLAU259).
Copyright © 2009–2013, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: CC430F6137 CC430F6135 CC430F6127 CC430F6126 CC430F6125 CC430F5137
CC430F5135 CC430F5133

ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
CC430F5137, CC430F5135, CC430F5133
SLAS554H –MAY 2009–REVISED SEPTEMBER 2013 www.ti.com
CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations,
other than program-flow instructions, are performed as register operations in conjunction with seven addressing
modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register
operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant
generator, respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data, address, and control buses and can be handled with all
instructions.
The instruction set consists of the original 51 instructions with three formats and seven address modes and
additional instructions for the expanded address range. Each instruction can operate on word and byte data.
Operating Modes
The CC430 has one active mode and five software-selectable low-power modes of operation. An interrupt event
can wake up the device from any of the low-power modes, service the request, and restore back to the low-
power mode on return from the interrupt program.
The following six operating modes can be configured by software:
• Active mode (AM)
– All clocks are active
• Low-power mode 0 (LPM0)
– CPU is disabled
– ACLK and SMCLK remain active, MCLK is disabled
– FLL loop control remains active
• Low-power mode 1 (LPM1)
– CPU is disabled
– FLL loop control is disabled
– ACLK and SMCLK remain active, MCLK is disabled
• Low-power mode 2 (LPM2)
– CPU is disabled
– MCLK and FLL loop control and DCOCLK are disabled
– DCO's dc-generator remains enabled
– ACLK remains active
• Low-power mode 3 (LPM3)
– CPU is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DCO's dc-generator is disabled
– ACLK remains active
• Low-power mode 4 (LPM4)
– CPU is disabled
– ACLK is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DCO's dc-generator is disabled
– Crystal oscillator is stopped
– Complete data retention
16 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: CC430F6137 CC430F6135 CC430F6127 CC430F6126 CC430F6125 CC430F5137
CC430F5135 CC430F5133

ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
CC430F5137, CC430F5135, CC430F5133
www.ti.com SLAS554H –MAY 2009–REVISED SEPTEMBER 2013
Interrupt Vector Addresses
The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The
vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 4. Interrupt Sources, Flags, and Vectors
SYSTEM WORD
INTERRUPT SOURCE INTERRUPT FLAG PRIORITY
INTERRUPT ADDRESS
System Reset
Power-Up
External Reset WDTIFG, KEYV (SYSRSTIV)(1)(2) Reset 0FFFEh 63, highest
Watchdog Timeout, Password
Violation
Flash Memory Password Violation
System NMI SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,
PMM VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG, (Non)maskable 0FFFCh 62
Vacant Memory Access JMBOUTIFG (SYSSNIV)(1)(3)
JTAG Mailbox
User NMI
NMI NMIIFG, OFIFG, ACCVIFG (SYSUNIV)(1)(3) (Non)maskable 0FFFAh 61
Oscillator Fault
Flash Memory Access Violation
Comparator_B Comparator_B Interrupt Flags (CBIV)(1) Maskable 0FFF8h 60
Watchdog Interval Timer Mode WDTIFG Maskable 0FFF6h 59
USCI_A0 Receive or Transmit UCA0RXIFG, UCA0TXIFG (UCA0IV)(1) Maskable 0FFF4h 58
UCB0RXIFG, UCB0TXIFG, I2C Status Interrupt
USCI_B0 Receive or Transmit Maskable 0FFF2h 57
Flags (UCB0IV)(1)
ADC12_A ADC12IFG0 ... ADC12IFG15 (ADC12IV)(1) Maskable 0FFF0h 56
(Reserved on CC430F612x)
TA0 TA0CCR0 CCIFG0 Maskable 0FFEEh 55
TA0CCR1 CCIFG1 ... TA0CCR4 CCIFG4,
TA0 Maskable 0FFECh 54
TA0IFG (TA0IV)(1)
Radio Interface Interrupt Flags (RF1AIFIV)
RF1A CC1101-based Radio Maskable 0FFEAh 53
Radio Core Interrupt Flags (RF1AIV)
DMA DMA0IFG, DMA1IFG, DMA2IFG (DMAIV)(1) Maskable 0FFE8h 52
TA1 TA1CCR0 CCIFG0 Maskable 0FFE6h 51
TA1CCR1 CCIFG1 ... TA1CCR2 CCIFG2,
TA1 Maskable 0FFE4h 50
TA1IFG (TA1IV)(1)
I/O Port P1 P1IFG.0 to P1IFG.7 (P1IV)(1) Maskable 0FFE2h 49
I/O Port P2 P2IFG.0 to P2IFG.7 (P2IV)(1) Maskable 0FFE0h 48
LCD_B LCD_B Interrupt Flags (LCDBIV)(1) Maskable 0FFDEh 47
(Reserved on CC430F513x) RTCRDYIFG, RTCTEVIFG, RTCAIFG,
RTC_A Maskable 0FFDCh 46
RT0PSIFG, RT1PSIFG (RTCIV)(1)
AES AESRDYIFG Maskable 0FFDAh 45
0FFD8h 44
Reserved Reserved(4) ⋮ ⋮
0FF80h 0, lowest
(1) Multiple source flags
(2) A reset is generated if the CPU tries to fetch instructions from within peripheral space.
(3) (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
(4) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain
compatibility with other devices, it is recommended to reserve these locations.
Copyright © 2009–2013, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: CC430F6137 CC430F6135 CC430F6127 CC430F6126 CC430F6125 CC430F5137
CC430F5135 CC430F5133

ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
CC430F5137, CC430F5135, CC430F5133
SLAS554H –MAY 2009–REVISED SEPTEMBER 2013 www.ti.com
Memory Organization
Table 5. Memory Organization
CC430F6137 CC430F6135
CC430F6127 CC430F6126(1) CC430F6125 CC430F5133(1)
CC430F5137(1) CC430F5135(1)
Main Memory Total 32kB 32kB 16kB 8kB
(flash) Size
Main: Interrupt 00FFFFh to 00FF80h 00FFFFh to 00FF80h 00FFFFh to 00FF80h 00FFFFh to 00FF80h
vector
Main: code Bank 0 32kB 32kB 16kB 8kB
memory 00FFFFh to 008000h 00FFFFh to 008000h 00FFFFh to 00C000h 00FFFFh to 00E000h
Total 4kB 2kB 2kB 2kB
RAM Size
Sect 1 2kB not available not available not available
002BFFh to 002400h
Sect 0 2kB 2kB 2kB 2kB
0023FFh to 001C00h 0023FFh to 001C00h 0023FFh to 001C00h 0023FFh to 001C00h
128 B 128 B 128 B 128 B
001AFFh to 001A80h 001AFFh to 001A80h 001AFFh to 001A80h 001AFFh to 001A80h
Device
Descriptor 128 B 128 B 128 B 128 B
001A7Fh to 001A00h 001A7Fh to 001A00h 001A7Fh to 001A00h 001A7Fh to 001A00h
Info A 128 B 128 B 128 B 128 B
0019FFh to 001980h 0019FFh to 001980h 0019FFh to 001980h 0019FFh to 001980h
Info B 128 B 128 B 128 B 128 B
00197Fh to 001900h 00197Fh to 001900h 00197Fh to 001900h 00197Fh to 001900h
Information
memory (flash) Info C 128 B 128 B 128 B 128 B
0018FFh to 001880h 0018FFh to 001880h 0018FFh to 001880h 0018FFh to 001880h
Info D 128 B 128 B 128 B 128 B
00187Fh to 001800h 00187Fh to 001800h 00187Fh to 001800h 00187Fh to 001800h
BSL 3 512 B 512 B 512 B 512 B
0017FFh to 001600h 0017FFh to 001600h 0017FFh to 001600h 0017FFh to 001600h
BSL 2 512 B 512 B 512 B 512 B
Bootstrap loader 0015FFh to 001400h 0015FFh to 001400h 0015FFh to 001400h 0015FFh to 001400h
(BSL) memory BSL 1 512 B 512 B 512 B 512 B
(flash) 0013FFh to 001200h 0013FFh to 001200h 0013FFh to 001200h 0013FFh to 001200h
BSL 0 512 B 512 B 512 B 512 B
0011FFh to 001000h 0011FFh to 001000h 0011FFh to 001000h 0011FFh to 001000h
4 KB 4 KB 4 KB 4 KB
Peripherals 000FFFh to 0h 000FFFh to 0h 000FFFh to 0h 000FFFh to 0h
(1) All memory regions not specified here are vacant memory, and any access to them causes a Vacant Memory Interrupt.
Bootstrap Loader (BSL)
The BSL enables users to program the flash memory or RAM using various serial interfaces. Access to the
device memory via the BSL is protected by an user-defined password. BSL entry requires a specific entry
sequence on the RST/NMI/SBWTDIO and TEST/SBWTCK pins. For a complete description of the features of the
BSL and its implementation, see the MSP430 Programming Via the Bootstrap Loader User's Guide (SLAU319).
Table 6. UART BSL Pin Requirements and Functions
DEVICE SIGNAL BSL FUNCTION
RST/NMI/SBWTDIO Entry sequence signal
TEST/SBWTCK Entry sequence signal
P1.6 Data transmit
P1.5 Data receive
VCC Power supply
VSS Ground supply
18 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: CC430F6137 CC430F6135 CC430F6127 CC430F6126 CC430F6125 CC430F5137
CC430F5135 CC430F5133

ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
CC430F5137, CC430F5135, CC430F5133
www.ti.com SLAS554H –MAY 2009–REVISED SEPTEMBER 2013
JTAG Operation
JTAG Standard Interface
The CC430 family supports the standard JTAG interface which requires four signals for sending and receiving
data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to enable the
JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with MSP430
development tools and device programmers. The JTAG pin requirements are shown in Table 7. For further
details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's
Guide (SLAU278). For a complete description of the features of the JTAG interface and its implementation, see
MSP430 Programming Via the JTAG Interface (SLAU320).
Table 7. JTAG Pin Requirements and Functions
DEVICE SIGNAL DIRECTION FUNCTION
PJ.3/TCK IN JTAG clock input
PJ.2/TMS IN JTAG state control
PJ.1/TDI/TCLK IN JTAG data input, TCLK input
PJ.0/TDO OUT JTAG data output
TEST/SBWTCK IN Enable JTAG pins
RST/NMI/SBWTDIO IN External reset
VCC Power supply
VSS Ground supply
Spy-Bi-Wire Interface
In addition to the standard JTAG interface, the CC430 family supports the two wire Spy-Bi-Wire interface. Spy-Bi-
Wire can be used to interface with MSP430 development tools and device programmers. The Spy-Bi-Wire
interface pin requirements are shown in Table 8. For further details on interfacing to development tools and
device programmers, see the MSP430 Hardware Tools User's Guide (SLAU278). For a complete description of
the features of the JTAG interface and its implementation, see MSP430 Programming Via the JTAG Interface
(SLAU320).
Table 8. Spy-Bi-Wire Pin Requirements and Functions
DEVICE SIGNAL DIRECTION FUNCTION
TEST/SBWTCK IN Spy-Bi-Wire clock input
RST/NMI/SBWTDIO IN, OUT Spy-Bi-Wire data input/output
VCC Power supply
VSS Ground supply
Flash Memory
The flash memory can be programmed via the JTAG port, Spy-Bi-Wire (SBW), or in-system by the CPU. The
CPU can perform single-byte, single-word, and long-word writes to the flash memory. Features of the flash
memory include:
• Flash memory has n segments of main memory and four segments of information memory (Info A to Info D)
of 128 bytes each. Each segment in main memory is 512 bytes in size.
• Segments 0 to n may be erased in one step, or each segment may be individually erased.
• Segments Info A to Info D can be erased individually, or as a group with the main memory segments.
Segments Info A to Info D are also called information memory.
• Segment A can be locked separately.
Copyright © 2009–2013, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: CC430F6137 CC430F6135 CC430F6127 CC430F6126 CC430F6125 CC430F5137
CC430F5135 CC430F5133

ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
CC430F5137, CC430F5135, CC430F5133
SLAS554H –MAY 2009–REVISED SEPTEMBER 2013 www.ti.com
RAM Memory
The RAM memory is made up of n sectors. Each sector can be completely powered down to save leakage,
however, all data is lost. Features of the RAM memory include:
• RAM memory has n sectors of 2k bytes each.
• Each sector 0 to n can be complete disabled, however data retention is lost.
• Each sector 0 to n automatically enters low power retention mode when possible.
Peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using all
instructions. For complete module descriptions, see the CC430 Family User's Guide (SLAU259).
Oscillator and System Clock
The Unified Clock System (UCS) module includes support for a 32768-Hz watch crystal oscillator, an internal
very-low-power low-frequency oscillator (VLO), an internal trimmed low-frequency oscillator (REFO), an
integrated internal digitally-controlled oscillator (DCO), and a high-frequency crystal oscillator. The UCS module
is designed to meet the requirements of both low system cost and low-power consumption. The UCS module
features digital frequency locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the
DCO frequency to a programmable multiple of the watch crystal frequency. The internal DCO provides a fast
turn-on clock source and stabilizes in less than 5 µs. The UCS module provides the following clock signals:
• Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal, a high-frequency crystal, the internal low-
frequency oscillator (VLO), or the trimmed low-frequency oscillator (REFO).
• Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources made
available to ACLK.
• Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourced by
same sources made available to ACLK.
• ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32.
Power Management Module (PMM)
The PMM includes an integrated voltage regulator that supplies the core voltage to the device and contains
programmable output levels to provide for power optimization. The PMM also includes supply voltage supervisor
(SVS) and supply voltage monitoring (SVM) circuitry, as well as brownout protection. The brownout circuit is
implemented to provide the proper internal reset signal to the device during power-on and power-off. The
SVS/SVM circuitry detects if the supply voltage drops below a user-selectable level and supports both supply
voltage supervision (the device is automatically reset) and supply voltage monitoring (SVM, the device is not
automatically reset). SVS and SVM circuitry is available on the primary supply and core supply.
Digital I/O
There are up to five 8-bit I/O ports implemented: ports P1 through P5.
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt conditions is possible.
• Programmable pullup or pulldown on all ports.
• Programmable drive strength on all ports.
• Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.
• Read/write access to port-control registers is supported by all instructions.
• Ports can be accessed byte-wise (P1 through P5) or word-wise in pairs (PA and PB).
20 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: CC430F6137 CC430F6135 CC430F6127 CC430F6126 CC430F6125 CC430F5137
CC430F5135 CC430F5133