Texas Instruments OMAP5910 Product manual

OMAP5910
Dual-Core Processor
Technical Reference Manual
Literature Number: SPRU602B
January 2003

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Copyright 2003, Texas Instruments Incorporated

iiiContents
Preface
Read This First
About This Manual
ThismanualdescribestheTexasInstrumentsOMAP5910multimediaproces-
sor, hereafter called the OMAP5910 device. The OMAP5910 device supports
the development and testing of wireless device applications that use the
MicrosoftWindowsCEortheSymbianEPOCoperatingsystem.Thismanual
is intended for developers who have knowledge of the Windows CE or the
Symbian EPOC operating system and of the wireless application environ-
ment.
Notational Conventions
This document uses the following conventions.
-Program listings, program examples, and interactive displays are shown
in a special typeface similar to a typewriter’s. Examples use a bold
version of the special typeface for emphasis; interactive displays use a
bold version ofthe special typefacetodistinguish commands thatyou
enter from items that the system displays (such as prompts, command
output, error messages, etc.).
Here is a sample program listing:
0011 0005 0001 .field 1, 2
0012 0005 0003 .field 3, 4
0013 0005 0006 .field 6, 3
0014 0006 .even
Here is an example of a system prompt and a command that you might
enter:
C: csr –a /user/ti/simuboard/utilities

Notational Conventions
iv
-In syntax descriptions, the instruction, command, or directive is in a bold
typefacefontandparametersareinanitalictypeface.Portionsofasyntax
that are in bold should be entered as shown; portions of a syntax that are
in italics describe the type of information that should be entered. Here is
an example of a directive syntax:
.asect ”section name”, address
.asectisthedirective.Thisdirectivehastwoparameters,indicatedbysec-
tionnameandaddress.Whenyou use .asect, the first parametermustbe
anactualsectionname,enclosedindoublequotes;thesecondparameter
must be an address.
-Square brackets ( [and ]) identify an optional parameter. If you use an
optional parameter, you specify the information within the brackets; you
don’t enter the brackets themselves. Here’s an example of an instruction
that has an optional parameter:
LALK 16–bit constant [, shift]
TheLALKinstruction hastwoparameters.Thefirstparameter, 16-bitcon-
stant, is required. The second parameter, shift, is optional. As this syntax
shows,ifyou usetheoptionalsecondparameter,youmustprecede itwith
a comma.
Square brackets are also used as part of the pathname specification for
VMS pathnames; in this case, the brackets are actually part of the path-
name (they are not optional).
-Braces( {and} )indicatealist.Thesymbol|(readasor)separatesitems
within the list. Here’s an example of a list:
{ * | *+ | *– }
This provides three choices: *, *+, or *–.
Unless the list is enclosed in square brackets, you must choose one item
from the list.
-Some directives can have a varying number of parameters. For example,
the .byte directive can have up to 100 parameters. The syntax for this di-
rective is:
.byte value1[, ... , valuen]
This syntax shows that .byte must have at least one value parameter, but
you have the option of supplying additional value parameters, separated
by commas.

Notational Conventions
vRead This First
Information About Cautions and Warnings
This book may contain cautions and warnings.
This is an example of a caution statement.
A caution statement describes a situation that could potentially
damage your software or equipment.
This is an example of a warning statement.
A warning statement describes a situation that could potentially
cause harm to you.
The information in a caution or a warning is provided for your protection.
Please read each caution and warning carefully.
Related Documentation From Texas Instruments
TMS320C55x DSP CPU Reference Guide (SPRU371D)
TMS320C55x DSP Functional Overview (SPRU312)
TMS320C55x DSP Function Library (DSPLIB) Programmer’s Reference
(SPRU422D)
TMS320C55x Technical Overview (SPRU393)
TMS320C55x DSP Programmer’s Guide (SPRU376A)
TMS320C55x DSP Mnemonic Instruction Set Ref Guide (SPRU374F)
TMS320C55x Assembly Language Tools User’s Guide (SPRU280D)
TMS320C55x Optimizing C Compiler User’s Guide (SPRU281C)
The MultiMediaCard System Specification Version 3.1 –June 2001. MMCA
Technical Committee
SD Memory Card Specifications: Part 1 Physical Layer Specification, Version
1.0 –March 2000 + Supplementary Notes Part 1 June 2000. SD Group
Information About Cautions and Warnings / Related Documentation From Texas Instruments

Trademarks
vi
Trademarks
Bluetooth is a trademark owned by the Bluetooth SIG, Inc. and licensed to
Texas Instruments.
TMS320C5510, TMS320C55x, C55x, and Code Composer Studio are
trademarks of Texas Instruments.
Microsoft, Windows, Windows CE, Windows CE Platform Builder, and
Windows NT are trademarks of Microsoft Corporation.
Other trademarks are the property of their respective owners.

Contents
vii
Contents
1 Introduction 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduces the setup, components, and features of the OMAP5910 processor and provides a
high-level view of the device architecture.
1.1 Overview 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Description 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Features 1-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Architecture 1-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 Memory Maps 1-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6 Software Compatibility 1-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6.1 OMAP Driver Compatibility Conventions 1-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 MPU Subsystem 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Describes the core, caches, memory management units (MMUs), interface, and bridges of the
OMAP5910 multimedia processor microprocessor unit (MPU) subsystem.
2.1 Introduction 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 MPU Core 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Instruction Cache 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.1 Operation 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.2 Validity 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Data Cache 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.1 D-Cache Operation 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.2 Validity 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.3 Double-Mapped Space 2-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 Write Buffer 2-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.1 Operation 2-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.2 SWAP Instruction 2-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6 Coprocessor 15 2-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.1 CP15 Access 2-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.2 Register Descriptions 2-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7 MPU Memory Management Unit 2-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7.1 Translation Look-Aside Buffer 2-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7.2 Translation Table 2-27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7.3 Domains and Access Permissions 2-27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7.4 MMU Program-Accessible Registers 2-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7.5 Address Translation 2-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7.6 Translation Process 2-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7.7 MMU Faults and MPU Aborts 2-39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7.8 Fault Address and Fault Status Registers (FAR and FSR) 2-41. . . . . . . . . . . . . . .
2.7.9 Domain Access Control 2-42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7.10 Permission Access 2-43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents
viii
2.7.11 Fault Checking Sequence 2-43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7.12 External Aborts 2-46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7.13 Buffered Writes 2-46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8 DSP Memory Management Unit 2-47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.9 MPU Interface 2-55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.9.1 Functional Features 2-56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.9.2 MPUI Registers 2-57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.10 MPU TI Peripheral Bus Bridges 2-65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.10.1 8-Bit, 16-Bit, and 32-Bit Word Access 2-65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.10.2 TIPB Allocation 2-66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.10.3 Access Factor and Time-Out 2-66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.10.4 MPU Posted Write 2-67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.10.5 Pipeline Mode 2-67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.10.6 Abort 2-67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.10.7 TIPB Bridge Registers 2-67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.11 Endianism Conversion 2-71. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.11.1 Conversion Through the DSP MMU 2-72. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.11.2 Conversion Through the MPUI 2-74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.12 ETM Environment 2-75. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.12.1 ETM Features 2-75. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.12.2 ETM Interface 2-75. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.12.3 Operation 2-77. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.12.4 Additional Reference Materials 2-78. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 DSP Subsystem 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Describes the OMAP5910 multimedia processor DSP subsystem.
3.1 Architecture Overview 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.1 DSP Core 3-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 TMS320C55x DSP CPU Overview 3-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.1 On-Chip Memory 3-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.2 Hardware Acceleration Modules 3-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.3 CPU Overview 3-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 DSP Memory 3-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.1 Internal Memory 3-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.2 Instruction Cache 3-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.3 System Memory 3-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.4 Memory Map 3-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.5 Peripheral Register Addresses 3-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 DMA Controller 3-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.1 Key Features of the DMA Controller 3-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.2 DMA Controller Configuration Registers 3-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.3 DSP DMA Event Mapping 3-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5 TIPB Bridge 3-27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.1 Control Mode Register (CMR) 3-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.2 Idle Control and Idle Status Registers (ICR and ISTR) 3-31. . . . . . . . . . . . . . . . . . .

Contents
ixContents
3.6 MPU Interface 3-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.1 HOM/SAM Change Outside of Reset 3-34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.2 ST3—HOM_P Bit (Bit 8) 3-34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.3 ST3—HOM_R Bit (Bit 9) 3-35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7 EMIF 3-36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.1 EMIF Global Control Register (EMIF_GCR) 3-36. . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.2 EMIF Global Reset Register (EMIF GRR) 3-37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8 DSP Memory Management Unit 3-37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9 DSP Subsystem Clocking and Reset Control 3-38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.10 System Operating Details 3-39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.10.1 DSP Private Peripherals 3-39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.10.2 DSP Public Peripherals 3-39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.10.3 DSP/MPU Shared Peripherals 3-40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.10.4 Boot Mode for DSP Subsystem 3-40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Memory Interface Traffic Controller 4-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Describes the OMAP5910 multimedia processor memory interface traffic controller (TC).
4.1 Introduction 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 Memory Map 4-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 Memory Interfaces 4-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.1 Internal Memory Interface 4-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.2 External Memory Interface Slow 4-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.3 External Memory Interface Fast 4-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4 Traffic Controller Memory Interface Registers 4-42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5 Interfacing Memories With the OMAP5910 Device 4-57. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 System DMA Controller 5-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Describes the system DMA controller for the OMAP5910 multimedia processor.
5.1 Introduction 5-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2 External Connections 5-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3 Generic Channels 5-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.1 Transfers 5-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.2 Addressing Modes 5-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.3 Data Packing and Bursting 5-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.4 Data/Address Alignment 5-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.5 Constraint on Channel Configuration Parameters 5-21. . . . . . . . . . . . . . . . . . . . . . .
5.3.6 Endianism 5-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.7 Interrupt Generation 5-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.8 Memory Space Protection 5-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4 LCD Dedicated Channel 5-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.1 Functional Description 5-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.2 Addressing Units 5-27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.3 LCD Channel Usage Restrictions 5-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.4 LCD Transfer Examples 5-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5 DMA Request Mapping 5-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6 Registers 5-34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6.1 Generic Channel Registers 5-41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents
x
6 MPU Private Peripherals 6-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Describes the OMAP5910 multimedia processor MPU private peripherals.
6.1 Overview 6-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2 Timer Description 6-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.1 Programming the Timer 6-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.2 Timer Registers 6-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3 Watchdog Timer 6-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.1 Introduction 6-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.2 Programming the Watchdog Timer in Watchdog Mode 6-10. . . . . . . . . . . . . . . . . . .
6.3.3 Programming the Watchdog Timer in Timer Mode 6-11. . . . . . . . . . . . . . . . . . . . . .
6.3.4 Watchdog Timer Registers 6-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4 MPU Interrupt Handlers 6-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.1 MPU Level 1 Interrupt Handler 6-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.2 MPU Level 2 Interrupt Handler 6-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5 Level 1 and Level 2 Interrupt Mapping 6-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6 Interrupt Handler Level 1 and Level 2 Registers 6-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.7 Configuration Module 6-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.7.1 Configuration Register Capabilities 6-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.7.2 OMAP5910 Native and Compatibility Modes 6-24. . . . . . . . . . . . . . . . . . . . . . . . . . .
6.7.3 OMAP5910 Generic Pin Multiplexing and Pullup/Pulldown Control 6-25. . . . . . . .
6.7.4 OMAP5910 MMC/SD Pin Multiplexing 6-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.7.5 OMAP5910 Pullups and Pulldowns 6-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.8 OMAP5910 Configuration Registers 6-27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.9 Device Identification 6-70. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.9.1 Identification Code Register 6-70. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.9.2 Die Identification (ID) 6-71. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7 MPU Public Peripherals 7-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Describes the OMAP5910 multimedia processor MPU public peripherals.
7.1 MPU Public Peripherals 7-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2 Camera Interface 7-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2.1 Functional Architecture 7-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2.2 Clock Switching Procedures 7-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3 MPU I/O 7-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.1 MPU I/O Interrupts 7-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.2 MPU I/O Clocks and Reset 7-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.3 MPUIO Keyboard Interface 7-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.4 MPUIO General-Purpose I/O Interface 7-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.5 GPIO Interrupt Reset 7-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.6 GPIO Interrupt Masking 7-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.7 Event Capture Module 7-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.8 MPU I/O Registers 7-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .