Texas Instruments TMS320DM643x User manual

TMS320DM643x DMPDSP Subsystem
Reference Guide
Literature Number: SPRU978E
March 2008

2 SPRU978E – March 2008Submit Documentation Feedback

Contents
Preface ............................................................................................................................... 9
1 Introduction ............................................................................................................. 111.1 Introduction ......................................................................................................... 121.2 Block Diagram ..................................................................................................... 121.3 DSP Subsystem in TMS320DM643x DMP .................................................................... 131.3.1 Components of the DSP Subsystem .................................................................. 13
2 TMS320C64x+ Megamodule ....................................................................................... 152.1 Introduction ......................................................................................................... 162.2 TMS320C64x+ CPU .............................................................................................. 162.3 Memory Controllers ............................................................................................... 182.3.1 L1P Controller ............................................................................................ 182.3.2 L1D Controller ............................................................................................ 202.3.3 L2 Controller .............................................................................................. 202.3.4 External Memory Controller (EMC) .................................................................... 212.3.5 Internal DMA (IDMA) ..................................................................................... 212.4 Internal Peripherals ............................................................................................... 222.4.1 Interrupt Controller (INTC) .............................................................................. 222.4.2 Power-Down Controller (PDC) .......................................................................... 222.4.3 Bandwidth Manager ...................................................................................... 23
3 System Memory ....................................................................................................... 253.1 Memory Map ....................................................................................................... 263.1.1 DSP Internal Memory (L1P, L1D, L2) ................................................................. 263.1.2 External Memory ......................................................................................... 263.1.3 Internal Peripherals ...................................................................................... 263.1.4 Device Peripherals ....................................................................................... 263.2 Memory Interfaces Overview .................................................................................... 273.2.1 DDR2 External Memory Interface ...................................................................... 273.2.2 External Memory Interface .............................................................................. 27
4 Device Clocking ....................................................................................................... 294.1 Overview ............................................................................................................ 304.2 Clock Domains ..................................................................................................... 304.2.1 Core Domains ............................................................................................ 304.2.2 Core Frequency Flexibility .............................................................................. 324.2.3 DDR2/EMIF Clock ........................................................................................ 334.2.4 I/O Domains ............................................................................................... 344.2.5 Video Processing Back End ............................................................................ 35
5 PLL Controller .......................................................................................................... 375.1 PLL Module ........................................................................................................ 385.2 PLL1 Control ....................................................................................................... 385.2.1 Device Clock Generation ................................................................................ 395.2.2 Steps for Changing PLL1/Core Domain Frequency ................................................. 395.3 PLL2 Control ....................................................................................................... 435.3.1 Device Clock Generation ................................................................................ 43
SPRU978E – March 2008 Contents 3Submit Documentation Feedback

5.3.2 Steps for Changing PLL2 Frequency .................................................................. 445.4 PLL Controller Registers ......................................................................................... 485.4.1 Peripheral ID Register (PID) ............................................................................ 495.4.2 Reset Type Status Register (RSTYPE) ............................................................... 495.4.3 PLL Control Register (PLLCTL) ........................................................................ 505.4.4 PLL Multiplier Control Register (PLLM) ............................................................... 515.4.5 PLL Controller Divider 1 Register (PLLDIV1) ......................................................... 515.4.6 PLL Controller Divider 2 Register (PLLDIV2) ......................................................... 525.4.7 PLL Controller Divider 3 Register (PLLDIV3) ......................................................... 525.4.8 Oscillator Divider 1 Register (OSCDIV1) .............................................................. 535.4.9 Bypass Divider Register (BPDIV) ...................................................................... 545.4.10 PLL Controller Command Register (PLLCMD) ...................................................... 555.4.11 PLL Controller Status Register (PLLSTAT) .......................................................... 555.4.12 PLL Controller Clock Align Control Register (ALNCTL) ............................................ 565.4.13 PLLDIV Ratio Change Status Register (DCHANGE) ............................................... 575.4.14 Clock Enable Control Register (CKEN) .............................................................. 585.4.15 Clock Status Register (CKSTAT) ..................................................................... 595.4.16 SYSCLK Status Register (SYSTAT) .................................................................. 60
6 Power and Sleep Controller ....................................................................................... 616.1 Introduction ......................................................................................................... 626.2 Power Domain and Module Topology .......................................................................... 636.3 Power Domain and Module States .............................................................................. 646.3.1 Power Domain States .................................................................................... 646.3.2 Module States ............................................................................................ 646.3.3 Local Reset ............................................................................................... 656.4 Executing State Transitions ...................................................................................... 656.4.1 Power Domain State Transitions ....................................................................... 656.4.2 Module State Transitions ................................................................................ 656.5 IcePick Emulation Support in the PSC ......................................................................... 666.6 PSC Interrupts ..................................................................................................... 666.6.1 Interrupt Events ........................................................................................... 666.6.2 Interrupt Registers ........................................................................................ 676.6.3 Interrupt Handling ........................................................................................ 686.7 PSC Registers ..................................................................................................... 686.7.1 Peripheral Revision and Class Information Register (PID) ......................................... 696.7.2 Interrupt Evaluation Register (INTEVAL) .............................................................. 696.7.3 Module Error Pending Register 1 (MERRPR1) ...................................................... 706.7.4 Module Error Clear Register 1 (MERRCR1) .......................................................... 706.7.5 Power Domain Transition Command Register (PTCMD) ........................................... 716.7.6 Power Domain Transition Status Register (PTSTAT) ............................................... 716.7.7 Power Domain Status 0 Register (PDSTAT0) ........................................................ 726.7.8 Power Domain Control 0 Register (PDCTL0) ........................................................ 736.7.9 Module Status n Register (MDSTATn) ................................................................ 746.7.10 Module Control n Register (MDCTLn) ................................................................ 75
7 Power Management .................................................................................................. 777.1 Overview ............................................................................................................ 787.2 PSC and PLLC Overview ........................................................................................ 787.3 Clock Management ............................................................................................... 79
4Contents SPRU978E – March 2008Submit Documentation Feedback

7.3.1 Module Clock ON/OFF .................................................................................. 797.3.2 Module Clock Frequency Scaling ...................................................................... 797.3.3 PLL Bypass and Power Down .......................................................................... 797.4 DSP Sleep Mode Management ................................................................................. 807.4.1 DSP Sleep Modes ........................................................................................ 807.4.2 DSP Module Clock ON/OFF ............................................................................ 807.5 3.3 V I/O Power Down ............................................................................................ 817.6 Video DAC Power Down ......................................................................................... 81
8 Interrupt Controller ................................................................................................... 83
9 System Module ........................................................................................................ 859.1 Overview ............................................................................................................ 869.2 Device Identification ............................................................................................... 869.3 Device Configuration .............................................................................................. 869.3.1 Pin Multiplexing Control ................................................................................. 869.3.2 Device Boot Configuration Status ...................................................................... 869.4 3.3 V I/O Power-Down Control .................................................................................. 879.5 Peripheral Status and Control ................................................................................... 879.5.1 Timer Control ............................................................................................. 879.5.2 VPSS Clock and DAC Control .......................................................................... 879.5.3 DDR2 VTP Control ....................................................................................... 879.5.4 HPI Control ................................................................................................ 879.6 Bandwidth Management .......................................................................................... 889.6.1 Bus Master DMA Priority Control ....................................................................... 889.6.2 EDMA Transfer Controller Configuration .............................................................. 899.7 Boot Control ........................................................................................................ 89
10 Reset ...................................................................................................................... 9110.1 Overview ............................................................................................................ 9210.2 Reset Pins .......................................................................................................... 9210.3 Device Configurations at Reset ................................................................................. 9210.4 DSP Reset ......................................................................................................... 9310.4.1 DSP Local Reset ........................................................................................ 9310.4.2 DSP Module Reset ...................................................................................... 93
11 Boot Modes ............................................................................................................. 95
A Revision History ....................................................................................................... 97
SPRU978E – March 2008 Contents 5Submit Documentation Feedback

List of Figures
1-1 TMS320DM643x DMP Block Diagram .................................................................................. 122-1 TMS320C64x+ Megamodule Block Diagram ........................................................................... 172-2 C64x+ Cache Memory Architecture ...................................................................................... 194-1 Overall Clocking Diagram ................................................................................................. 314-2 VPBE/DAC Clocking ....................................................................................................... 355-1 PLL1 Structure in the TMS320DM643x DMP .......................................................................... 395-2 PLL2 Structure in the TMS320DM643x DMP .......................................................................... 435-3 Peripheral ID Register (PID) .............................................................................................. 495-4 Reset Type Status Register (RSTYPE) ................................................................................. 495-5 PLL Control Register (PLLCTL) .......................................................................................... 505-6 PLL Multiplier Control Register (PLLM) ................................................................................. 515-7 PLL Controller Divider 1 Register (PLLDIV1) ........................................................................... 515-8 PLL Controller Divider 2 Register (PLLDIV2) .......................................................................... 525-9 PLL Controller Divider 3 Register (PLLDIV3) .......................................................................... 525-10 Oscillator Divider 1 Register (OSCDIV1) ................................................................................ 535-11 Bypass Divider Register (BPDIV) ........................................................................................ 545-12 PLL Controller Command Register (PLLCMD) ......................................................................... 555-13 PLL Controller Status Register (PLLSTAT) ............................................................................. 555-14 PLL Controller Clock Align Control Register (ALNCTL) ............................................................... 565-15 PLLDIV Ratio Change Status Register (DCHANGE) .................................................................. 575-16 Clock Enable Control Register (CKEN) ................................................................................. 585-17 Clock Status Register (CKSTAT) ........................................................................................ 595-18 SYSCLK Status Register (SYSTAT) ..................................................................................... 606-1 Power and Sleep Controller (PSC) Integration ......................................................................... 626-2 Peripheral Revision and Class Information Register (PID) ........................................................... 696-3 Interrupt Evaluation Register (INTEVAL) ................................................................................ 696-4 Module Error Pending Register 1 (MERRPR1) ........................................................................ 706-5 Module Error Clear Register 1 (MERRCR1) ............................................................................ 706-6 Power Domain Transition Command Register (PTCMD) ............................................................. 716-7 Power Domain Transition Status Register (PTSTAT) ................................................................. 716-8 Power Domain Status 0 Register (PDSTAT0) .......................................................................... 726-9 Power Domain Control 0 Register (PDCTL0) .......................................................................... 736-10 Module Status nRegister (MDSTAT n).................................................................................. 746-11 Module Control nRegister (MDCTL n)................................................................................... 75
6List of Figures SPRU978E – March 2008Submit Documentation Feedback

List of Tables
4-1 System Clock Modes and Fixed Ratios for Core Clock Domains.................................................... 304-2 Example PLL1 Frequencies and Dividers (27 MHZ Clock Input) .................................................... 324-3 Example PLL2 Frequencies (Core Voltage = 1.2V) ................................................................... 334-4 Example PLL2 Frequencies (Core Voltage = 1.05V) .................................................................. 334-5 Peripheral I/O Domain Clock ............................................................................................. 344-6 Possible Clocking Modes.................................................................................................. 365-1 System PLLC1 Output Clocks ............................................................................................ 395-2 DDR PLLC2 Output Clocks ............................................................................................... 435-3 PLL and Reset Controller List ............................................................................................ 485-4 PLL and Reset Controller Registers ..................................................................................... 485-5 Peripheral ID Register (PID) Field Descriptions ........................................................................ 495-6 Reset Type Status Register (RSTYPE) Field Descriptions ........................................................... 495-7 PLL Control Register (PLLCTL) Field Descriptions .................................................................... 505-8 PLL Multiplier Control Register (PLLM) Field Descriptions ........................................................... 515-9 PLL Controller Divider 1 Register (PLLDIV1) Field Descriptions .................................................... 515-10 PLL Controller Divider 2 Register (PLLDIV2) Field Descriptions .................................................... 525-11 PLL Controller Divider 3 Register (PLLDIV3) Field Descriptions .................................................... 525-12 Oscillator Divider 1 Register (OSCDIV1) Field Descriptions ......................................................... 535-13 Bypass Divider Register (BPDIV) Field Descriptions .................................................................. 545-14 PLL Controller Command Register (PLLCMD) Field Descriptions................................................... 555-15 PLL Controller Status Register (PLLSTAT) Field Descriptions ....................................................... 555-16 PLL Controller Clock Align Control Register (ALNCTL) Field Descriptions ........................................ 565-17 PLLDIV Ratio Change Status Register (DCHANGE) Field Descriptions ........................................... 575-18 Clock Enable Control Register (CKEN) Field Descriptions ........................................................... 585-19 Clock Status Register (CKSTAT) Field Descriptions .................................................................. 595-20 SYSCLK Status Register (SYSTAT) Field Descriptions .............................................................. 606-1 DM643x DMP Default Module Configuration ........................................................................... 636-2 Module States .............................................................................................................. 646-3 IcePick Emulation Commands ............................................................................................ 666-4 PSC Interrupt Events ...................................................................................................... 666-5 Power and Sleep Controller (PSC) Registers .......................................................................... 686-6 Peripheral Revision and Class Information Register (PID) Field Descriptions ..................................... 696-7 Interrupt Evaluation Register (INTEVAL) Field Descriptions ......................................................... 696-8 Module Error Pending Register 1 (MERRPR1) Field Descriptions .................................................. 706-9 Module Error Clear Register 1 (MERRCR1) Field Descriptions ..................................................... 706-10 Power Domain Transition Command Register (PTCMD) Field Descriptions ....................................... 716-11 Power Domain Transition Status Register (PTSTAT) Field Descriptions ........................................... 716-12 Power Domain Status 0 Register (PDSTAT0) Field Descriptions ................................................... 726-13 Power Domain Control 0 Register (PDCTL0) Field Descriptions .................................................... 736-14 Module Status nRegister (MDSTAT n) Field Descriptions ............................................................ 746-15 Module Control nRegister (MDCTL n) Field Descriptions ............................................................. 757-1 Power Management Features ............................................................................................ 789-1 TMS320DM643x DMP Master IDs ....................................................................................... 889-2 TMS320DM643x DMP Default Master Priorities ....................................................................... 8910-1 Reset Types ................................................................................................................. 92A-1 Document Revision History ............................................................................................... 97
SPRU978E – March 2008 List of Tables 7Submit Documentation Feedback

List of Tables8 SPRU978E – March 2008Submit Documentation Feedback

PrefaceSPRU978E – March 2008
Read This First
About This Manual
This document describes the DSP subsystem in the TMS320DM643x Digital Media Processor (DMP).
Notational Conventions
This document uses the following conventions.•Hexadecimal numbers are shown with the suffix h. For example, the following number is 40hexadecimal (decimal 64): 40h.•Registers in this document are shown in figures and described in tables.– Each register figure shows a rectangle divided into fields that represent the fields of the register.Each field is labeled with its bit name, its beginning and ending bit numbers above, and itsread/write properties below. A legend explains the notation used for the properties.– Reserved bits in a register figure designate a bit that is used for future device expansion.
Related Documentation From Texas InstrumentsThe following documents describe the TMS320DM643x Digital Media Processor (DMP). Copies of thesedocuments are available on the Internet at www.ti.com .Tip: Enter the literature number in the search boxprovided at www.ti.com.
The current documentation that describes the DM643x DMP, related peripherals, and other technicalcollateral, is available in the C6000 DSP product folder at: www.ti.com/c6000 .
SPRU983 —TMS320DM643x DMP Peripherals Overview Reference Guide. Provides an overview andbriefly describes the peripherals available on the TMS320DM643x Digital Media Processor (DMP).
SPRAA84 —TMS320C64x to TMS320C64x+ CPU Migration Guide. Describes migrating from theTexas Instruments TMS320C64x digital signal processor (DSP) to the TMS320C64x+ DSP. Theobjective of this document is to indicate differences between the two cores. Functionality in thedevices that is identical is not included.
SPRU732 —TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide. Describes the CPUarchitecture, pipeline, instruction set, and interrupts for the TMS320C64x and TMS320C64x+ digitalsignal processors (DSPs) of the TMS320C6000 DSP family. The C64x/C64x+ DSP generationcomprises fixed-point devices in the C6000 DSP platform. The C64x+ DSP is an enhancement ofthe C64x DSP with added functionality and an expanded instruction set.
SPRU871 —TMS320C64x+ DSP Megamodule Reference Guide. Describes the TMS320C64x+ digitalsignal processor (DSP) megamodule. Included is a discussion on the internal direct memory access(IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidthmanagement, and the memory and cache.
SPRU862 —TMS320C64x+ DSP Cache User's Guide. Explains the fundamentals of memory cachesand describes how the two-level cache-based internal memory architecture in the TMS320C64x+digital signal processor (DSP) of the TMS320C6000 DSP family can be efficiently used in DSPapplications. Shows how to maintain coherence with external memory, how to use DMA to reducememory latencies, and how to optimize your code to improve cache efficiency. The internal memoryarchitecture in the C64x+ DSP is organized in a two-level hierarchy consisting of a dedicatedprogram cache (L1P) and a dedicated data cache (L1D) on the first level. Accesses by the CPU tothe these first level caches can complete without CPU pipeline stalls. If the data requested by theCPU is not contained in cache, it is fetched from the next lower memory level, L2 or externalmemory.
SPRU978E – March 2008 Read This First 9Submit Documentation Feedback

TMS320C6000, C6000 are trademarks of Texas Instruments.
Read This First10 SPRU978E – March 2008Submit Documentation Feedback

Chapter 1SPRU978E – March 2008
Introduction
Topic .................................................................................................. Page
1.1 Introduction .............................................................................. 121.2 Block Diagram .......................................................................... 121.3 DSP Subsystem in TMS320DM643x DMP ..................................... 13
SPRU978E – March 2008 Introduction 11Submit Documentation Feedback

www.ti.com
1.1 Introduction
1.2 Block Diagram
JTAG Interface
System Control
PLLs/Clock Generator
Input
Clock(s)
Power/Sleep Controller
Pin Multiplexing
DSP Subsystem
C64x+tDSP CPU
32 KB
L1 Pgm
128 KB L2 RAM
80 KB
L1 Data
BT.656,
Y/C,
Raw (Bayer)
Video Processing Subsystem (VPSS)
CCD
Controller
Video
Interface
Front End
Resizer
Histogram/
3A
Preview
10b DAC
On-Screen
Display
(OSD)
Video
Encoder
(VENC)
10b DAC
10b DAC
10b DAC
Back End 8b BT.656,
Y/C,
24b RGB
NTSC/
PAL,
S-Video,
RGB,
YPbPr
Switched Central Resource (SCR)
Peripherals
EDMA
I2C HECC UART
Serial Interfaces
DDR2
Mem Ctlr
(32b)
Async EMIF/
NAND/
(8b)
Program/Data Storage
Watchdog
Timer PWM
System
General-
Purpose
Timer
PCI
(33 MHz) VLYNQ EMAC
With
MDIO
Connectivity
HPI
McASP McBSP
OSC
Boot ROM
16b
GPIO
Introduction
The TMS320DM643x Digital Media Processor (DMP) contains a powerful DSP to efficiently handle image,video, and audio processing tasks. The DM643x DMP consists of the following primary components andsub-systems:
•DSP Subsystem (DSPSS), including the C64x+ Megamodule and associated memory.•Video Processing Subsystem (VPSS), including the Video Processing Front End (VPFE) Subsystem,Image Input and Image Processing Subsystem, and the Video Processing Back End (VPBE) DisplaySubsystem
•A set of I/O peripherals•A powerful DMA subsystem and DDR2 memory controller interface
The DSP subsystem includes TI’s standard TMS320C64x+ Megamodule and several blocks of internalmemory (L1P, L1D, and L2).
For more information, see the TMS320C64x+ DSP Megamodule Peripherals Reference Guide(SPRU871 ), the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (SPRU732 ), and theTMS320C64x+ DSP Cache User’s Guide (SPRU862 ).
An example block diagram for the TMS320DM643x DMP is shown in Figure 1-1 .
Figure 1-1. TMS320DM643x DMP Block Diagram
Introduction 12 SPRU978E – March 2008Submit Documentation Feedback

www.ti.com
1.3 DSP Subsystem in TMS320DM643x DMP
1.3.1 Components of the DSP Subsystem
DSP Subsystem in TMS320DM643x DMP
In the DM643x DMP, the DSP subsystem is responsible for performing digital signal processing for digitalmedia applications. In addition, the DSP subsystem acts as the overall system controller, responsible forhandling many system functions such as system-level initialization, configuration, user interface, usercommand execution, connectivity functions, and overall system control.
The DSP subsystem in the DM643x DMP consists of the following components:•C64x+ Megamodule
•DSP Internal Memories– Level-1 program memory (L1P)– Level-1 data memory (L1D)– Level-2 unified memory (L2)
The DSP also manages/controls all peripherals on the device. Refer to device-specific data manual for thefull list of peripherals.
Figure 1-1 shows the functional block diagram of the DM643x DMP and how the DSP subsystem isconnected to the rest of the device. The DM643x DMP architecture uses the System Infrastructure(Switched Central Resource) to transfer data within the system.
Chapter 2 discusses the C64x+ Megamodule in more details, including its detailed block diagram.
SPRU978E – March 2008 Introduction 13Submit Documentation Feedback

Introduction 14 SPRU978E – March 2008Submit Documentation Feedback

Chapter 2SPRU978E – March 2008
TMS320C64x+ Megamodule
Topic .................................................................................................. Page
2.1 Introduction .............................................................................. 162.2 TMS320C64x+ CPU .................................................................... 162.3 Memory Controllers ................................................................... 182.4 Internal Peripherals ................................................................... 22
SPRU978E – March 2008 TMS320C64x+ Megamodule 15Submit Documentation Feedback

www.ti.com
2.1 Introduction
2.2 TMS320C64x+ CPU
Introduction
The C64x+ Megamodule (Figure 2-1 ) consists of the following components:•TMS320C64x+ CPU•Internal memory controllers:– Level-1 program memory controller (L1P controller)– Level-1 data memory controller (L1D controller)– Level-2 unified memory controller (L2 controller)– External memory controller (EMC)– Internal direct memory access (IDMA) controller•Internal peripherals
– Interrupt controller (INTC)– Power-down controller (PDC)
The C64x+ Megamodule includes the C64x+ CPU. The C64x+ CPU is a member of the TMS320C6000™generation of devices. The C6000™ devices execute up to eight 32-bit instructions per cycle. The CPUconsists of 64 general-purpose 32-bit registers and eight functional units. The eight functional units containtwo multipliers and six ALUs. For more information on the CPU, see the TMS320C64x/C64x+ DSP CPUand Instruction Set Reference Guide (SPRU732 ).
Features of the C6000 devices include:•Advanced VLIW CPU with eight functional units, including two multipliers and six arithmetic units– Executes up to eight instructions per cycle for up to ten times the performance of typical DSPs– Allows designers to develop highly effective RISC-like code for rapid development time•Instruction packing– Gives code-size equivalence for eight instructions that execute serially or in parallel– Reduces code size, program fetches, and power consumption•Conditional execution of most instructions– Reduces costly branching– Increases parallelism for higher sustained performance•Efficient code execution on independent functional units– Industry's most efficient C compiler on DSP benchmark suite– Industry's first assembly optimizer for rapid development and improved parallelization•8/16/32-bit data support, providing efficient memory support for a variety of applications•40-bit arithmetic options add extra precision for vocoders and other computationally intensiveapplications
•Saturation and normalization provide support for key arithmetic operations•Field manipulation and instruction extract, set, clear, and bit counting support a common operationfound in control and data manipulation applications
The C64x+ devices include the following additional features:•Each multiplier can perform two 16 ×16-bit or four 8 ×8-bit multiplies every clock cycle•Quad 8-bit and dual 16-bit instruction set extensions with data flow support•Support for nonaligned 32-bit (word) and 64-bit (double word) memory accesses•Special communication-specific instructions to address common operations in error-correcting codes•Bit count and rotate hardware extends support for bit-level algorithms•Compact instructions: common instructions (AND, ADD, LD, MPY) have 16-bit versions to reduce codesize
16 TMS320C64x+ Megamodule SPRU978E – March 2008Submit Documentation Feedback

www.ti.com
Cache control
Memory protect
Bandwidth mgmt
L1P
RAM/
cache
256
Bandwidth mgmt
Memory protect
Cache control
256
L2
256
RAM/
Cache ROM
256
Instruction fetch
file A file B
C64x+ CPU
256
Cache control
Memory protect
Bandwidth mgmt
L1D
128 128
8 x 32
IDMA
256
256 128
256
Power down
Interrupt
controller
CFG
MDMA SDMA
EMC
256
32 Chip
registers
64 64
RAM/
cache
Register Register
System
infrastructure
TMS320C64x+ CPU
•Protected mode operation: a two-level system of privileged program execution to support highercapability operating systems and system features, such as memory protection•Exceptions support for error detection and program redirection to provide robust code execution•Hardware support for modulo loop operation to reduce code size•Industry's first assembly optimizer for rapid development and improved parallelization
Figure 2-1. TMS320C64x+ Megamodule Block Diagram
SPRU978E – March 2008 TMS320C64x+ Megamodule 17Submit Documentation Feedback

www.ti.com
2.3 Memory Controllers
2.3.1 L1P Controller
Memory Controllers
The C64x+ Megamodule implements a two-level internal cache-based memory architecture with externalmemory support. Level 1 memory is split into separate program memory (L1P memory) and data memory(L1D memory). Figure 2-2 shows a diagram of the memory architecture. L1P and L1D are configurable aspart L1 RAM (normal addressable on-chip memory) and part L1 cache. L1 memory is accessible to theCPU without stalls. Level 2 memory (L2) can also be split into L2 RAM (normal addressable on-chipmemory) and L2 cache for caching external memory locations.
The following controllers manage RAM/cache configuration and cache data paths:•L1P controller
•L1D controller
•L2 controller
•External memory controller (EMC)
The internal direct memory access (IDMA) controller manages DMA among the L1P, L1D, and L2memories.
This section briefly describes the cache and DMA controllers. For detailed information about each of thesecontrollers, see the TMS320C64x+ DSP Cache User’s Guide (SPRU862 ) and the TMS320C64x+ DSPMegamodule Reference Guide (SPRU871 ).
Note: The C64x+ Megamodule includes the memory controllers; however, the physical L1P, L1D,and L2 memories are not part of the megamodule, even though they reside in the DSPsubsystem. Thus, the physical memories are described separately because the C64x+Megamodule supports a variety of memory configurations. Refer to Section 3.1 for moreinformation on the L1P, L1D, and L2 memory configuration specific to the DM643x DMP.
The L1P controller is the hardware interface between level 1 program memory (L1P memory) and theother components in the C64x+ Megamodule (for example, C64x+ CPU, L2 controller, and EMC). TheL1P controller responds to instruction fetch requests from the C64x+ CPU and manages transferoperations between L1P memory and the L2 controller and between L1P memory and the EMC.
Refer to the device-specific data manual for the amount of L1P memory on the device. The L1P controllerhas a register interface that allows you to configure part or all of the L1P RAM as normal RAM or ascache. You can configure cache sizes of 0 KB, 4 KB, 8 KB, 16 KB, or 32 KB of the RAM.
The L1P is divided into two regions—denoted L1P region 0 and L1P region 1. This is the L1P architectureon the DM643x DMP:•L1P region 0: Not populated with memory.•L1P region 1: Populated with memory that can be configured as mapped memory or cache. The L1Pregion 1 memory has 0 wait state. This region is shown as “L1P RAM/Cache” in the device-specificdata manual.
The DM643x DMP does not support the L1P memory protection feature of the standardC64x+ Megamodule.
Refer to the TMS320C64x+ DSP Cache User’s Guide (SPRU862 ) and to the L1P controller section of theTMS320C64x+ DSP Megamodule Reference Guide (SPRU871 ) for more information on the L1P controllerand for a description of its control registers.
18 TMS320C64x+ Megamodule SPRU978E – March 2008Submit Documentation Feedback

www.ti.com
C64x+ CPU
Fetch Path Data Path
Write
Buffer
L1D
Cache
L1D
SRAM
L1 Data
L1P
Cache
L1P
SRAM
L1 Program
L2 Cache
L2 SRAM
L2 Unified Data/Program Memory
External Memory
64 bit
256 bit
128 bit
256 bit
256 bit
2 x 64 bit
Legend:
addressable memory
cache memory
data paths managed by
cache controller
256 bit
Memory Controllers
Figure 2-2. C64x+ Cache Memory Architecture
SPRU978E – March 2008 TMS320C64x+ Megamodule 19Submit Documentation Feedback

www.ti.com
2.3.2 L1D Controller
2.3.3 L2 Controller
Memory Controllers
The L1D controller is the hardware interface between level 1 data memory (L1D memory) and the othercomponents in the C64x+ Megamodule (for example, C64x+ CPU, L2 controller, and EMC). The L1Dcontroller responds to data requests from the C64x+ CPU and manages transfer operations between L1Dmemory and the L2 controller and between L1D memory and the EMC.
Refer to the device-specific data manual for the amount of L1D memory on the device. The L1D controllerhas a register interface that allows you to configure part of the L1D RAM as normal data RAM or ascache. You can configure cache sizes of 0 KB, 4 KB, 8 KB, 16 KB, or 32 KB of the RAM.
The L1D is divided into two regions—denoted L1D region 0 and L1D region 1. This is the L1D architectureon the DM643x DMP:•L1D region 0: On some DM643x devices, this region is populated with mapped memory. If it ispopulated with memory, this region is shown as “L1D RAM” in the device-specific data manual.•L1D region 1: Populated with memory that can be configured as mapped memory or cache. Thisregion is shown as “L1D RAM/Cache” in the device-specific data manual.
The DM643x DMP does not support the L1D memory protection features of the standardC64x+ Megamodule.
Refer to the TMS320C64x+ DSP Cache User’s Guide (SPRU862 ) and to the L1D controller section of theTMS320C64x+ DSP Megamodule Reference Guide (SPRU871 ) for more information on the L1D controllerand for a description of its control registers.
The L2 controller is the hardware interface between level 2 memory (L2 memory) and the othercomponents in the C64x+ Megamodule (for example, L1P controller, L1D controller, and EMC). The L2controller manages transfer operations between L2 memory and the other memory controllers (L1Pcontroller, L1D controller, and EMC).
Refer to device-specific data manual for the amount of L2 memory on the device. The L2 controller has aregister interface that allows you to configure part or all of the L2 RAM as normal RAM or as cache. Youcan configure cache sizes of 0 KB, 32 KB, 64 KB, or 128 KB of the RAM.
The L2 memory implements two separate memory ports. This is the L2 architecture on the DM643x DMP:•Port 0– Shown as “L2 RAM/Cache” in the device-specific data manual.– Banking scheme: 2 ×128-bit banks– Latency: 1 cycle (0 wait state)•Port 1– Shown as “Boot ROM” in the device-specific data manual.– Banking scheme: 1 ×256-bit bank– Latency: 1 cycle (0 wait state)
The DM643x DMP does not support the L2 memory protection feature of the standardC64x+ Megamodule.
Refer to the TMS320C64x+ DSP Cache User’s Guide (SPRU862 ) and to the L2 controller section of theTMS320C64x+ DSP Megamodule Reference Guide (SPRU871 ) for more information on the L2 controllerand for a description of its control registers.
TMS320C64x+ Megamodule20 SPRU978E – March 2008Submit Documentation Feedback