General Description
1-4
Introduction
The combination of the TMS320’s Harvard-type architecture (separate pro-
gram and data buses) and its special digital signal processing instruction set
providespeed andflexibility toexecute 12.8MIPS (millioninstructions perse-
cond). The TMS320 family optimizes speed by implementing functions in
hardware that other processors implement through software or microcode.
This hardware-intensive approach provides the design engineer with power
previously unavailable on a single chip.
The TMS320C2x generation includes six members: TMS320C25,
TMS320C25-33, TMS320C25-50, TMS320E25, TMS320C26, and
TMS320C28. Table 1–1 provides an overview of the TMS320C2x generation
of processors with comparisons of memory, I/O, cycle timing, and package
type.
Table 1–1.TMS320C2x Processors Overview
Device Memory
On-chip ROM/ Off-chip
RAM EPROM Prog Data I/O Ports †
Ser Par DMA
Cycle
Time
(ns)
Package
Type*
PGA PLCC CER QFP
TMS320C25‡ 544 4K 64K 64K Yes 16 ×16 Con 100 68 68 — —
TMS320C25-33 544 4K 64K 64K Yes 16 ×16 Con 120 —68——
TMS320C25-50§ 544 4K 64K 64K Yes 16 ×16 Con 80 —68——
TMS320E25§ 544 4K 64K 64K Yes 16 ×16 Con 100 — — 68 80
TMS320C26 1568 256 64K 64K Yes 16 ×16 Con 100 —68——
TMS320C28 544 8K 64K 64K Yes 16 ×16 Con 100 —68—80
†Ser = serial; Par = parallel; DMA = direct memory access; Con = concurrent DMA.
‡Military version available; contact nearest TI Field Sales Office for availability.
§Military version planned; contact nearest TI Field Sales Office for details.
*PGA = 68-pin grid array; PLCC = plastic-leaded chip carrier; CER = surface mount ceramic-leaded chip carrier (CER-QUAD);
QFP = plastic quad flat package
The TMS320C25, like all members of the TMS320C2x generation, is pro-
cessedin CMOS technology.TheTMS320C25iscapableofexecuting10mil-
lioninstructionspersecond. Enhanced featuressuchas24 additional instruc-
tions (133 total), eight auxiliary registers, an eight-level hardware stack, 4K
wordsofon-chipprogramROM,abit-reversedindexedaddressingmode,and
thelowpower dissipation inherent to the CMOS process contribute to the high
performance.
The TMS320C25-33 is a 33-MHz version of the TMS320C25. It is capable of
an instruction cycle of 120 ns. It is architecturally identical to the 40-MHz ver-
sionof theTMS320C25andispin-for-pinandobject-codecompatiblewith the
TMS320C25.
The TMS320C25-50 is a high-speed version of the TMS320C25. It is capable
ofaninstructioncycletimeof80ns.Itisarchitecturallyidenticaltothe40-MHz
versionof the TMS320C25 and is pin-for-pin and object-code compatible with
the TMS320C25.
