Texas Instruments TMS320C28x User manual

TMS320C28x DSP
CPU and Instruction Set
Reference Guide
Literature Number: SPRU430D
August 2001 −Revised March 2004

IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products Applications
Amplifiers amplifier.ti.com Audio www.ti.com/audio
Data Converters dataconverter.ti.com Automotive www.ti.com/automotive
DSP dsp.ti.com Broadband www.ti.com/broadband
Interface interface.ti.com Digital Control www.ti.com/digitalcontrol
Logic logic.ti.com Military www.ti.com/military
Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork
Microcontrollers microcontroller.ti.com Security www.ti.com/security
Telephony www.ti.com/telephony
Video & Imaging www.ti.com/video
Wireless www.ti.com/wireless
Mailing Address: Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2004, Texas Instruments Incorporated

iiiRead This First
Preface
Read This First
About This Manual
This manual describes the central processing unit (CPU) and the assembly language instructions of the
TMS320C28x 32-bit fixed-point digital signal processors (DSPs). It also describes emulation features
available on these DSPs. A summary of the chapters and appendixes follows:
Chapter 1 Architectural Overview
This chapter introduces the T320C2800 DSP core that is at the heart of each
TMS320C28x DSP. The chapter includes a memory map and a high-level de-
scription of the memory interface that connects the core with memory and
peripheral devices.
Chapter 2 Central Processing Unit
This chapter describes the architecture, registers, and primary functions of
the CPU. The chapter includes detailed descriptions of the flag and control
bits in the most important CPU registers, status registers ST0 and ST1.
Chapter 3 Interrupts and Reset
This chapter describes the interrupts and how they are handled by the CPU.
The chapter also explains the effects of a reset on the CPU and includes dis-
cussion of the automatic context save performed by the CPU prior to servic-
ing an interrupt.
Chapter 4 Pipeline
This chapter describes the phases and operation of the instruction pipeline.
The chapter is primarily for readers interested in increasing the efficiency of
their programs by preventing pipeline delays.
Chapter 5 Addressing Modes
This chapter explains the modes by which the assembly language instruc-
tions accept data and access register and memory locations. The chapter in-
cludes a description of how addressing-mode information is encoded in op-
codes.
Chapter 6 Assembly Language Instructions
This chapter provides summaries of the instruction set and detailed descrip-
tions (including examples) for the instructions. The chapter includes an ex-
planation of how 32-bit accesses are aligned to even addresses.

Notational Conventions
iv
Chapter 7 Emulation Features
This chapter describes the TMS320C28x emulation features that can be
used with only a JTAG port and two additional emulation pins.
Appendix A Register Quick Reference
This appendix is a concise central resource for information about the status
and control registers of the CPU. The chapter includes figures that summa-
rize the bit fields of the registers.
Appendix B Submitting ROM Codes to TI
This appendix describes the procedures for getting code-customized ROM
in a Texas Instruments (TI) DSP.
Appendix C C2xLP and C28x Architectural Differences
This appendix describes the differences in the architecture of the C2xLP and
the C28x.
Appendix D Migration From C2xLP
This appendix explains how to migrate code from the C2xLP to the C28x.
Appendix E C2xLP Instruction Set Compatibility
This appendix describes the instruction set compatibility with the C2xLP.
Appendix F Migration From C27x to C28x
This appendix explains how to migrate code from the C27x to the C28x.
Appendix G Glossary
This appendix explains abbreviations, acronyms, and special terminology
used throughout this document.
Notational Conventions
This document uses the following conventions:
-The device number TMS320C28x is very often abbreviated as ’28x.
-Program examples are shown in a special typeface. Here is a sam-
ple line of program code:
PUSH IER
-Portions of an instruction syntax that are in bold should be entered as
shown; portions of a syntax that are in italics are variables indicating in-
formation that should be entered. Here is an example of an instruction
syntax:
MOV ARx, *−SP[6bit]
MOV is the instruction mnemonic. This instruction has two operands, indi-
cated by ARxand *−SP[6bit]. Where the variable xappears, you type a
About This Manual / Notational Conventions

Notational Conventions
vRead This First
value from 0 to 5; where the 6bit appears, you type a 6-bit constant. The
rest of the instruction, including the square brackets, must be entered as
shown.
-When braces or brackets enclose an operand, as in {operand}, the oper-
and is optional. If you use an optional operand, you specify the information
within the braces; you do not enter the braces themselves. In the following
syntax, the operand << shift is optional:
MOV ACC, *−SP[6bit] {<<shift}
MOV ACC, *−SP{6bit} {<<shift}
For example, you could use either of the following instructions:
MOV ACC, *−SP[5]
MOV ACC, *−SP[5]<< 4
-In most cases, hexadecimal numbers are shown with a subscript of 16. For
example, the hexadecimal number 40 would be shown as 4016. An excep-
tion to this rule is a hexadecimal number in a code example; these hexade-
cimal numbers have the suffix h. For example, the number 40 in the follow-
ing code is a hexadecimal 40.
MOVB AR0,#40h
Similarly, binary numbers usually are shown with a subscript of 2. For ex-
ample, the binary number 4 would be shown as 01002. Binary numbers in
example code have the suffix b. For example, the following code uses a
binary 4.
MOVB AR0,#0100b
-Bus signals and bits are sometimes represented with the following nota-
tions:
Notation Description Example
Bus(n:m) Signals n through m of bus PRDB(31:0) represents the 32
signals of the program-read data
bus (PRDB).
Register(n:m) Bits n through m of register T(3:0) represents the 4 least sig-
nificant bits of the T register.
Register(n) Bit n of register IER(4) represents bit 4 of the in-
terrupt enable register (IER).

Related Documentation From Texas Instruments
vi
-Concatenated values are represented with the following notation:
Notation Description Example
x:y x concatenated with y AR1:AR0 is the concatenation of
the 16-bit registers AR1 and
AR0. AR0 is the low word. AR1
is the high word.
-If a signal is from an active-low pin, the name of the signal is qualified with
an overbar (for example, INT1). If a signal is from an active-high pin or from
hardware inside the the DSP (in which case, the polarity is irrelevant), the
name of the signal is left unqualified (for example, DLOGINT).
Related Documentation From Texas Instruments
The following books describe the TMS320C28x DSP and related support
tools. The documents are available for downloading on the Texas Instruments
website (www.ti.com).
TMS320C2xx User’s Guide (literature number SPRU127) discusses the
hardware aspects of the TMS320C2xx16-bit fixed-point digital signal
processors. It describes the architecture, the instruction set, and the on-
chip peripherals.
TMS320C28x Assembly Language Tools User’s Guide (literature number
SPRU513) describes the assembly language tools (assembler and other
tools used to develop assembly language code), assembler directives,
macros, common object file format, and symbolic debugging directives
for the TMS320C28xdevice.
TMS320C28x Optimizing C Compiler User’s Guide (literature number
SPRU514) describes the TMS320C28xC/C++ compiler. This compiler
accepts ANSI standard C/C++ source code and produces TMS320
DSP assembly language source code for the TMS320C28x device.
TMS320F2810, TMS320F2811, TMS320F2812, TMS320C2810,
TMS320C2811, and TMS320C2812 Digital Signal Processors
(literature number SPRS174) data sheet contains the electrical and
timing specifications for these devices, as well as signal descriptions and
pinouts for all of the available packages.
TMS320F2801, TMS320F2806, TMS320F2808 Digital Signal Processors
(literature number SPRS230) data sheet contains the pinout, signal de-
scriptions, as well as electrical and timing specifications for the F280x
devices.
Notational Conventions / Related Documentation From Texas Instruments

Related Documentation From Texas Instruments
viiRead This First
TMS320C2800 Digital Signal Processor (literature number SPRS178) data
sheet contains the block diagram, component descriptions, timing
information, and electrical specifications for the TMP320C2800 DSP.
TMS320C28x Analog-to-Digital Converter (ADC) Reference Guide (litera-
ture number SPRU060) describes the ADC module. The module is a
12−bit pipelined ADC. The analog circuits of this converter, referred to
as the core in this document, include the front-end analog multiplexers
(MUXs), sample−and−hold (S/H) circuits, the conversion core, voltage
regulators, and other analog supporting circuits. Digital circuits, referred
to as the wrapper in this document, include programmable conversion
sequencer, result registers, interface to analog circuits, interface to de-
vice peripheral bus, and interface to other on-chip modules.
TMS320C28x Boot ROM Reference Guide (literature number SPRU095)
describes the purpose and features of the bootloader (factory-pro-
grammed boot-loading software). It also describes other contents of the
device on-chip boot ROM and identifies where all of the information is lo-
cated within that memory.
TMS320C28x Enhanced Controller Area Network (eCAN) Reference
Guide (literature number SPRU074) describes the eCAN that uses es-
tablished protocol to communicate serially with other controllers in elec-
trically noisy environments. With 32 fully configurable mailboxes and
time-stamping feature, the eCAN module provides a versatile and robust
serial communication interface. The eCAN module implemented in the
C28x DSP is compatible with the CAN 2.0B standard (active).
TMS320C28x Event Manager (EV) Reference Guide (literature number
SPRU065) describes the EV modules that provide a broad range of func-
tions and features that are particularly useful in motion control and motor
control applications. The EV modules include general-purpose (GP) tim-
ers, full-compare/PWM units, capture units, and quadrature-encoder
pulse (QEP) circuits.
TMS320C28x External Interface (XINTF) Reference Guide (literature num-
ber SPRU067) describes the various interrupts and system control fea-
tures of the 28x digital signal processors (DSPs).
TMS320C28x Multi-channel Buffered Serial Ports (McBSPs) Reference
Guide(literature number SPRU061) describes the McBSP) available on
the C28x devices. The McBSPs allow direct interface between a DSP
and other devices in a system.
TMS320C28x Peripheral Reference Guide (literature number SPRU566)
describes the peripheral reference guides of the 28x digital signal proc-
essors (DSPs).

Trademarks
viii
TMS320C28x Serial Communication Interface (SCI) Reference Guide (lit-
erature number SPRU051) describes the SCI that is a two-wire asyn-
chronous serial port, commonly known as a UART. The SCI modules
support digital communications between the CPU and other asynchro-
nous peripherals that use the standard non-return-to-zero (NRZ) format.
TMS320C28x Serial Peripheral Interface (SPI) Reference Guide (literature
number SPRU059) describes the SPI −a high-speed synchronous serial
input/output (I/O) port that allows a serial bit stream of programmed
length (one to sixteen bits) to be shifted into and out of the device at a
programmed bit−transfer rate. The SPI is used for communications be-
tween the DSP controller and external peripherals or another controller.
TMS320C28x System Control and Interrupts Reference Guide (literature
number SPRU078) describes the various interrupts and system control
features of the 28x digital signal processors (DSPs).
Trademarks
320 Hotline On-line is a trademark of Texas Instruments Incorporated.
HP-UX is a trademark of Hewlett-Packard Company.
IBM and PC are trademarks of International Business Machines Corporation.
Intel is a trademark of Intel Corporation.
MS-DOS is a registered trademark of Microsoft Corporation.
PALis a registered trademark of Advanced Micro Devices, Inc.
SunOS is a trademark of Sun Microsystems, Inc.
C2xLP, C27x, C28x, TMS320C28x, and XDS510 are trademarks of Texas Instruments Incorporated.

Contents
ix
Contents
1 Architectural Overview 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduces the architecture and memory map of the T320C28x DSP CPU.
1.1 Introduction to the CPU 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.1 Compatibility With Other TMS320 CPUs 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1.2 Switching to C28x Mode From Reset 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Components of the CPU 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2.1 Central Processing Unit (CPU) 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2.2 Emulation Logic 1-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2.3 Signals 1-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Memory Map 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.1 On-Chip Program/Data 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.2 Reserved 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.3 CPU Interrupt Vectors 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Memory Interface 1-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4.1 Address and Data Buses 1-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4.2 Special Bus Operations 1-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4.3 Alignment of 32-Bit Accesses to Even Addresses 1-11. . . . . . . . . . . . . . . . . . . . . . .
2 Central Processing Unit 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Describes the registers and primary functions of the TMS320C28x CPU.
2.1 CPU Architecture 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 CPU Registers 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.1 Accumulator (ACC, AH, AL) 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.2 Multiplicand Register (XT) 2-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.3 Product Register (P, PH, PL) 2-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.4 Data Page Pointer (DP) 2-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.5 Stack Pointer (SP) 2-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.6 Auxiliary Registers (XAR0−XAR7, AR0−AR7) 2-12. . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.7 Program Counter (PC) 2-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.8 Return Program Counter (RPC) 2-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.9 Status Registers (ST0, ST1) 2-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.10 Interrupt-Control Registers (IFR, IER, DBGIER) 2-14. . . . . . . . . . . . . . . . . . . . . . . .
2.3 Status Register (ST0) 2-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Status Register ST1 2-34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 Program Flow 2-39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents
x
2.5.1 Interrupts 2-39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.2 Branches, Calls, and Returns 2-39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.3 Repeating a Single Instruction 2-39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.4 Instruction Pipeline 2-40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6 Multiply Operations 2-41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.1 16-bit X 16-bit Multiplication 2-41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.2 32-Bit X 32-Bit Multiplication 2-42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7 Shift Operations 2-44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 CPU Interrupts and Reset 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Describes the TMS320C28x interrupts and how they are handled by the CPU. Also
explains the effects of a hardware reset.
3.1 CPU Interrupts Overview 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 CPU Interrupt Vectors and Priorities 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Maskable Interrupts: INT1−INT14, DLOGINT, and RTOSINT 3-6. . . . . . . . . . . . . . . . . . . . .
3.3.1 CPU Interrupt Flag Register (IFR) 3-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.2 CPU Interrupt Enable Register (IER) and
CPU Debug Interrupt Enable Register (DBGIER) 3-8. . . . . . . . . . . . . . . . . . . . . . . .
3.4 Standard Operation for Maskable Interrupts 3-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5 Nonmaskable Interrupts 3-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.1 INTR Instruction 3-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.2 TRAP Instruction 3-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.3 Hardware Interrupt NMI 3-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6 Illegal-Instruction Trap 3-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7 Hardware Reset (RS) 3-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Pipeline 4-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Describes the phases and operation of the instruction pipeline.
4.1 Pipelining of Instructions 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.1 Decoupled Pipeline Segments 4-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.2 Instruction-Fetch Mechanism 4-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.3 Address Counters FC, IC, and PC 4-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 Visualizing Pipeline Activity 4-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 Freezes in Pipeline Activity 4-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.1 Wait States 4-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.2 Instruction-Not-Available Condition 4-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4 Pipeline Protection 4-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.1 Protection During Reads and Writes to the Same Data-Space Location 4-12. . . .
4.4.2 Protection Against Register Conflicts 4-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5 Avoiding Unprotected Operations 4-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.1 Unprotected Program-Space Reads and Writes 4-16. . . . . . . . . . . . . . . . . . . . . . . .
4.5.2 An Access to One Location That Affects Another Location 4-16. . . . . . . . . . . . . . .
4.5.3 Write Followed By Read Protection Mode 4-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 C28x Addressing Modes 5-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Describes the addressing modes of the C28x.
5.1 Types of Addressing Modes 5-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents
xiContents
5.2 Addressing Modes Select Bit (AMODE) 5-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3 Assembler/Compiler Tracking of AMODE Bit 5-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4 Direct Addressing Modes (DP) 5-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5 Stack Addressing Modes (SP) 5-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6 Indirect Addressing Modes 5-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6.1 C28x Indirect Addressing Modes (XAR0 to XAR7) 5-10. . . . . . . . . . . . . . . . . . . . . .
5.6.2 C2xLP Indirect Addressing Modes (ARP, XAR0 to XAR7) 5-12. . . . . . . . . . . . . . . .
5.6.3 Circular Indirect Addressing Modes (XAR6, XAR1) 5-21. . . . . . . . . . . . . . . . . . . . . .
5.7 Register Addressing Modes 5-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7.1 32-Bit Register Addressing Modes 5-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7.2 16-Bit Register Addressing Modes 5-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.8 Data/Program/IO Space Immediate Addressing Modes 5-28. . . . . . . . . . . . . . . . . . . . . . . . .
5.9 Program Space Indirect Addressing Modes 5-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.10 Byte Addressing Modes 5-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.11 Alignment of 32-Bit Operations 5-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 C28x Assembly Language Instructions 6-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Presents summaries of the instruction set, defines special symbols and notations used, and
describes each instruction in detail in alphabetical order.
6.1 Instruction Set Summary (Organized by Function) 6-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2 Register Operations 6-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7 Emulation Features 7-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Explains features supported by the T320C2800 CPU for testing and debugging programs.
7.1 Overview of Emulation Features 7-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2 Debug Interface 7-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3 Debug Terminology 7-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.4 Execution Control Modes 7-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.4.1 Stop Mode 7-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.4.2 Real-Time Mode 7-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.4.3 Summary of Stop Mode and Real-Time Mode 7-11. . . . . . . . . . . . . . . . . . . . . . . . . .
7.5 Aborting Interrupts With the ABORTI Instruction 7-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.6 DT-DMA Mechanism 7-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.7 Analysis Breakpoints, Watchpoints, and Counter(s) 7-19. . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.7.1 Analysis Breakpoints 7-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.7.2 Watchpoints 7-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.7.3 Benchmark Counter/Event Counter(s) 7-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.7.4 Typical Analysis Unit Configurations 7-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.8 Data Logging 7-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.8.1 Creating a Data Logging Transfer Buffer 7-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.8.2 Accessing the Emulation Registers Properly 7-26. . . . . . . . . . . . . . . . . . . . . . . . . . .
7.8.3 Data Log Interrupt (DLOGINT) 7-27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.8.4 Examples of Data Logging 7-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.9 Sharing Analysis Resources 7-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents
xii
7.10 Diagnostics and Recovery 7-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A Register Quick Reference A-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Is a concise, central resource for information about the status and control registers of the
TMS320C28x CPU.
A.1 Reset Values of and Instructions for Accessing the Registers A-2. . . . . . . . . . . . . . . . . . . . .
A.2 Register Figures A-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B Submitting ROM Codes to TI B-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Explains the process for submitting custom program code to TI for designing masks for the on-
chip ROM on a TMS320 DSP.
B.1 Introduction B-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B.2 Code Submission B-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B.3 ROM Layout B-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B.4 ROM Code Generation Flow B-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C C2xLP and C28x Architectural Differences C-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C.1 Summary of Architecture Differences Between C2xLP and C28x C-2. . . . . . . . . . . . . . . . . .
C.1.1 Enhancements of the C28x over the C2xLP: C-2. . . . . . . . . . . . . . . . . . . . . . . . . . . .
C.2 Registers C-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C.2.1 CPU Register Changes C-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C.2.2 Data Page (DP) Pointer Changes C-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C.2.3 Status Register Changes C-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C.2.4 Register Reset Conditions C-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C.3 Memory Map C-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D C2xLP Migration Guidelines D-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D.1 Introduction D-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D.2 Recommended Migration Flow D-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D.3 Mixing C2xLP and C28x Assembly D-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D.4 Code Examples D-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D.4.1 Boot Code for C28x operating mode initalization D-7. . . . . . . . . . . . . . . . . . . . . . . . .
D.4.2 IER/IFR Code D-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D.4.3 Context Save/Restore D-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D.5 Reference Tables for C2xLP Code Migration Topics D-10. . . . . . . . . . . . . . . . . . . . . . . . . . . .
E C2xLP Instruction Set Compatibility E-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Describes the instruction set compatibility between the C2xLP and the C28x.
E.1 Condition Tests on Flags E-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
E.2 C2xLP vs. C28x Mnemonics E-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
E.3 Repeatable Instructions E-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
F Migration From C27x to C28x F-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
F.1 Architecture Changes F-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
F.1.1 Changes to Registers F-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents
xiiiContents
F.1.2 Full Context Save and Restore F-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
F.1.3 B0/B1 Memory Map Consideration F-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
F.1.4 C27x Object Compatibility F-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
F.2 Moving to a C28x Object F-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
F.2.1 Caution When Changing OJBMODE F-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
F.3 Migrating to C28x Object Code F-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
F.3.1 Instruction Syntax Changes F-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
F.3.2 Repeatable Instructions F-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
F.3.3 Changes to the SUBCU Instruction F-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
F.4 Compiling C28x Source Code F-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figures
xiv
Figures
1−1. High-Level Conceptual Diagram of the CPU 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−2. TMS320C28x High-Level Memory Map 1-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−1. Conceptual Block Diagram of the CPU 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−2. C28x Registers 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−3. Individually Accessible Portions of the Accumulator 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−4. Individually Accessible Halves of the XT Register 2-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−5. Individually Accessible Halves of the P Register 2-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−6. Pages of Data Memory 2-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−7. Address Reach of the Stack Pointer 2-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−8. XAR0 −XAR7 Registers 2-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−9. XAR0 −XAR7 2-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−10. Bit Fields of Status Register (ST0) 2-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−11. Bit Fields of Status Register 1 (ST1) 2-34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−12. Conceptual Diagram of Components Involved in 16 X16-Bit Multiplication 2-42. . . . . . . . . . .
2−13. Conceptual Diagram of Components Involved in 32 X 32-Bit Multiplication 2-43. . . . . . . . . . .
3−1. Interrupt Flag Register (IFR) 3-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−2. Interrupt Enable Register (IER) 3-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−3. Debug Interrupt Enable Register (DBGIER) 3-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−4. Standard Operation for CPU Maskable Interrupts 3-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−5. Functional Flow Chart for an Interrupt Initiated by the TRAP Instruction 3-18. . . . . . . . . . . . .
5−1. Circular Buffer with AMODE = 0 5-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−2. Circular Buffer with AMODE = 1 5-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−1. JTAG Header to Interface a Target to the Scan Controller 7-3. . . . . . . . . . . . . . . . . . . . . . . . . .
7−2. Stop Mode Execution States 7-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−3. Real-time Mode Execution States 7-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−4. Stop Mode Versus Real-Time Mode 7-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−5. Process for Handling a DT-DMA Request 7-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−6. ADDRL (at Data-Space Address 00 083816) 7-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−7. ADDRH (at Data-Space Address 00 083916) 7-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−8. REFL (at Data-Space Address 00 084A16) 7-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−9. REFH (at Data-Space Address 00 084B16) 7-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−10. Valid Combinations of Analysis Resources 7-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A−1. Status register ST0 A-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A−2. Status register ST1, Bits15−8 A-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A−3. Status Register ST1, Bits 7−0 A-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A−4. Interrupt flag register (IFR) A-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figures
xvContents
A−5. Interrupt enable register (IER) A-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A−6. Debug interrupt enable register (DBGIER) A-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B−1. TMS320 ROM Code Prototype and Production Flowchart B-3. . . . . . . . . . . . . . . . . . . . . . . . . .
C−1. Register Changes From C2xLP to C28x C-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C−2. Direct Addressing Mode Mapping C-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C−3. Status Register Comparison Between C2xLP and C28x C-7. . . . . . . . . . . . . . . . . . . . . . . . . . . .
C−4. Memory Map Comparison (See Note A) C-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D−1. Flow Chart of Recommended Migration Steps D-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
F−1. C28x Registers F-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
F−2. Full Context Save/Restore F-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
F−3. Code for a Full Context Save/Restore for C28x vs C27x F-6. . . . . . . . . . . . . . . . . . . . . . . . . . . .
F−4. Mapping of Memory Blocks B0 and B1 on C27x F-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
F−5. C27x Compatible Mapping of Blocks M0 and M1 F-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
F−6. Building a C27x Object File From C27x Source F-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
F−7. Building a C28x Object File From Mixed C27x/C28x Source F-9. . . . . . . . . . . . . . . . . . . . . . . .
F−8. Compiling C28x Source F-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Tables
xvi
Tables
1−1. Compatibility Modes 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−2. Summary of Bus Use During Data-Space and Program-Space Accesses 1-10. . . . . . . . . . . .
1−3. Special Bus Operations 1-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−1. CPU Register Summary 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−2. Available Operations for Shifting Values in the Accumulator 2-8. . . . . . . . . . . . . . . . . . . . . . . . .
2−3. Product Shift Modes 2-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−4. Instructions That Affect OVC/OVCU 2-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−5. Instructions Affected by the PM Bits 2-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−6. Instructions Affected by V flag 2-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−7. Negative Flag Under Overflow Conditions 2-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−8. Bits Affected by the C Bit 2-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−9. Instructions That Affect the TC Bit 2-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−10. Instructions Affected by SXM 2-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−11. Shift Operations 2-45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−1. Interrupt Vectors and Priorities 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−2. Requirements for Enabling a Maskable Interrupt 3-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−3. Register Pairs Saved and SP Positions for Context Saves 3-14. . . . . . . . . . . . . . . . . . . . . . . .
3−4. Register Pairs Saved and SP Positions for Context Saves 3-20. . . . . . . . . . . . . . . . . . . . . . . .
3−5. Registers After Reset 3-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−1. Addressing Modes for “loc16” or “loc32” 5-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−1. Instruction Set Summary (Organized by Function) 6-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−2. Register Operations 6-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−1. 14-Pin Header Signal Descriptions 7-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−2. Selecting Device Operating Modes By Using TRST, EMU0, and EMU1 7-5. . . . . . . . . . . . . . .
7−3. Interrupt Handling Information By Mode and State 7-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−4. Start Address and DMA Registers 7-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−5. End-Address Registers 7-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−6. Analysis Resources 7-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A−1. Reset Values of the Status and Control Registers A-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B−1. Checksum Computation Memory Locations B-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C−1. General Features C-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C−2. C2xLP Product Mode Shifter C-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C−3. C28x Product Mode Shifter C-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C−4. Reset Conditions of Internal Registers C-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C−5. Status Register Bits C-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C−6. B0 Memory Map C-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Tables
xviiContents
D−1. Code to Save Contents Of IMR (IER) And Disabling Lower Priority Interrupts At
Beginning Of ISR D-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D−2. Code to Disable an Interrupt D-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D−3. Code to Enable an Interrupt D-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D−4. Code to Clear the IFR Register D-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D−5. Full Context Save/Restore Comparison D-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D−6. C2xLP and C28x Differences in Interrupts D-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D−7. C2xLP and C28x Differences in Status Registers D-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D−8. C2xLp and C28x Differences in Memory Maps D-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D−9. C2xLP and C28x Differences in Instructions and Registers D-13. . . . . . . . . . . . . . . . . . . . . . .
D−10. Code Generation Tools and Syntax Differences D-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
E−1. C28x and C2xLP Flags E-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
E−2. C2xLP Instructions and C28x Equivalent Instructions E-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
E−3. Repeatable Instructions for the C2xLP and C28x E-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
F−1. ST0 Register Bits F-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
F−2. ST1 Register Bits F-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
F−3. Instruction Syntax Change F-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Examples
xviii
Examples
3−1. Typical ISR 3-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−1. Relationship Between Pipeline and Address Counters FC, IC, and PC 4-6. . . . . . . . . . . . . . .
4−2. Diagramming Pipeline Activity 4-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−3. Simplified Diagram of Pipeline Activity 4-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−4. Conflict Between a Read From and a Write to Same Memory Location 4-13. . . . . . . . . . . . . .
4−5. Register Conflict 4-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−1. Initialization Code for Data Logging With Word Counter 7-28. . . . . . . . . . . . . . . . . . . . . . . . . . .
7−2. Initialization Code for Data Logging With End Address 7-29. . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-1
Architectural Overview
The TMS320C28xtis one of several fixed-point generations of digital signal
processors (DSPs) in the TMS320 family. The C28xtis source-code and ob-
ject-code compatible with the C27xt. In addition, much of the code written for
the C2xLP CPU can be reassembled to run on a C28x device.
The C2xLP CPU is used in all TMS320F24xx and TMS320C20x DSPs and
their derivatives. This document refers to C2xLP as a generic name for the
DSP CPU used in these devices.
This chapter provides an overview of the architectural structure and compo-
nents of the C28x CPU.
Topic Page
1.1 Introduction to the CPU 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Components of the CPU 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Memory Map 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Memory Interface 1-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 1

Introduction to the CPU
1-2
1.1 Introduction to the CPU
The CPU is a low-cost 32-bit fixed-point digital signal processor (DSP). This
device draws from the best features of digital signal processing; reduced
instruction set computing (RISC); and microcontroller architectures, firmware,
and tool sets. The DSP features include a modified Harvard architecture and
circular addressing. The RISC features are single-cycle instruction execution,
register-to-register operations, and modified Harvard architecture (usable in
Von Neumann mode). The microcontroller features include ease of use
through an intuitive instruction set, byte packing and unpacking, and bit manip-
ulation.
The modified Harvard architecture of the CPU enables instruction and data
fetches to be performed in parallel. The CPU can read instructions and data
while it writes data simultaneously to maintain the single-cycle instruction op-
eration across the pipeline. The CPU does this over six separate address/data
buses.
1.1.1 Compatibility With Other TMS320 CPUs
The C28x DSP features compatibility modes that minimize the migration effort
from the C27x and C2xLP CPUs. The operating mode of the device is
determined by a combination of the OBJMODE and AMODE bits in status
register 1 (ST1) as shown in Table 1−1. The OBJMODE bit allows you to select
between code compiled for a C28x (OBJMODE == 1) and code compiled for
a C27x (OBJMODE == 0). The AMODE bit allows you to select between
C28x/C27x instruction addressing modes (AMODE == 0) and C2xLP
compatible instruction addressing modes (AMODE == 1).
Table 1−1. Compatibility Modes
OBJMODE AMODE
C28x Mode 1 0
C2xLP Source-compatible Mode 1 1
C27x Object-compatible Mode†0 0
†The C28x is in C27x-compatible mode at reset.
-C28x Mode: In C28x mode, you can take advantage of all the C28x native
features, addressing modes, and instructions. To operate in C28x mode
from reset, your code must first set the OBJMODE bit by using the
”C28OBJ” (or ”SETC OBJMODE”) instruction. This book assumes you are
operating in C28x mode unless stated otherwise.
-C2xLP Source-Compatible Mode: C2xLP source-compatible mode al-
lows you to run C2xLP source code which has been reassembled using