Texas Instruments TAS5026REF User manual

TAS5026REF
Reference Design for the TAS5026 Digital Audio
PWM Processor
April 2003 Digital Audio/Application
User’s Guide
SLEU035

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Copyright 2003, Texas Instruments Incorporated

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Texas Instruments (TI) provides the enclosed product(s) under the following conditions:
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EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the specified input and output ranges described in
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Exceeding the specified input range may cause unexpected operation and/or irreversible
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Applyingloadsoutsideofthespecifiedoutputrangemayresultinunintendedoperationand/or
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please contact a TI field representative.
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60°C.TheEVM isdesignedto operateproperlywith certain componentsabove 60°C aslong
astheinputandoutput rangesare maintained.Thesecomponentsincludebut arenot limited
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typesof devicescanbeidentifiedusingtheEVM schematiclocated intheEVMUser’sGuide.
When placing measurement probes near these devices during operation, please be aware
that these devices may be very warm to the touch.
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Post Office Box 655303
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Copyright 2003, Texas Instruments Incorporated

Information About Cautions and Warnings
iii
Preface
Read This First
About This Manual
This manual describes the TAS5026REF reference design from Texas Instru-
ments.
How to Use This Manual
This document contains the following chapters:
-Chapter 1 –Introduction
-Chapter 2 –System Interfaces
-Chapter 3 –Schematic, Parts List, PCB Specification, and PCB Layout
Information About Cautions and Warnings
This book may contain cautions and warnings.
This is an example of a caution statement.
A caution statement describes a situation that could potentially
damage your software or equipment.
This is an example of a warning statement.
A warning statement describes a situation that could potentially
cause harm to you.
The information in a caution or a warning is provided for your protection.
Please read each caution and warning carefully.

Related Documentation From Texas Instruments
iv
Related Documentation From Texas Instruments
The following is a list of data manual that have detailed descriptions of the
integrated circuits used in the design of the TAS5026REF evaluation module.
The data manuals can be obtained at the URL http://www.ti.com.
Part Number Literature Number
TAS5026PFB
SN74LVC2G08DCTR
SN74LVC08APWR
SN74LVC126APWR
TPA112DGN
SLES041
SCES198
SCAS283
SCAS339
SLOS212
Trademarks
Equibit is a trademark of Texas Instruments.

Contents
v
Contents
1 Introduction 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 TAS5026REF Features 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 PCB Key Map 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Jumper Settings 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 System Interfaces 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Digital Audio Interface (J160) 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Control Interface (J100) 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 PWM Interface (J140) 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Schematic, Parts List, PCB Specification, and PCB Layout 3-1. . . . . . . . . . . . . . . . . . . . . . . . .
Figures
1–1 TDAA System With TAS5026REF and TAS5110D6REF Reference Designs 1-2. . . . . . . . . .
1–2 Physical Structure for the TAS5026REF (Rough Outline) 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . .
2–1 Pin Numbers at PWM Interface (J140) 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tables
2–1 Digital Audio Interface Pin Connections 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–2 Clock Rates 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–3 Control Interface Pin Connections 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–4 J140 Pin Description 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

vi

1-1
Introduction
The true digital audio amplifiers (TDAA) system consists of a PCM-PWM
modulatordeviceandaPWMpoweroutputdevice.ThePCM-PWMprocessor
accepts a serial PCM digital audio stream and converts it to a 3.3-V PWM
audio stream. The TDAA output stage provides a large-signal PWM output.
The digital PWM signal is then demodulated, providing power output for
driving loudspeakers. This patented technology provides low cost, high
quality, highly efficient digital audio applicable to many audio systems
developed for the digital age.
The TAS5026REF reference design demonstrates the integrated circuit
TAS5026 from Texas Instruments (TI). The TAS5026 is a 24-bit multichannel
digital pulse width modulator based on Equibittechnology. The TAS5026 is
designed to drive up to six digital power devices to provide six channels of
digital audio amplification. The digital power devices can be conventional
monolithic power stages (such as the TAS5110 or the TAS5112) or discrete
differential power stages using gate drivers and MOSFETs.
Topic Page
1.1 TAS5026REF Features 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 PCB Key Map 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Jumper Settings 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 1

1-2
TheTAS5026hassixindependentvolumecontrolswithsoftvolumeandmute.
The TAS5026 supports bridged output configurations. The device operates in
AD mode (2-level modulation scheme). This all-digital audio system contains
onlytwoanalogcomponents inthesignalchain–anLC low-passfilterateach
speaker terminal. The TAS5026 provides up to 96-dB SNR at the speaker
terminals. The TAS5026 has a wide variety of serial input options including
right justified (16, 20, or 24 bit), I2S (16, 20, or 24 bit), left justified, or DSP (16
bit) data formats. It is fully compatible with AES standard sampling rates of
44.1 kHz, 48 kHz, 88.2 kHz, and 96 kHz, including de-emphasis for 44.1-kHz
and48-kHzsamplerates.TheTAS5026plustheTAS51xxpowerstagedevice
combination can be used in a wide range of applications such as
microcomponent systems, home theater in a box (HTIB), DVD receivers, A/V
receivers, or TV sets.
Together with the TAS5110D6REF or the TAS5112D6REF module, the
TAS5026REF module is a complete true digital audio amplifiersystem, which
includesdigitalvolumecontrol,headphoneamplifier, and a subwoofer output.
Figure 1–1.TDAA System With TAS5026REF and TAS5110D6REF Reference Designs
TAS5026DREF
Module PWM Interface
Digital
Audio
Interface
Control
Interface
I2C Bus
Control Interface
I2S Bus
TAS5110D6REF
Module
1.1 TAS5026REF Features
-Six channel TDAA reference design (double-sided plated-through PCB
layout)
-Supports noiseless self-contained protection system (short circuit and
thermal) for the TAS5110 and the TAS5182 output stages. The
autorecovery loop is closed when JMP120 and JMP121 are shorted.
-Onboard headphone amplifier

1-3
1.2 PCB Key Map
The physical structure for the TAS5026REF is illustrated in Figure 1–2.
Figure 1–2.Physical Structure for the TAS5026REF (Rough Outline)
Head–
Phone
Out
(J320)
Headphone Amplifier
Section PWM Processor Section
PWM Interface
(J140)
Control Interface
(J100) Digital Audio Interface (J160)
TI
TAS5026REF
JMP120 JMP121
1.3 Jumper Settings
Together with the TAS5100/TAS5110/TAS5182 PWM output stages from
Texas Instruments, the TAS5026REF module can be configured in
autorecovery mode (closed loop).The SHUTDOWN signal(s) from the output
stageisconnectedtoerrorrecoveryatthePWMprocessorwhenJMP120and
JMP121 are shorted.
The autorecovery loop has to be disabled when the modulator board is
connected to an output stage module with autorecovery on-chip (e.g. the
TAS5111 and the TAS5112 reference modules). Autorecovery is disabled
when JMP120 and JMP 121 are removed.

1-4

2-1
System Interfaces
This chapter describes the TAS5026REF system interfaces.
Topic Page
2.1 Digital Audio Interface (J160) 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Control Interface (J100) 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 PWM Interface (J140) 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 2

2-2
2.1 Digital Audio Interface (J160)
The digital audio interface contains digital audio signal data (I2S), clocks, etc.
SeetheTAS5026datamanual,SLES041, for signal timing and details not ex-
plained in this document.
Table 2–1.Digital Audio Interface Pin Connections
Pin No. Net Name Description
01 GND Ground
02 MCLK-IN Not used
03 GND Ground
04 SDIN1 I2S data 1, channel 1 and 2 (left and right front speakers)
05 SDIN2 I2S data 2, channel 3 and 4 (left and right rear speakers)
06 SDIN3 I2S data 3, channel 5 and 6 (center speaker subwoofer)
07 GND Ground
08 GND Ground
09 GND Ground
10 GND Ground
11 SCLK I2Sbitclock(64xFs)usedtoshiftinserialdatafromSIN1,SDIN2,andSDIN3.SDATA
is sampled with the rising edge of the SCLK. The I2S format can be changed in the
I2C registers.
12 GND Ground
13 LRCLK Left/right clock (Fs) used to indicate left/right data being transmitted in SDATA. The
left channel is transmitted when LRCLK is low and the right channel is transmitted
when LRCLK is high.
14 GND Ground
15 Not used For future use
16 GND Ground
Table 2–2.Clock Rates
Sample Frequency LRCLK (Fs) SCLK (64 ×Fs) MCLK
32 kHz 32 kHz 2.048 MHz 8.192 MHz
Normal Speed
×
44.1 kHz 44.1 kHz 2.8224 MHz 11.2896 MHz
MCLK = 256 ×Fs 48 kHz 48 kHz 3.072 MHz 12.288 MHz
64 kHz 64 kHz 4.096 MHz 16.384 MHz
Double Speed
×
88.2 kHz 88.2 kHz 5.6448 MHz 22.5792 MHz
MCLK = 256 ×Fs 96 kHz 96 kHz 6.144 MHz 24.576 MHz
Quad Speed 176.4 kHz 176.4 kHz 11.2896 MHz 22.579 MHz Quad Speed
MCLK = 128 ×Fs 192 kHz 192 kHz 12.288 MHz 24.576 MHz

2-3
2.2 Control Interface (J100)
The control interface connects the TAS5026 board to the microcontroller
section.
Table 2–3.Control Interface Pin Connections
Pin No. Net Name Description
01 GND Ground
02 V-HBRIDGE-CONTROL Not used
03 GND Ground
04 RESET System reset (bidirectional). The TAS5026 enters a 4-ms initiation
sequence before PWM signals are present at the output.
If a quit reset is desired, MUTE should be asserted low before applying
RESET.
05 SOFT–RESET TAS5026 error recovery (active low). Enables the user to enter a reset
state click and pop free without resetting the I2C (volume) register
settings.
Bothsoftandhardresetsstoptheoutputstagefromswitchingandbrings
it into a low-low state, meaning the low-side MOSFET in both half
bridges is ON.
06 MUTE MUTE (active low) ramps the volume from any setting to noiseless soft
mute.
Alternatively, the mute mode can also be initiated through the serial
control interface (I2C).
07 POWER–DOWN POWER–DOWN(activelow)placestheTAS5026inpower-downmode.
During power down, all I2C and data bus operations are ignored.
If a quit power down is desired, MUTE should be asserted low before
applying RESET.
08 Not used
09 Not used
10 SDA I2C data clock
11 GND Ground
12 SCL I2C bit clock
13 Not used
14 I2C–ADDRESS–SELECT TAS5026 I2C address
select: Pin Level
Low
High
I2C Address
1Ah
1Bh
15 DOUBLE–SPEED DOUBLE–SPEED (active high) is used to support sampling rates of
88.2 kHz and 96 kHz.
Alternatively, the double-speed mode can also be initiated through the
serial control interface (I2C).
16 CLIP Digital clipping indicator (active low)
17 GND Ground
18 DEM-SEL2 De-emphasis filter select bit 1
DEM-SEL2
0
0
1
1
DEM-SEL1
0
1
0
1
MODE
De-emphasis disabled
De-emphasis enabled for Fs = 32 kHz
De-emphasis enabled for Fs = 44.1 kHz
De-emphasis enabled for Fs = 48 kHz

2-4
Table 2–3. Control Interface Pin Connections (Continued)
Pin No. Net Name Description
19 DEM-SEL1 De-emphasis filter select bit 1
20 SD–E1 Shutdown error reporting group 1. The TAS51XX digital output stages
(channel 1, 2, and 5) assert this signal low when an internal error occurs.
Thiscanbeduetoeitheranovertemperatureprotectionoranovercurrent
event.
21 SD–E2 Shutdown error reporting group 2. The TAS51XX digital output stages
(channel 3, 4, and 6) assert this signal low when an internal error occurs.
Thiscanbeduetoeitheranovertemperatureprotectionoranovercurrent
event.
22 ERROR0 Error reporting 0 (ERR0 from the TAS51XX output stages)
23 ERROR1 Error reporting 1 (ERR1 from the TAS51XX output stages)
24 HEADPHONE–DISABLE Headphone control
Headphone 1. Mute all channels (register address 03h)
enable sequence 2. HEADPHONE–DISABLE is asserted high.
3. Individual channel mute of channels 3–6
(register address 19h).
4. Unmuteallchannels(registeraddress03h).
Headphone 1. Mute all channels (register address 03h)
disable sequence 2. HEADPHONE–DISABLE is asserted low.
3. Unmute of channels 3–6 (register address
19h).
4. Unmuteallchannels(registeraddress03h).
Headphone 0 Headphone output disabled.
disable mode 1 Output stage channel 1 and 2 is muted.
Channel 3, 4, 5, and 6 should be muted
through the I2C interface.
25 GND Ground
26 GND Ground
27 Not used For future use
28 Not used For future use
29 Not used For future use
30 Not used For future use
31 GND Ground
32 GND Ground
33 +5V Power supply (out)
34 +5V Power supply (out)

2-5
2.3 PWM Interface (J140)
The PWM interface connects the TAS5026REF board to the output stage
module.
Figure 2–1.Pin Numbers at PWM Interface (J140)
2
31 5
64 8
97
10 12
1311 15
1614 18
1917
20 22
2321 25
2624 28
2927
30 32
3331 35
3634 38
3937
40 42
4341 45
4644 48
4947
50
Table 2–4.J140 Pin Description
Pin No. Net Name Description
01 V-HBRIDGE-CONTROL For future use
02 GND Ground
03 PWM–AP–1Channel 1 PWM input (differential +) –positive H-bridge side
04 PWM–AM–1Channel 1 PWM input (differential –) –positive H-bridge side
05 VALID–1Valid channel 1
06 PWM–BM–1Channel 1 PWM input (differential –) –negative H-bridge side
07 PWM–BP–1Channel 1 PWM input (differential +) –negative H-bridge side
08 GND Ground
09 PWM–AP–2Channel 2 PWM input (differential +) –positive H-bridge side
10 PWM–AM–2Channel 2 PWM input (differential –) –positive H-bridge side
11 VALID–2Valid channel 2
12 PWM–BM–2Channel 2 PWM input (differential –) –negative H-bridge side
13 PWM–BP–2Channel 2 PWM input (differential +) –negative H-bridge side
14 GND Ground
15 PWM–AP–3Channel 3 PWM input (differential +) –positive H-bridge side
16 PWM–AM–3Channel 3 PWM input (differential –) –positive H-bridge side
17 VALID–3Valid channel 3
18 PWM–BM–3Channel 3 PWM input (differential –) –negative H-bridge side
19 PWM–BP–3Channel 3 PWM input (differential +) –negative H-bridge side
20 GND Ground
21 PWM–AP–4Channel 4 PWM input (differential +) –positive H-bridge side
22 PWM–AM–4Channel 4 PWM input (differential –) –positive H-bridge side
23 VALID–4Valid channel 4
24 PWM–BM–4Channel 4 PWM input (differential –) –negative H-bridge side
25 PWM–BP–4Channel 4 PWM input (differential +) –negative H-bridge side
26 GND Ground
27 PWM–AP–5Channel 5 PWM input (differential +) –positive H-bridge side

2-6
Table 2–4. J100 Pin Description (Continued)
Pin No. Net Name Description
28 PWM–AM–5Channel 5 PWM input (differential –) –positive H-bridge side
29 VALID–5Valid channel 5
30 PWM–BM–5Channel 5 PWM input (differential –) –negative H-bridge side
31 PWM–BP–5Channel 5 PWM input (differential +) –negative H-bridge side
32 GND Ground
33 PWM–AP–6Channel 6 PWM input (differential +) –positive H-bridge side
34 PWM–AM–6Channel 6 PWM input (differential –) –positive H-bridge side
35 VALID–6Valid channel 6
36 PWM–BM–6Channel 6 PWM input (differential –) –negative H-bridge side
37 PWM–BP–6Channel 6 PWM input (differential +) –negative H-bridge side
38 SD–E1 Shutdown group 1 (center + left and right front speakers)
39 SD–E2 Shutdown group 2 (subwoofer + left and right rear speakers)
40 ERROR0 Error signal ERR0 from TAS5110
41 ERROR1 Error signal ERR1 from TAS5110
42 RESET System reset (bidirectional)
43 PSU–COMP–2For future use
44 PSU–COMP–1For future use
45 Not Used For future use
46 Not Used For future use
47 +3.3V 3.3-V supply voltage for the modulator module (e.g., the TAS5026REF)
48 GND Ground
49 +5V 5-V supply voltage
50 +5V 5-V supply voltage

3-1
Schematic, Parts List, PCB Specification, and
PCB Layout
The chapter contains the schematic, parts list, PCB specification, and PCB
layout for the TAS5026REF.
Chapter 3

TI DIGITAL AUDIO GROUP
ALL RIGHTS RESERVED - PATENTS PENDING
TEXAS INSTRUMENTS INCORPORATED
TI DIGITAL AUDIO GROUP
ALL RIGHTS RESERVED - PATENTS PENDING
TEXAS INSTRUMENTS INCORPORATED
Input & Output Section
TAS5026REF