Texas Instruments TMS320C6454 User manual

www.ti.com
PRODUCT PREVIEW
1 TMS320C6454 Fixed-Point Digital Signal Processor
1.1 Features
TMS320C6454Fixed-Point Digital Signal Processor
SPRS311A – APRIL 2006 – REVISED DECEMBER 2006
•32-Bit DDR2 Memory Controller (DDR2-533•High-Performance Fixed-Point DSP (C6454)
SDRAM)– 1.39-, 1.17-, and 1-ns Instruction Cycle Time
•EDMA3 Controller (64 Independent Channels)– 720-MHz, 850-MHz, and 1-GHz Clock Rate– Eight 32-Bit Instructions/Cycle
•32-/16-Bit Host-Port Interface (HPI)– 8000 MIPS/MMACS (16-Bits)
•32-Bit 33-/66-MHz, 3.3-V Peripheral Component– Commercial Temperature [0°C to 90°C]
Interconnect (PCI) Master/Slave InterfaceConforms to PCI Specification 2.3•TMS320C64x+™ DSP Core– Dedicated SPLOOP Instruction
•One Inter-Integrated Circuit (I
2
C) Bus– Compact Instructions (16-Bit)
•Two McBSPs– Instruction Set Enhancements
•10/100/1000 Mb/s Ethernet MAC (EMAC)– Exception Handling
– IEEE 802.3 Compliant•TMS320C64x+ Megamodule L1/L2 Memory
– Supports Multiple Media IndependentArchitecture:
Interfaces (MII, GMII, RMII, and RGMII)– 256K-Bit (32K-Byte) L1P Program Cache
– 8 Independent Transmit (TX) and[Direct Mapped]
8 Independent Receive (RX) Channels– 256K-Bit (32K-Byte) L1D Data Cache
•Two 64-Bit General-Purpose Timers,[2-Way Set-Associative]
Configurable as Four 32-Bit Timers– 8M-Bit (1048K-Byte) L2 Unified Mapped
•16 General-Purpose I/O (GPIO) PinsRAM/Cache [Flexible Allocation]
•System PLL and PLL Controller– 256K-Bit (32K-Byte) L2 ROM
•Secondary PLL and PLL Controller, Dedicated– Time Stamp Counter
to EMAC and DDR2 Memory Controller•Endianess: Little Endian, Big Endian
•IEEE-1149.1 (JTAG™)•64-Bit External Memory Interface (EMIFA)
Boundary-Scan-Compatible– Glueless Interface to Asynchronous
•697-Pin Ball Grid Array (BGA) PackageMemories (SRAM, Flash, and EEPROM) and
(ZTZ or GTZ Suffix), 0.8-mm Ball PitchSynchronous Memories (SBSRAM and ZBTSRAM)
•0.09- µm/7-Level Cu Metal Process (CMOS)– Supports Interface to Standard Sync
•3.3-/1.8-/1.5-V I/Os, 1.25-/1.2-V InternalDevices and Custom Logic (FPGA, CPLD,
•Pin-Compatible with the TMS320C6455ASICs, etc.)
Fixed-Point Digital Signal Processor– 32M-Byte Total Addressable ExternalMemory Space
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this document.All trademarks are the property of their respective owners.
PRODUCT PREVIEW information concerns products in the
Copyright © 2006–2006, Texas Instruments Incorporatedformative or design phase of development. Characteristic data andother specifications are design goals. Texas Instruments reservesthe right to change or discontinue these products without notice.

www.ti.com
PRODUCT PREVIEW
1.1.1 ZTZ/GTZ BGA Package (Bottom View)
ZTZ/GTZ 697-PIN BALL GRID ARRAY (BGA) PACKAGE
(BOTTOM VIEW)
A
2
B
1 3456789101112 131415
161718192021 222324
2526
C
DE
FG
HJ
KL
MN
PR
TU
VW
YAA
AB AC
AD AE
AF
2728 29
AG
AH AJ
NOTE: The ZTZ mechanical package designator represents the version of the GTZ package with lead-free balls. For more detailed information,
see the Mechanical Data section of this document.
1.2 Description
TMS320C6454
Fixed-Point Digital Signal Processor
SPRS311A – APRIL 2006 – REVISED DECEMBER 2006
The TMS320C6454 devices are designed for a package temperature range of 0°C to +90°C (commercialtemperature range).
Figure 1-1. ZTZ/GTZ BGA Package (Bottom View)
The TMS320C64x+™ DSPs (including the TMS320C6454 device) are the highest-performance fixed-pointDSP generation in the TMS320C6000™ DSP platform. The C6454 device is based on the third-generationhigh-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed byTexas Instruments (TI), making these DSPs an excellent choice for applications including video andtelecom infrastructure, imaging/medical, and wireless infrastructure (WI). The C64x+™ devices areupward code-compatible from previous devices that are part of the C6000™ DSP platform.
The C6454 offers a lower cost pin-compatible migration path for C6455 customers who don't need the2MB of the C6455 or the high-speed interconnect provided by Serial RapidIO. The C6454 also providesan excellent migration path for existing C6414/6415/6416 customers who require C6454 advancedperipherals; DDR2 at 533 MHz provides 2x performance boost over older SDRAM interface, gigabitEthernet provides low-cost high-performance ubiquitous packet interface, and 66-MHz PCI (revision 2.3complaint) provides legacy high-bandwidth interconnect.
Based on 90-nm process technology and with performance of up to 8000 million instructions per second(MIPS) [or 8000 16-bit MMACs per cycle] at a clock rate of 1 GHz, the C6454 device offers cost-effectivesolutions to high-performance DSP programming challenges. The C6454 DSP possesses the operationalflexibility of high-speed controllers and the numerical capability of array processors.
TMS320C6454 Fixed-Point Digital Signal Processor2Submit Documentation Feedback

www.ti.com
PRODUCT PREVIEW
TMS320C6454Fixed-Point Digital Signal Processor
SPRS311A – APRIL 2006 – REVISED DECEMBER 2006
The C64x+ DSP core employs eight functional units, two register files, and two data paths. Like the earlierC6000 devices, two of these eight functional units are multipliers or .M units. Each C64x+ .M unit doublesthe multiply throughput versus the C64x core by performing four 16-bit x 16-bit multiply-accumulates(MACs) every clock cycle. Thus, eight 16-bit x 16-bit MACs can be executed every cycle on the C64x+core. At a 1-GHz clock rate, this means 8000 16-bit MMACs can occur every second. Moreover, eachmultiplier on the C64x+ core can compute one 32-bit x 32-bit MAC or four 8-bit x 8-bit MACs every clockcycle.
The C6454 DSP integrates a large amount of on-chip memory organized as a two-level memory system.The level-1 (L1) program and data memories on the C6454 device are 32KB each. This memory can beconfigured as mapped RAM, cache, or some combination of the two. When configured as cache, L1program (L1P) is a direct mapped cache where as L1 data (L1D) is a two-way set associative cache. Thelevel 2 (L2) memory is shared between program and data space and is 1048KB in size. L2 memory canalso be configured as mapped RAM, cache, or some combination of the two. The C64x+ Megamodulealso has a 32-bit peripheral configuration (CFG) port, an internal DMA (IDMA) controller, a systemcomponent with reset/boot control, interrupt/exception control, a power-down control, and a free-running32-bit timer for time stamp.
The peripheral set includes: an inter-integrated circuit bus module (I2C); two multichannel buffered serialports (McBSPs); a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a peripheralcomponent interconnect (PCI); a 16-pin general-purpose input/output port (GPIO) with programmableinterrupt/event generation modes; an 10/100/1000 Ethernet media access controller (EMAC), whichprovides an efficient interface between the C6454 DSP core processor and the network; a managementdata input/output (MDIO) module (also part of the EMAC) that continuously polls all 32 MDIO addresses inorder to enumerate all PHY devices in the system; a glueless external memory interface (64-bit EMIFA),which is capable of interfacing to synchronous and asynchronous peripherals; and a 32-bit DDR2 SDRAMinterface.
The I2C ports on the C6454 allows the DSP to easily control peripheral devices and communicate with ahost processor. In addition, the standard multichannel buffered serial port (McBSP) may be used tocommunicate with serial peripheral interface (SPI) mode peripheral devices.
The C6454 has a complete set of development tools which includes: a new C compiler, an assemblyoptimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility intosource code execution.
Submit Documentation Feedback TMS320C6454 Fixed-Point Digital Signal Processor 3

www.ti.com
PRODUCT PREVIEW
1.3 Functional Block Diagram
L2 Memory Controller
(Memory Protect/
Bandwidth Mgmt)
DDR2
Mem Ctlr
System(B)
C64x+ DSP Core
Data Path B
B Register File
B31−B16
B15−B0
Instruction Fetch
Data Path A
A Register File
A31−A16
A15−A0
Device
Configuration
Logic
.L1 .S1 .M1
xx
xx .D1 .D2 .M2
xx
xx .S2 .L2
64
SBSRAM
SRAM
L1P Cache Direct-Mapped
32K Bytes
L1D Cache
2-Way
Set-Associative
32K Bytes Total
C6454
Primary Switched Central Resource
PLL1 and
PLL1
Controller
EMIFA
ZBT SRAM
HI
Boot Configuration
ROM/FLASH
I/O Devices
I2C
GPIO16(B)
16
McBSP0(A)
Internal DMA
(IDMA)
M
e
g
a
m
o
d
u
l
e
L2
Cache
Memory
1048K
Bytes
L1P Memory Controller (Memory Protect/Bandwidth Mgmt)
McBSP1(A)
HPI (32/16)(B)
Instruction
Decode
16-/32-bit
Instruction Dispatch
Control Registers
In-Circuit Emulation
DDR2 SDRAM 32
LO
Timer1(C)
HI
LO
Timer0(C)
PLL2 and
PLL2
Controller(D)
EMAC
10/100/1000
SPLOOP Buffer
Power Control
L1D Memory Controller (Memory Protect/Bandwidth Mgmt)
Interrupt and Exception Controller
EDMA 3.0
L2 ROM
32K
Bytes(E)
Secondary
Switched Central
Resource
A. McBSPs: Framing Chips − H.100, MVIP, SCSA, T1, E1; AC97 Devices; SPI Devices; Codecs
B. The PCI peripheral pins are muxed with some of the HPI peripheral pins. For more detailed information, see the Device Configuration section
of this document.
C. Each of the TIMER peripherals (TIMER1 and TIMER0) is configurable as either two 64-bit general-purpose timers or two 32-bit general-purpose
timers or a watchdog timer.
D. The PLL2 controller also generates clocks for the EMAC.
E. When accessing the internal ROM of the DSP, the CPU frequency must always be less than 750 MHz.
MDIO
RMGII(D)
GMII
RMII
MII
PCI66(B)
TMS320C6454
Fixed-Point Digital Signal Processor
SPRS311A – APRIL 2006 – REVISED DECEMBER 2006
Figure 1-2 shows the functional block diagram of the C6454 device.
Figure 1-2. Functional Block Diagram
TMS320C6454 Fixed-Point Digital Signal Processor4Submit Documentation Feedback

www.ti.com
PRODUCT PREVIEW
Contents
TMS320C6454Fixed-Point Digital Signal Processor
SPRS311A – APRIL 2006 – REVISED DECEMBER 2006
1 TMS320C6454 Fixed-Point Digital Signal 5.5 Megamodule Resets ................................ 81Processor .................................................. 1
5.6 Megamodule Revision ............................... 821.1 Features .............................................. 1
5.7 C64x+ Megamodule Register Description(s) ........ 831.1.1 ZTZ/GTZ BGA Package (Bottom View) .............. 2
6 Device Operating Conditions ........................ 901.2 Description ............................................ 2
6.1 Absolute Maximum Ratings Over Operating CaseTemperature Range (Unless Otherwise Noted) ..... 901.3 Functional Block Diagram ............................ 4
6.2 Recommended Operating Conditions ............... 902 Device Overview ......................................... 6
6.3 Electrical Characteristics Over Recommended2.1 Device Characteristics ................................ 6
Ranges of Supply Voltage and Operating Case2.2 CPU (DSP Core) Description ......................... 7
Temperature (Unless Otherwise Noted) ............ 922.3 Memory Map Summary ............................. 10
7 C64x+ Peripheral Information and Electrical2.4 Boot Sequence ...................................... 12
Specifications ........................................... 942.5 Pin Assignments .................................... 14
7.1 Parameter Information .............................. 942.6 Signal Groups Description .......................... 18
7.2 Recommended Clock and Control Signal TransitionBehavior ............................................. 962.7 Terminal Functions .................................. 24
7.3 Power Supplies ...................................... 962.8 Development ........................................ 47
7.4 Enhanced Direct Memory Access (EDMA3)3 Device Configuration .................................. 50
Controller ............................................ 983.1 Device Configuration at Device Reset .............. 50
7.5 Interrupts ........................................... 1123.2 Peripheral Configuration at Device Reset ........... 52
7.6 Reset Controller .................................... 1163.3 Peripheral Selection After Device Reset ............ 53
7.7 PLL1 and PLL1 Controller ......................... 1233.4 Device State Control Registers ..................... 55
7.8 PLL2 and PLL2 Controller ......................... 1383.5 Device Status Register Description ................. 65
7.9 DDR2 Memory Controller .......................... 1473.6 JTAG ID (JTAGID) Register Description ............ 67
7.10 External Memory Interface A (EMIFA) ............. 1493.7 Pullup/Pulldown Resistors ........................... 67
7.11 I2C Peripheral ...................................... 1603.8 Configuration Examples ............................. 69
7.12 Host-Port Interface (HPI) Peripheral ............... 1664 System Interconnect ................................... 71
7.13 Multichannel Buffered Serial Port (McBSP) ........ 1774.1 Internal Buses, Bridges, and Switch Fabrics ........ 71
7.14 Ethernet MAC (EMAC) ............................. 1874.2 Data Switch Fabric Connections .................... 72
7.15 Timers .............................................. 2054.3 Configuration Switch Fabric ......................... 74
7.16 Peripheral Component Interconnect (PCI) ......... 2074.4 Priority Allocation .................................... 76
7.17 General-Purpose Input/Output (GPIO) ............. 2145 C64x+ Megamodule .................................... 77
7.18 IEEE 1149.1 JTAG ................................. 2165.1 Memory Architecture ................................ 77
8 Mechanical Data ....................................... 2175.2 Memory Protection .................................. 80
8.1 Thermal Data ...................................... 2175.3 Bandwidth Management ............................ 80
8.2 Packaging Information ............................. 2175.4 Power-Down Control ................................ 81
Revision History ............................................ 218
Submit Documentation Feedback Contents 5

www.ti.com
PRODUCT PREVIEW
2 Device Overview
2.1 Device Characteristics
TMS320C6454
Fixed-Point Digital Signal Processor
SPRS311A – APRIL 2006 – REVISED DECEMBER 2006
Table 2-1 , provides an overview of the C6454 DSP. The tables show significant features of the C6454device, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package typewith pin count.
Table 2-1. Characteristics of the C6454 Processor
HARDWARE FEATURES C6454
EMIFA (64-bit bus width)
1(clock source = AECLKIN or SYSCLK4)DDR2 Memory Controller (32-bit bus width) [1.8 V I/O]
1(clock source = CLKIN2)EDMA3 (64 independent channels) [CPU/3 clock rate] 1I2C 1Peripherals
HPI (32- or 16-bit user selectable) 1 (HPI16 or HPI32)Not all peripherals pinsare available at the same
PCI (32-bit), [66-MHz or 33-MHz] 1 (PCI66 or PCI33)time (For more detail, see
McBSPs (internal CPU/6 or external clock source upthe Device Configuration
2to 100 Mbps)section).
10/100/1000 Ethernet MAC (EMAC) 1Management Data Input/Output (MDIO) 164-Bit Timers (Configurable)
2 64-bit or 4 32-bit(internal clock source = CPU/6 clock frequency)General-Purpose Input/Output Port (GPIO) 16Size (Bytes) 1144K32K-Byte (32KB) L1 Program Memory Controller[SRAM/Cache]On-Chip Memory
Organization 32KB Data Memory Controller [SRAM/Cache]1048KB L2 Unified Memory/Cache
32KB L2 ROMC64x+ Megamodule Megamodule Revision ID Register (address location:
See Section 5.6 ,Megamodule RevisionRevision ID 0181 2000h)
See Section 3.6 ,JTAG ID (JTAGID) RegisterJTAG BSDL_ID JTAGID register (address location: 0x02A80008)
DescriptionFrequency MHz 720, 850, and 1000 (1 GHz)1.39 ns (C6454-720), 1.17 ns (C6454-850),Cycle Time ns
1 ns (C6454-1000) [1 GHz CPU]1.25 V (-1000)Core (V)
1.2 V (-850/-720)Voltage
1.5/1.8 [EMAC RGMII], andI/O (V)
1.8 and 3.3 V [I/O Supply Voltage]PLL1 and PLL1
CLKIN1 frequency multiplier Bypass (x1), x15, x20, x25, x30, x32Controller Options
CLKIN2 frequency multiplierPLL2 x20[DDR2 Memory Controller and EMAC support only]
697-Pin Flip-Chip Plastic BGA (ZTZ)BGA Package 24 x 24 mm
697-Pin Plastic BGA (GTZ)Process Technology µm 0.09 µmProduct Preview (PP), Advance Information (AI),Product Status
(1)
PPor Production Data (PD)
(1) PRODUCT PREVIEW information concerns experimental products (designated as TMX) that are in the formative or design phase ofdevelopment. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change ordiscontinue these products without notice.
Device Overview6Submit Documentation Feedback

www.ti.com
PRODUCT PREVIEW
2.2 CPU (DSP Core) Description
TMS320C6454Fixed-Point Digital Signal Processor
SPRS311A – APRIL 2006 – REVISED DECEMBER 2006
Table 2-1. Characteristics of the C6454 Processor (continued)
HARDWARE FEATURES C6454
TMX320C6454ZTZ7,(For more details on the C64x+™ DSP partDevice Part Numbers TMX320C6454ZTZ8,numbering, see Figure 2-12 )
TMX320C6454ZTZ
The C64x+ Central Processing Unit (CPU) consists of eight functional units, two register files, and twodata paths as shown in Figure 2-1 . The two general-purpose register files (A and B) each contain32 32-bit registers for a total of 64 registers. The general-purpose registers can be used for data or can bedata address pointers. The data types supported include packed 8-bit data, packed 16-bit data, 32-bitdata, 40-bit data, and 64-bit data. Values larger than 32 bits, such as 40-bit-long or 64-bit-long values arestored in register pairs, with the 32 LSBs of data placed in an even register and the remaining 8 or32 MSBs in the next upper register (which is always an odd-numbered register).
The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing oneinstruction every clock cycle. The .M functional units perform all multiply operations. The .S and .L unitsperform a general set of arithmetic, logical, and branch functions. The .D units primarily load data frommemory to the register file and store results from the register file into memory.
The C64x+ CPU extends the performance of the C64x core through enhancements and new features.
Each C64x+ .M unit can perform one of the following each clock cycle: one 32 x 32 bit multiply, two16 x 16 bit multiplies, two 16 x 32 bit multiplies, four 8 x 8 bit multiplies, four 8 x 8 bit multiplies with addoperations, and four 16 x 16 multiplies with add/subtract capabilities (including a complex multiply). Thereis also support for Galois field multiplication for 8-bit and 32-bit data. Many communications algorithmssuch as FFTs and modems require complex multiplication. The complex multiply (CMPY) instruction takesfor 16-bit inputs and produces a 32-bit real and a 32-bit imaginary output. There are also complexmultiplies with rounding capability that produces one 32-bit packed output that contain 16-bit real and16-bit imaginary values. The 32 x 32 bit multiply instructions provide the extended precision necessary foraudio and other high-precision algorithms on a variety of signed and unsigned 32-bit data types.
The .L or (Arithmetic Logic Unit) now incorporates the ability to do parallel add/subtract operations on apair of common inputs. Versions of this instruction exist to work on 32-bit data or on pairs of 16-bit dataperforming dual 16-bit add and subtracts in parallel. There are also saturated forms of these instructions.
The C64x+ core enhances the .S unit in several ways. In the C64x core, dual 16-bit MIN2 and MAX2comparisons were only available on the .L units. On the C64x+ core they are also available on the .S unitwhich increases the performance of algorithms that do searching and sorting. Finally, to increase datapacking and unpacking throughput, the .S unit allows sustained high performance for the quad 8-bit/16-bitand dual 16-bit instructions. Unpack instructions prepare 8-bit data for parallel 16-bit operations. Packinstructions return parallel results to output precision including saturation support.
Submit Documentation Feedback Device Overview 7

www.ti.com
PRODUCT PREVIEW
TMS320C6454
Fixed-Point Digital Signal Processor
SPRS311A – APRIL 2006 – REVISED DECEMBER 2006
Other new features include:•SPLOOP - A small instruction buffer in the CPU that aids in creation of software pipelining loops wheremultiple iterations of a loop are executed in parallel. The SPLOOP buffer reduces the code sizeassociated with software pipelining. Furthermore, loops in the SPLOOP buffer are fully interruptible.•Compact Instructions - The native instruction size for the C6000 devices is 32 bits. Many commoninstructions such as MPY, AND, OR, ADD, and SUB can be expressed as 16 bits if the C64x+compiler can restrict the code to use certain registers in the register file. This compression isperformed by the code generation tools.•Instruction Set Enhancements - As noted above, there are new instructions such as 32-bitmultiplications, complex multiplications, packing, sorting, bit manipulation, and 32-bit Galois fieldmultiplication.
•Exception Handling - Intended to aid the programmer in isolating bugs. The C64x+ CPU is able todetect and respond to exceptions, both from internally detected sources (such as illegal op-codes) andfrom system events (such as a watchdog time expiration).•Privilege - Defines user and supervisor modes of operation, allowing the operating system to give abasic level of protection to sensitive resources. Local memory is divided into multiple pages, each withread, write, and execute permissions.•Time-Stamp Counter - Primarily targeted for Real-Time Operating System (RTOS) robustness, afree-running time-stamp counter is implemented in the CPU which is not sensitive to system stalls.
For more details on the C64x+ CPU and its enhancements over the C64x architecture, see the followingdocuments:
•TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732 )•TMS320C64x+ DSP Cache User's Guide (literature number SPRU862 )•TMS320C64x+ Megamodule Reference Guide (literature number SPRU871 )•TMS320C6455 Technical Reference (literature number SPRU965 )•TMS320C64x to TMS320C64x+ CPU Migration Guide (literature number SPRAA84 )
Device Overview8Submit Documentation Feedback

www.ti.com
PRODUCT PREVIEW
src2
src2
Á
Á
Á
Á
Á
Á
Á
.D1
.M1
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
.S1
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
.L1
long src
odd dst
src2
src1
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
src1
src1
src1
even dst
even dst
odd dst
dst1
dst
src2
src2
src2
long src
DA1
ST1b
LD1b
LD1a
ST1a
Data path A
Odd
register
file A
(A1, A3,
A5...A31)
Á
Á
Á
Odd
register
file B
(B1, B3,
B5...B31)
Á
Á
Á
.D2
Á
Á
Á
Á
src1
dst
src2
DA2
LD2a
LD2b
src2
.M2 src1
Á
Á
Á
dst1
Á
Á
Á
.S2 src1
Á
Á
Á
Á
even dst
long src
odd dst
ST2a
ST2b
long src
.L2
Á
Á
Á
Á
even dst
odd dst
Á
Á
Á
src1
Data path B
Control Register
32 MSB
32 LSB
dst2 (A)
32 MSB
32 LSB
2x
1x
32 LSB
32 MSB
32 LSB
32 MSB
dst2
(B)
(B)
(A)
8
8
8
8
32
32
32
32
(C)
(C)
Even
register
file A
(A0, A2,
A4...A30)
Even
register
file B
(B0, B2,
B4...B30)
(D)
(D)
(D)
(D)
A. On .M unit, dst2 is 32 MSB.
B. On .M unit, dst1 is 32 LSB.
C. On C64x CPU .M unit, src2 is 32 bits; on C64x+ CPU .M unit, src2 is 64 bits.
D. On .L and .S units, odd dst connects to odd register files and even dst connects to even register files.
TMS320C6454Fixed-Point Digital Signal Processor
SPRS311A – APRIL 2006 – REVISED DECEMBER 2006
Figure 2-1. TMS320C64x+™ CPU (DSP Core) Data Paths
Submit Documentation Feedback Device Overview 9

www.ti.com
PRODUCT PREVIEW
2.3 Memory Map Summary
TMS320C6454
Fixed-Point Digital Signal Processor
SPRS311A – APRIL 2006 – REVISED DECEMBER 2006
Table 2-2 shows the memory map address ranges of the C6454 device. The external memoryconfiguration register address ranges in the C6454 device begin at the hex address location 0x7000 0000for EMIFA and hex address location 0x7800 0000 for DDR2 Memory Controller.
Table 2-2. C6454 Memory Map Summary
MEMORY BLOCK DESCRIPTION BLOCK SIZE (BYTES) HEX ADDRESS RANGE
Reserved 1024K 0000 0000 - 000F FFFFInternal ROM 32K 0010 0000 - 0010 7FFFReserved 7M - 32K 0010 8000 - 007F FFFFInternal RAM (L2) [L2 SRAM] 1M 0080 0000 - 008F FFFFReserved 5M 0090 0000 - 00DF FFFFL1P SRAM 32K 00E0 0000 - 00E0 7FFFReserved 1M - 32K 00E0 8000 - 00EF FFFFL1D SRAM 32K 00F0 0000 - 00F0 7FFFReserved 1M - 32K 00F0 8000 - 00FF FFFFReserved 8M 0100 0000 - 017F FFFFC64x+ Megamodule Registers 4M 0180 0000 - 01BF FFFFReserved 12.5M 01C0 0000 - 0287 FFFFHPI Control Registers 256K 0288 0000 - 028B FFFFMcBSP 0 Registers 256K 028C 0000 - 028F FFFFMcBSP 1 Registers 256K 0290 0000 - 0293 FFFFTimer 0 Registers 256K 0294 0000 - 0297 FFFFTimer 1 Registers 128K 0298 0000 - 0299 FFFFPLL1 Controller (including Reset Controller) Registers 512 029A 0000 - 029A 01FFReserved 256K - 512 029A 0200 - 029B FFFFPLL2 Controller Registers 512 029C 0000 - 029C 01FFReserved 64K 029C 0200 - 029C FFFFEDMA3 Channel Controller Registers 32K 02A0 0000 - 02A0 7FFFReserved 96K 02A0 8000 - 02A1 FFFFEDMA3 Transfer Controller 0 Registers 32K 02A2 0000 - 02A2 7FFFEDMA3 Transfer Controller 1 Registers 32K 02A2 8000 - 02A2 FFFFEDMA3 Transfer Controller 2 Registers 32K 02A3 0000 - 02A3 7FFFEDMA3 Transfer Controller 3 Registers 32K 02A3 8000 - 02A3 FFFFReserved 256K 02A4 0000 - 02A7 FFFFChip-Level Registers 256K 02A8 0000 - 02AB FFFFDevice State Control Registers 256K 02AC 0000 - 02AF FFFFGPIO Registers 16K 02B0 0000 - 02B0 3FFFI2C Data and Control Registers 256K 02B0 4000 - 02B3 FFFFReserved 720K 02B4 0000 - 02BF FFFFPCI Control Registers 256K 02C0 0000 - 02C3 FFFFReserved 256K 02C4 0000 - 02C7 FFFFEMAC Control 4K 02C8 0000 - 02C8 0FFFEMAC Control Module Registers 2K 02C8 1000 - 02C8 17FFMDIO Control Registers 2K 02C8 1800 - 02C8 1FFFEMAC Descriptor Memory 8K 02C8 2000 - 02C8 3FFFReserved 496K 02C8 4000 - 02CF FFFFReserved 220M 02D0 0000 - 0FFF FFFFReserved 256M 1000 0000 - 1FFF FFFF
Device Overview10 Submit Documentation Feedback