Texas Instruments TMS320DM36 Series User manual

TMS320DM36x DMSoC
Multichannel Buffered Serial Port (McBSP)
Interface
User's Guide
Literature Number: SPRUFI3A
March 2009–Revised August 2009

2SPRUFI3A–March 2009–Revised August 2009
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Preface ....................................................................................................................................... 7
1 Introduction ...................................................................................................................... 10
1.1 Purpose of the Peripheral ............................................................................................. 10
1.2 Features ................................................................................................................. 10
1.3 Functional Block Diagram ............................................................................................. 11
1.4 Industry Standard Compliance Statement .......................................................................... 11
2 Peripheral Architecture ...................................................................................................... 12
2.1 Clock Control ........................................................................................................... 12
2.2 Signal Descriptions .................................................................................................... 12
2.3 Pin Multiplexing ........................................................................................................ 12
2.4 Endianness Considerations .......................................................................................... 12
2.5 Clock, Frames, and Data ............................................................................................. 13
2.6 McBSP Standard Operation .......................................................................................... 28
2.7 μ-Law/A-Law Companding Hardware Operation .................................................................. 41
2.8 Multichannel Selection Modes ....................................................................................... 44
2.9 SPI Operation Using the Clock Stop Mode ......................................................................... 52
2.10 Resetting the Serial Port: RRST, XRST, GRST, and RESET ................................................... 59
2.11 McBSP Initialization Procedure ...................................................................................... 60
2.12 Interrupt Support ....................................................................................................... 64
2.13 EDMA Event Support .................................................................................................. 65
2.14 Power Management ................................................................................................... 66
2.15 Emulation Considerations ............................................................................................. 66
3 Registers .......................................................................................................................... 67
3.1 Data Receive Register (DRR) ........................................................................................ 68
3.2 Data Transmit Register (DXR) ....................................................................................... 68
3.3 Serial Port Control Register (SPCR) ................................................................................ 69
3.4 Receive Control Register (RCR) ..................................................................................... 71
3.5 Transmit Control Register (XCR) .................................................................................... 73
3.6 Sample Rate Generator Register (SRGR) ......................................................................... 75
3.7 Multichannel Control Register (MCR) ............................................................................... 76
3.8 Enhanced Receive Channel Enable Registers (RCERE0-RCERE3) ........................................... 80
3.9 Enhanced Transmit Channel Enable Registers (XCERE0-XCERE3) ........................................... 82
3.10 Pin Control Register (PCR) ........................................................................................... 84
Appendix A Revision History ...................................................................................................... 86
3
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List of Figures
1 McBSP Block Diagram.................................................................................................... 11
2 Clock and Frame Generation ............................................................................................ 13
3 Transmit Data Clocking................................................................................................... 14
4 Receive Data Clocking.................................................................................................... 14
5 Sample Rate Generator Block Diagram................................................................................ 15
6 CLKG Synchronization and FSG Generation When GSYNC = 1 and CLKGDV = 1............................. 18
7 CLKG Synchronization and FSG Generation When GSYNC = 1 and CLKGDV = 3............................. 19
8 Digital Loopback Mode ................................................................................................... 19
9 Programmable Frame Period and Width............................................................................... 22
10 Dual-Phase Frame Example............................................................................................. 24
11 Single-Phase Frame of Four 8-Bit Elements .......................................................................... 25
12 Single-Phase Frame of One 32-Bit Element........................................................................... 26
13 Data Delay.................................................................................................................. 26
14 2-Bit Data Delay Used to Discard Framing Bit ........................................................................ 27
15 McBSP Standard Operation.............................................................................................. 28
16 Receive Operation......................................................................................................... 29
17 Transmit Operation........................................................................................................ 29
18 Maximum Frame Frequency for Transmit and Receive.............................................................. 30
19 Unexpected Frame Synchronization With (R/X)FIG = 0 ............................................................. 31
20 Unexpected Frame Synchronization With (R/X)FIG = 1 ............................................................. 32
21 Maximum Frame Frequency Operation With 8-Bit Data ............................................................. 33
22 Data Packing at Maximum Frame Frequency With (R/X)FIG = 1................................................... 33
23 Serial Port Receive Overrun ............................................................................................. 35
24 Serial Port Receive Overrun Avoided................................................................................... 35
25 Decision Tree Response to Receive Frame Synchronization Pulse................................................ 37
26 Unexpected Receive Frame Synchronization Pulse.................................................................. 37
27 Transmit With Data Overwrite ........................................................................................... 38
28 Transmit Empty............................................................................................................ 39
29 Transmit Empty Avoided ................................................................................................. 39
30 Decision Tree Response to Transmit Frame Synchronization Pulse............................................... 41
31 Unexpected Transmit Frame Synchronization Pulse................................................................. 41
32 Companding Flow ......................................................................................................... 42
33 Companding Data Formats .............................................................................................. 42
34 Transmit Data Companding Format in DXR........................................................................... 42
35 Companding of Internal Data ............................................................................................ 43
36 DX Timing for Multichannel Operation.................................................................................. 45
37 Alternating Between the Channels of Partition A and the Channels of Partition B ............................... 47
38 Reassigning Channel Blocks Throughout a McBSP Data Transfer ................................................ 47
39 McBSP Data Transfer in the 8-Partition Mode ........................................................................ 48
40 Activity on McBSP Pins for the Possible Values of XMCM.......................................................... 51
41 Typical SPI Interface...................................................................................................... 52
42 SPI Transfer with CLKSTP = 2h (no clock delay) and CLKXP = 0 ................................................. 54
43 SPI Transfer With CLKSTP = 3h (clock delay) and CLKXP = 0 .................................................... 54
44 SPI Transfer With CLKSTP = 2h (no clock delay) and CLKXP = 1................................................. 55
45 SPI Transfer With CLKSTP = 3h (clock delay) and CLKXP = 1 .................................................... 55
46 McBSP as the SPI Master................................................................................................ 57
47 Data Receive Register (DRR) ........................................................................................... 68
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48 Data Transmit Register (DXR)........................................................................................... 68
49 Serial Port Control Register (SPCR).................................................................................... 69
50 Receive Control Register (RCR) ........................................................................................ 71
51 Transmit Control Register (XCR)........................................................................................ 73
52 Sample Rate Generator Register (SRGR)............................................................................. 75
53 Multichannel Control Registers (MCR) ................................................................................. 76
54 Enhanced Receive Channel Enable Register n(RCEREn)......................................................... 80
55 Enhanced Transmit Channel Enable Register n(XCEREn)......................................................... 82
56 Pin Control Register (PCR) .............................................................................................. 84
5
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List of Tables
1 McBSP Interface Signals................................................................................................. 12
2 Choosing an Input Clock for the Sample Rate Generator With the
SCLKME and CLKSM Bits ............................................................................................... 16
3 Receive Clock Selection.................................................................................................. 20
4 Transmit Clock Selection................................................................................................. 21
5 Receive Frame Synchronization Selection............................................................................. 22
6 Transmit Frame Synchronization Selection............................................................................ 23
7 RCR/XCR Fields Controlling Elements per Frame and
Bits per Element........................................................................................................... 24
8 Receive/Transmit Frame Length Configuration ....................................................................... 24
9 Receive/Transmit Element Length Configuration ..................................................................... 25
10 Effect of RJUST Bit Values With 12-Bit Example Data ABCh....................................................... 27
11 Effect of RJUST Bit Values With 20-Bit Example Data ABCDEh................................................... 27
12 Justification of Expanded Data in DRR................................................................................. 42
13 Receive Channel Assignment and Control When Two Receive Partitions are Used ............................ 46
14 Transmit Channel Assignment and Control When Two Transmit Partitions are Used........................... 46
15 Receive Channel Assignment and Control When Eight Receive Partitions are Used ........................... 48
16 Transmit Channel Assignment and Control When Eight Transmit Partitions are Used.......................... 48
17 Selecting a Transmit Multichannel Selection Mode With the XMCM Bits.......................................... 49
18 Bits Used to Enable and Configure the Clock Stop Mode ........................................................... 53
19 Effects of CLKSTP and CLKXP Bits on the Clock Scheme ......................................................... 53
20 Bit Values Required to Configure the McBSP as an SPI Master ................................................... 57
21 Reset State of McBSP Pins.............................................................................................. 59
22 Receiver Clock and Frame Configurations............................................................................. 60
23 Transmitter Clock and Frame Configurations.......................................................................... 60
24 McBSP Emulation Modes Selectable With the FREE and SOFT Bits of SPCR .................................. 66
25 McBSP Registers.......................................................................................................... 67
26 Data Receive Register (DRR) Field Descriptions..................................................................... 68
27 Data Transmit Register (DXR) Field Descriptions .................................................................... 68
28 Serial Port Control Register (SPCR) Field Descriptions.............................................................. 69
29 Receive Control Register (RCR) Field Descriptions ................................................................. 71
30 Transmit Control Register (XCR) Field Descriptions ................................................................. 73
31 Sample Rate Generator Register (SRGR) Field Descriptions....................................................... 75
32 Multichannel Control Register (MCR) Field Descriptions ............................................................ 76
33 Enhanced Receive Channel Enable Register n(RCEREn) Field Descriptions ................................... 80
34 Use of the Receive Channel Enable Registers........................................................................ 81
35 Enhanced Transmit Channel Enable Register n(XCEREn) Field Descriptions................................... 82
36 Use of the Transmit Channel Enable Registers....................................................................... 83
37 Pin Control Register (PCR) Field Descriptions ........................................................................ 84
38 Document Revision History .............................................................................................. 86
6List of Tables SPRUFI3A–March 2009–Revised August 2009
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Preface
SPRUFI3A–March 2009–Revised August 2009
Read This First
About This Manual
Describes the operation of the multichannel buffered serial port (McBSP) interface in the TMS320DM6x
Digital Media System-on-Chip (DMSoC) . The McBSP consists of a data path and a control path that
connect to external devices. Separate pins for transmission and reception communicate data to these
external devices. The device's CPU communicates to the McBSP using 32-bit-wide control registers
accessible via the internal peripheral bus.
Notational Conventions
This document uses the following conventions.
• Hexadecimal numbers are shown with the suffix h. For example, the following number is 40
hexadecimal (decimal 64): 40h.
• Registers in this document are shown in figures and described in tables.
– Each register figure shows a rectangle divided into fields that represent the fields of the register.
Each field is labeled with its bit name, its beginning and ending bit numbers above, and its
read/write properties below. A legend explains the notation used for the properties.
– Reserved bits in a register figure designate a bit that is used for future device expansion.
Related Documentation from Texas Instruments
The following documents describe the TMS320DM36x Digital Media System-on-Chip (DMSoC). Copies of
these documents are available on the internet at www.ti.com.
SPRUFG5 —TMS320DM365 Digital Media System-on-Chip (DMSoC) ARM Subsystem Reference
Guide This document describes the ARM Subsystem in the TMS320DM36x Digital Media
System-on-Chip (DMSoC). The ARM subsystem is designed to give the ARM926EJ-S (ARM9)
master control of the device. In general, the ARM is responsible for configuration and control of the
device; including the components of the ARM Subsystem, the peripherals, and the external
memories.
SPRUFG8 —TMS320DM36x Digital Media System-on-Chip (DMSoC) Video Processing Front End
(VPFE) Users Guide This document describes the Video Processing Front End (VPFE) in the
TMS320DM36x Digital Media System-on-Chip (DMSoC).
SPRUFG9 —TMS320DM36x Digital Media System-on-Chip (DMSoC) Video Processing Back End
(VPBE) Users Guide This document describes the Video Processing Back End (VPBE) in the
TMS320DM36x Digital Media System-on-Chip (DMSoC).
SPRUFH0 —TMS320DM36x Digital Media System-on-Chip (DMSoC) 64-bit Timer Users Guide This
document describes the operation of the software-programmable 64-bit timers in the
TMS320DM36x Digital Media System-on-Chip (DMSoC).
SPRUFH1 —TMS320DM36x Digital Media System-on-Chip (DMSoC) Serial Peripheral Interface
(SPI) Users Guide This document describes the serial peripheral interface (SPI) in the
TMS320DM36x Digital Media System-on-Chip (DMSoC). The SPI is a high-speed synchronous
serial input/output port that allows a serial bit stream of programmed length (1 to 16 bits) to be
shifted into and out of the device at a programmed bit-transfer rate. The SPI is normally used for
communication between the DMSoC and external peripherals. Typical applications include an
interface to external I/O or peripheral expansion via devices such as shift registers, display drivers,
SPI EPROMs and analog-to-digital converters.
7
SPRUFI3A–March 2009–Revised August 2009 Preface
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Related Documentation from Texas Instruments www.ti.com
SPRUFH2 —TMS320DM36x Digital Media System-on-Chip (DMSoC) Universal Asynchronous
Receiver/Transmitter (UART) Users Guide This document describes the universal asynchronous
receiver/transmitter (UART) peripheral in the TMS320DM36x Digital Media System-on-Chip
(DMSoC). The UART peripheral performs serial-to-parallel conversion on data received from a
peripheral device, and parallel-to-serial conversion on data received from the CPU.
SPRUFH3 —TMS320DM36x Digital Media System-on-Chip (DMSoC) Inter-Integrated Circuit (I2C)
Peripheral Users Guide This document describes the inter-integrated circuit (I2C) peripheral in the
TMS320DM36x Digital Media System-on-Chip (DMSoC). The I2C peripheral provides an interface
between the DMSoC and other devices compliant with the I2C-bus specification and connected by
way of an I2C-bus.
SPRUFH5 —TMS320DM36x Digital Media System-on-Chip (DMSoC) Multimedia Card
(MMC)/Secure Digital (SD) Card Controller Users Guide This document describes the
multimedia card (MMC)/secure digital (SD) card controller in the TMS320DM36x Digital Media
System-on-Chip (DMSoC).
SPRUFH6 —TMS320DM36x Digital Media System-on-Chip (DMSoC) Pulse-Width Modulator (PWM)
Users Guide This document describes the pulse-width modulator (PWM) peripheral in the
TMS320DM36x Digital Media System-on-Chip (DMSoC).
SPRUFH7 —TMS320DM36x Digital Media System-on-Chip (DMSoC) Real-Time Out (RTO)
Controller Users Guide This document describes the Real Time Out (RTO) controller in the
TMS320DM36x Digital Media System-on-Chip (DMSoC).
SPRUFH8 —TMS320DM36x Digital Media System-on-Chip (DMSoC) General-Purpose Input/Output
(GPIO) Users Guide This document describes the general-purpose input/output (GPIO) peripheral
in the TMS320DM36x Digital Media System-on-Chip (DMSoC). The GPIO peripheral provides
dedicated general-purpose pins that can be configured as either inputs or outputs.
SPRUFH9 —TMS320DM36x Digital Media System-on-Chip (DMSoC) Universal Serial Bus (USB)
Controller Users Guide This document describes the universal serial bus (USB) controller in the
TMS320DM36x Digital Media System-on-Chip (DMSoC). The USB controller supports data
throughput rates up to 480 Mbps. It provides a mechanism for data transfer between USB devices
and also supports host negotiation.
SPRUFI0 —TMS320DM36x Digital Media System-on-Chip (DMSoC) Enhanced Direct Memory
Access (EDMA) Controller Users Guide This document describes the operation of the enhanced
direct memory access (EDMA3) controller in the TMS320DM36x Digital Media System-on-Chip
(DMSoC). The EDMA controller's primary purpose is to service user-programmed data transfers
between two memory-mapped slave endpoints on the DMSoC.
SPRUFI1 —TMS320DM36x Digital Media System-on-Chip (DMSoC) Asynchronous External
Memory Interface (EMIF) Users Guide This document describes the asynchronous external
memory interface (EMIF) in the TMS320DM36x Digital Media System-on-Chip (DMSoC). The EMIF
supports a glueless interface to a variety of external devices.
SPRUFI2 —TMS320DM36x Digital Media System-on-Chip (DMSoC) DDR2/Mobile DDR
(DDR2/mDDR) Memory Controller Users Guide This document describes the DDR2/mDDR
memory controller in the TMS320DM36x Digital Media System-on-Chip (DMSoC). The
DDR2/mDDR memory controller is used to interface with JESD79D-2A standard compliant DDR2
SDRAM and mobile DDR devices.
SPRUFI3 —TMS320DM36x Digital Media System-on-Chip (DMSoC) Multibuffered Serial Port
Interface (McBSP) User's Guide This document describes the operation of the multibuffered serial
host port interface in the TMS320DM36x Digital Media System-on-Chip (DMSoC). The primary
audio modes that are supported by the McBSP are the AC97 and IIS modes. In addition to the
primary audio modes, the McBSP supports general serial port receive and transmit operation.
SPRUFI4 —TMS320DM36x Digital Media System-on-Chip (DMSoC) Universal Host Port Interface
(UHPI) User's Guide This document describes the operation of the universal host port interface in
the TMS320DM36x Digital Media System-on-Chip (DMSoC).
8Read This First SPRUFI3A–March 2009–Revised August 2009
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www.ti.com Related Documentation from Texas Instruments
SPRUFI5 —TMS320DM36x Digital Media System-on-Chip (DMSoC) Ethernet Media Access
Controller (EMAC) User's Guide This document describes the operation of the ethernet media
access controller interface in the TMS320DM36x Digital Media System-on-Chip (DMSoC).
SPRUFI7 —TMS320DM36x Digital Media System-on-Chip (DMSoC) Analog to Digital Converter
(ADC) User's Guide This document describes the operation of the analog to digital conversion in
the TMS320DM36x Digital Media System-on-Chip (DMSoC).
SPRUFI8 —TMS320DM36x Digital Media System-on-Chip (DMSoC) Key Scan User's Guide This
document describes the key scan peripheral in the TMS320DM36x Digital Media System-on-Chip
(DMSoC).
SPRUFI9 —TMS320DM36x Digital Media System-on-Chip (DMSoC) Voice Codec User's Guide This
document describes the voice codec peripheral in the TMS320DM36x Digital Media
System-on-Chip (DMSoC). This module can access ADC/DAC data with internal FIFO (Read
FIFO/Write FIFO). The CPU communicates to the voice codec module using 32-bit-wide control
registers accessible via the internal peripheral bus.
SPRUFJ0 —TMS320DM36x Digital Media System-on-Chip (DMSoC) Power Management and
Real-Time Clock Subsystem (PRTCSS) User's Guide This document provides a functional
description of the Power Management and Real-Time Clock Subsystem (PRTCSS) in the
TMS320DM36x Digital Media System-on-Chip (DMSoC) and PRTC interface (PRTCIF).
SPRUGG8 —TMS320DM36x Digital Media System-on-Chip (DMSoC) Face Detection User's GuideThis
document describes the face detection capabilities for the TMS320DM36x Digital Media
System-on-Chip (DMSoC).
SPI is a trademark of Motorola, Inc..
9
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User's Guide
SPRUFI3A–March 2009–Revised August 2009
TMS320DM36x Multichannel Buffered Serial Port (McBSP)
Interface
1 Introduction
This document describes the operation of the multichannel buffered serial port (McBSP) interface in the
DM36x processor. Separate pins for transmission and reception communicate data to these external
devices. The CPU communicates to the McBSP using 32-bit-wide control registers accessible via the
internal peripheral bus.
1.1 Purpose of the Peripheral
The primary use for the multichannel buffered serial port (McBSP) is for audio interface purposes. The
primary audio modes that are supported are the AC97 and IIS modes. In addition to the primary audio
modes, the McBSP can be programmed to support other serial formats but is not intended to be used as a
high-speed interface.
1.2 Features
The McBSP provides the following functions:
• Full-duplex communication
• Double-buffered data registers, which allow a continuous data stream
• Independent framing and clocking for receive and transmit
• Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially
connected analog-to-digital (A/D) and digital-to-analog (D/A) devices
• External shift clock or an internal, programmable frequency shift clock for data transfer
In addition, the McBSP has the following capabilities:
• Direct interface to:
– T1/E1 framers
– MVIP switching compatible and ST-BUS compliant devices including:
• MVIP framers
• H.100 framers
• SCSA framers
– IOM-2 compliant devices
– AC97 compliant devices (the necessary multiphase frame synchronization capability is provided)
– IIS compliant devices
– SPI™ devices(master mode only)
• Multichannel transmit and receive of up to 128 channels
• A wide selection of data sizes, including 8, 12, 16, 20, 24, and 32 bits
•μ-Law and A-Law companding
• 8-bit data transfers with the option of LSB or MSB first
• Programmable polarity for both frame synchronization and data clocks
• Highly programmable internal clock and frame generation
10 TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface SPRUFI3A–March 2009–Revised August 2009
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SRGR
RBR
MCBSP_CLKS
MCBSP_FSR
MCBSP_FSX
MCBSP_CLKR
MCBSP_DX
MCBSP_DR
XEVT
REVT
XINT
RINT Interrupts
to CPU
McBSP
Compand
XSR
RSR
Compress
Expand DRR
DXR
Multichannel
selection
and control
generation
frame sync
Clock and
PCR
XCER
RCER
MCR
XCR
SPCR
RCR
Synchronization
events to DMA
32-bit
peripheral
bus
MCBSP_CLKX
www.ti.com Introduction
1.3 Functional Block Diagram
The McBSP consists of a data path and control path, as shown in Figure 1
Figure 1. McBSP Block Diagram
1.4 Industry Standard Compliance Statement
The McBSP supports the following industry standard interfaces:
AC97— The AC97 standard specifies a 5-wire digital serial link between an audio codec device and its
digital controller.
IIS— IIS is a protocol for transmitting two channels of digital audio data over a single serial connection.
The IIS bus is an industry standard three-wire interface for streaming stereo audio between
devices, typically between an ARM and a DAC/ADC.
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2 Peripheral Architecture
This section describes the architecture of the McBSP.
2.1 Clock Control
The McBSP can use an internal or external clock source. The internal clock source to the McBSP is an
output of the PLL controller. Either clock source can be divided-down inside the McBSP to generate the
actual interface bit clock frequency. For detailed timing information, see the device-specific data manual.
Detailed information about how the interface clock and frame synchronization signals are generated is
provided in Section 2.5.
2.2 Signal Descriptions
The signals used on the audio interface are listed in Table 1.
Table 1. McBSP Interface Signals
Pin I/O/Z Description
MCBSP_ I/O/Z Receive clock - supplies or receives a reference clock for the receiver; or supplies a reference clock to the sample
CLKR rate generator
MCBSP_ I Supplies the input clock of the sample rate generator
CLKS
MCBSP_ I/O/Z Transmit clock - supplies or receives a reference clock for the transmitter; or supplies a reference clock to the
CLKX sample rate generator
MCBSP_ I Received serial data
DR
MCBSP_ O/Z Transmitted serial data
DX
MCBSP_ I/O/Z Receive frame synchronization - control signal to synchronize the start of received data
FSR
MCBSP_ I/O/Z Transmit frame synchronization - control signal to synchronize the start of transmitted data
FSX
2.3 Pin Multiplexing
Extensive pin multiplexing is used to accommodate the largest number of peripheral functions in the
smallest possible package. Pin multiplexing is controlled using a combination of hardware configuration at
device reset and software programmable register settings. Refer to the device-specific data manual to
determine how pin multiplexing affects the McBSP.
2.4 Endianness Considerations
There are no endianness considerations for the McBSP.
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0
1
1
0
CLKXM
0
1
MCBSP_FSX pin
MCBSP_FSR pin
MCBSP_CLKR pin
MCBSP_CLKX pin
FSG
FSX_intCLKX_int
Frame selectionClock selection
CLKG
FSR_int
MCBSP_CLKS pin
Internal clock source (see Figure 5)
DXR to XSR
FSGM
0
1
FSR_int
CLKR_int
FSRP
1
00
1
FSRM
FSRM and GSYNC
FSRP
0
1
FSXP
FSXP
FSXM
FSXM
generator
Sample
rate
Receive
Transmit
DLB
CLKRM
CLKRM
CLKXM
CLKRP
CLKRP
CLKXP
CLKXP
DLB
www.ti.com Peripheral Architecture
2.5 Clock, Frames, and Data
The McBSP has several ways of selecting clocking and framing for both the receiver and transmitter.
Clocking and framing can be sent to both portions by the sample rate generator. Each portion can select
external clocking and/or framing independently. Figure 2 is a block diagram of the clock and frame
selection circuitry.
Figure 2. Clock and Frame Generation
2.5.1 Frame and Clock Operation
Receive and transmit frame sync pulses (FSR/X), and clocks (CLKR/X), can either be generated internally
by the sample rate generator (see Section 2.5.2) or be driven by an external source. The source of frame
sync and clock is selected by programming the mode bits, FS(R/X)M and CLK(R/X)M respectively, in the
pin control register (PCR). FSR is also affected by the GSYNC bit in the sample rate generator register
(SRGR), see Section 2.5.4.2 for details.
When MCBSP_FSR and MCBSP_FSX are inputs (FSXM = FSRM = 0), the McBSP detects them on the
internal falling edge of clock, CLKR_int and CLKX_int, respectively (see Figure 2). The receive data
arriving at the MCBSP_DR pin is also sampled on the falling edge of CLKR_int. These internal clock
signals are either derived from an external source via the CLK(R/X) pins or driven by the sample rate
generator clock (CLKG) internal to the McBSP.
When MCBSP_FSR and MCBSP_FSX are outputs driven by the sample rate generator, they are
generated (transition to their active state) on the rising edge of the internal clock, CLK(R/X)_int. Similarly,
data on MCBSP_DX is output on the rising edge of CLKX_int.
The FSRP, FSXP, CLKRP, and CLKXP bits in PCR configure the polarities of FSR, FSX, CLKR, and
CLKX. All frame sync signals (FSR_int and FSX_int) internal to the serial port are active high. If the serial
port is configured for external frame synchronization (MCBSP_FSR/MCBSP_FSX are inputs to the
McBSP) and FSRP = FSXP = 1, the external active (low) frame sync signals are inverted before being
sent to the receiver signal (FSR_int) and transmitter signal (FSX_int). Similarly, if internal synchronization
is selected (MCBSP_FSR/MCBSP_FSX are outputs and GSYNC = 0), the internal active (high) sync
signals are inverted if the polarity bit FS(R/X)P = 1, before being sent to the FS(R/X) pin.Figure 2 shows
this inversion using XOR gates.
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Disable time Propagation
delay
A1 A0 B7
CLKX_int
DX
DR
CLKR_int
B6B7
Data hold
Data setup
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
Peripheral Architecture www.ti.com
On the transmit side, the transmit clock polarity bit, CLKXP, sets the edge used to shift and clock out
transmit data. Data is always transmitted on the rising edge of CLKX_int (see Figure 3). If CLKXP = 1 and
external clocking is selected (CLKXM = 0 and CLKX is an input), the external falling-edge-triggered input
clock on CLKX is inverted to a rising-edge-triggered clock before being sent to the transmitter. If
CLKXP = 1 and internal clocking is selected (CLKXM = 1 and MCBSP_CLKX is an output pin), the internal
(rising-edge-triggered) clock, CLKX_int, is inverted before being sent out on the MCBSP_CLKX pin.
Similarly, the receiver can reliably sample data that is clocked (by the transmitter) with a rising-edge clock.
The receive clock polarity bit, CLKRP, sets the edge used to sample received data. The receive data is
always sampled on the falling edge of CLKR_int (see Figure 4). Therefore, if CLKRP = 1 and external
clocking is selected (CLKRM = 0 and CLKR is an input pin), the external rising-edge triggered input clock
on CLKR is inverted to a falling-edge clock before being sent to the receiver. If CLKRP = 1 and internal
clocking is selected (CLKRM = 1), the internal falling-edge-triggered clock is inverted to a rising edge
before being sent out on the MCBSP_CLKR pin.
In a system where the same clock (internal or external) is used to clock the receiver and transmitter,
CLKRP = CLKXP. The receiver uses the opposite edge as the transmitter to ensure valid setup and hold
times of data around this edge. Figure 4 shows how data clocked by an external serial device using a
rising-edge clock can be sampled by the McBSP receiver with the falling edge of the same clock.
Figure 3. Transmit Data Clocking
Figure 4. Receive Data Clocking
14 TMS320DM36x Multichannel Buffered Serial Port (McBSP) Interface SPRUFI3A–March 2009–Revised August 2009
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MCBSP_FSR
detection
Frame pulse
FWID
CLKG
FSG
Pulse
Frame
FPERCLKGDV
CLKSRG ÷ ÷
CLKSP
CLKS
McBSP
internal
clock
SCLKME, CLKSM
synchronization
and clock
GSYNC
0,0
0,1
1,0
1,1
CLKRP
MCBSP_CLKR pin
CLKXP
MCBSP_CLKX pin
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2.5.2 Sample Rate Generator Clocking and Framing
The sample rate generator is composed of a 3-stage clock divider that provides a programmable data
clock (CLKG) and framing signal (FSG), as shown in Figure 5. CLKG and FSG are McBSP internal signals
that can be programmed to drive receive and/or transmit clocking, CLK(R/X), and framing, FS(R/X). The
sample rate generator can be programmed to be driven by an internal clock source or an internal clock
derived from an external clock source.
The sample rate generator is not used when CLKX, FSX, CLKR, and FSR are driven by an external
source. Therefore, the GRST bit in the serial port control register (SPCR) does not need to be enabled
(GRST = 1) for this setup. The three stages of the sample rate generator circuit compute:
• Clock divide-down (CLKGDV): The number of input clocks per data bit clock
• Frame period (FPER): The frame period in data bit clocks
• Frame width (FWID): The width of an active frame pulse in data bit clocks
In addition, a frame pulse detection and clock synchronization module allows synchronization of the clock
divide-down with an incoming frame pulse. The operation of the sample rate generator during device reset
is described in Section 2.10.
Figure 5. Sample Rate Generator Block Diagram
15
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2.5.3 Data Clock Generation
When the receive/transmit clock mode is set to 1 (CLK(R/X)M = 1 in the pin control register (PCR)), the
data clocks (CLK(R/X)) are driven by the internal sample rate generator output clock, CLKG. You can
select for the receiver and transmitter from a variety of data bit clocks including:
• The input clock to the sample rate generator, which can be either the internal clock source or a
dedicated external clock source via the MCBSP_CLKX, MCBSP_CLKR, or MCBSP_CLKS pins. The
McBSP internal clock is the CPU/6 clock. See Section 2.5.3.1 for details on the source of the McBSP
internal clock.
• The input clock source (internal clock source or external clock
MCBSP_CLKX/MCBSP_CLKR/MCBSP_CLKS) to the sample rate generator can be divided-down by a
programmable value (CLKGDV bit in the sample rate generator register (SRGR)) to drive CLKG.
Regardless of the source to the sample rate generator, the rising edge of CLKSRG (see Figure 5)
generates CLKG and FSG.
2.5.3.1 Input Clock Source Mode: CLKSM and SCLKME
The sample rate generator input clock signal can be driven from one of four sources selectable with the
SCLKME bit in the pin control register (PCR) and the CLKSM bit in the sample rate generator register
(SRGR), see Table 2.
Table 2. Choosing an Input Clock for the Sample Rate Generator With the
SCLKME and CLKSM Bits
SCLKME Bit CLKSM Bit
in PCR in SRGR Input Clock for Sample Rate Generator
0 0 Signal on MCBSP_CLKS pin
0 1 McBSP internal input clock
1 0 Signal on MCBSP_CLKR pin
1 1 Signal on MCBSP_CLKX pin
2.5.3.2 Sample Rate Generator Data Bit Clock Rate: CLKGDV
The first divider stage generates the serial data bit clock from the input clock. This divider stage uses a
counter that is preloaded by the CLKGDV bit in the sample rate generator register (SRGR) and that
contains the divide ratio value. The output of this stage is the data bit clock that is output on the sample
rate generator output, CLKG, and that serves as the input for the second and third divider stages.
CLKG has a frequency equal to 1/(CLKGDV + 1) of the sample rate generator input clock. Thus, the
sample rate generator input clock frequency is divided by a value between 1 to 256. The CLKGDV value
chosen must result in a clock that meets the timing requirements/limitations specified in the device-specific
data manual.
When CLKGDV is an odd value or equal to 0, the CLKG duty cycle is 50%. Note that an odd CLKGDV
value means an even divide down of the source clock and an even CLKGDV value means an odd divide
down of the source clock. When CLKGDV is an even value (2p), the high state duration is p + 1 cycles
and the low state duration is p cycles. This is illustrated in Example 1. CLKGDV = 0,Example 2. CLKGDV
= 1, and Example 3. CLKGDV = 2.
In the following examples:
SIN = sample generator input clock period
fIN = sample generator input clock frequency
SG= CLKG period
fG= CLKG frequency
The following equation is given above: fG= fIN/(CLKGDV + 1); therefore, SG= (CLKGDV + 1) × SIN.
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Example 1.
CLKGDV = 0
SG= (CLKGDV + 1) × SIN = (0 + 1) × SIN = SIN
Pulse width high = SIN × (CLKGDV + 1)/2 = SIN × (0+ 1)/2 = 0.5 × SIN
Pulse width low = SIN × (CLKGDV + 1)/2 = SIN × (0+ 1)/2 = 0.5 × SIN
Example 2.
CLKGDV = 1
SG= (CLKGDV + 1) × SIN = (1 + 1) × SIN = 2 × SIN
Pulse width high = SIN × (CLKGDV + 1)/2 = SIN × (1 +1)/2 = SIN
Pulse width low = SIN × (CLKGDV + 1)/2 = SIN × (1+ 1)/2 = SIN
Example 3.
CLKGDV = 2
SG= (CLKGDV + 1) × SIN = (2 + 1) × SIN = 3 × SIN
Pulse width high = SIN × (CLKGDV/2 + 1) = SIN × (2/2 + 1) = 2 × SIN
Pulse width low = SIN × CLKGDV/2 = SIN × 2/2 = 1 × SIN
2.5.3.3 Bit Clock Polarity: CLKSP
The external clock (CLKS) is selected to drive the sample rate generator clock divider by selecting
CLKSM = 0 in the sample rate generator register (SRGR) and SCLKME = 0 in the pin control register
(PCR). In this case, the CLKSP bit in SRGR selects the edge of CLKS on which sample rate generator
data bit clock (CLKG) and frame sync signal (FSG) are generated. Since the rising edge of CLKSRG
generates CLKG and FSG, the rising edge of CLKS when CLKSP = 0 or the falling edge of CLKS when
CLKSP = 1 causes the transition on CLKG and FSG.
2.5.3.4 Bit Clock and Frame Synchronization
When the external clock (CLKS) is selected to drive the sample rate generator (CLKSM = 0 in SRGR and
SCLKME = 0 in PCR), the GSYNC bit in SRGR can be used to configure the timing of CLKG relative to
CLKS. GSYNC = 1 ensures that the McBSP and the external device to which it is communicating are
dividing down the CLKS with the same phase relationship. If GSYNC = 0, this feature is disabled and
CLKG runs freely and is not resynchronized. If GSYNC = 1, an inactive-to-active transition on FSR triggers
17
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FSR external (FSRP = 1)
FSG
CLKG (needs resync)
CLKG (no need to resync)
FSR external (FSRP = 0)
CLKS (CLKSP = 0)
CLKS (CLKSP = 1)
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a resynchronization of CLKG and the generation of FSG. CLKG always begins at a high state after
synchronization. Also, FSR is always detected at the same edge of CLKS that generates CLKG,
regardless of the length the FSR pulse. Although an external FSR is provided, FSG can still drive internal
receive frame synchronization when GSYNC = 1. When GSYNC = 1, FPER does not matter, because the
frame period is determined by the arrival of the external frame sync pulse.
Figure 6 and Figure 7 show this operation with various polarities of CLKS and FSR. These figures assume
that FWID is 0, for a FSG = 1 CLKG wide.
These figures show what happens to CLKG when it is initially in sync and GSYNC = 1, as well as when it
is not in sync with the frame synchronization and GSYNC = 1.
Figure 6. CLKG Synchronization and FSG Generation When GSYNC = 1 and CLKGDV = 1
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FSR external (FSRP = 1)
FSG
CLKG (needs resync)
CLKG (no need to resync)
FSR external (FSRP = 0)
CLKS (CLKSP = 0)
CLKS (CLKSP = 1)
(DLB)
From CPU or EDMA controllerMCBSP_DX
MCBSP_DR To CPU or
EDMA controller
DRRRJUST
DXR
RBR
XSR
RSR
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Figure 7. CLKG Synchronization and FSG Generation When GSYNC = 1 and CLKGDV = 3
When GSYNC = 1, the transmitter can operate synchronously with the receiver, provided that the following
conditions are met:
• FSX is programmed to be driven by the sample rate generator frame sync, FSG (FSGM = 1 in SRGR
and FSXM = 1 in PCR).
• The sample-rate generator clock should drive the transmit and receive bit clock (CLK(R/X)M = 1 in
SPCR). Therefore, the CLK(R/X) pin should not be driven by any other source.
2.5.3.5 Digital Loopback Mode: DLB
The DLB mode cannot be used when the McBSP is in clock stop mode (CLKSTP = 2h or 3h in the serial
port control register (SPCR)). Setting DLB = 1 in SPCR enables digital loopback mode. In DLB mode, DR,
FSR, and CLKR are internally connected through multiplexers to MCBSP_DX, FSX, and CLKX,
respectively, as shown in Figure 2 and Figure 8. DLB mode allows testing of serial port code without using
the external interface of the McBSP. MCBSP_CLKX and FSX must be enabled as outputs (CLKXM =
FSXM = 1) in DLB mode.
Figure 8. Digital Loopback Mode
2.5.3.6 Receive Clock Selection: DLB, CLKRM
Table 3 shows how the digital loopback bit (DLB) in the serial port control register (SPCR) and the
CLKRM bit in the pin control register (PCR) select the receiver clock. In digital loopback mode (DLB = 1),
the transmitter clock drives the receiver. CLKRM determines whether the MCBSP_CLKR pin is an input or
an output.
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Table 3. Receive Clock Selection
DLB Bit CLKRM Bit
in SPCR in PCR Source of Receive Clock CLKR Function
0 0 CLKR acts as an input driven by the external clock Input.
and inverted as determined by CLKRP before being
used.
0 1 The sample rate generator clock (CLKG) drives Output. CLKG inverted as determined by CLKRP
CLKR. before being driven out on CLKR.
1 0 CLKX_int drives the receive clock CLKR_int as High impedance.
selected and is inverted.
1 1 CLKX_int drives CLKR_int as selected and is Output. CLKR (same as CLKX) is inverted as
inverted. determined by CLKRP before being driven out.
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