Texas Instruments Serial Programming Adapter MSP430 User manual

MSP430 Memory Programming
User's Guide
Literature Number: SLAU265February 2009

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Contents
1 Overview of MSP430 Programming .............................................................................. 9
2 MSP430 Programming Via the Bootstrap Loader .......................................................... 112.1 Introduction .................................................................................................................. 112.2 Standard RESET and BSL Entry Sequence ............................................................................ 122.2.1 MSP430 20-Pin and 28-Pin Flash Devices With Shared JTAG Pins ....................................... 122.2.2 MSP430 Flash Devices With Dedicated JTAG Pins .......................................................... 132.3 UART Protocol .............................................................................................................. 13
3 ROM-Based Bootstrap Loader Protocol ....................................................................... 153.1 Synchronization Sequence ................................................................................................ 153.2 Commands .................................................................................................................. 153.2.1 Unprotected Commands ......................................................................................... 153.2.2 Password Protected Commands ................................................................................ 153.3 Programming Flow ......................................................................................................... 163.4 Data Frame ................................................................................................................. 173.4.1 Data-Stream Structure ............................................................................................ 173.4.2 Checksum .......................................................................................................... 183.4.3 Example Sequence ............................................................................................... 183.4.4 Commands – Detailed Description .............................................................................. 183.5 Loadable BSL ............................................................................................................... 223.6 Exiting the BSL ............................................................................................................. 233.7 Password Protection ....................................................................................................... 233.8 Code Protection Fuse ...................................................................................................... 233.9 BSL Internal Settings and Resources ................................................................................... 243.9.1 Chip Identification and BSL Version ............................................................................ 243.9.2 Vectors to Call the BSL Externally .............................................................................. 243.9.3 Initialization Status ................................................................................................ 243.9.4 Memory Allocation and Resources.............................................................................. 25
4 Flash-Based Bootstrap Loader Protocol ...................................................................... 274.1 BSL Data Packet ........................................................................................................... 274.2 Timer_A UART Peripheral Interface (PI) ................................................................................ 274.2.1 Wrapper ............................................................................................................ 274.2.2 Abbreviations ...................................................................................................... 274.2.3 Messages .......................................................................................................... 284.2.4 Interface Specific Commands ................................................................................... 284.3 BSL Core Command Structure ........................................................................................... 294.3.1 Abbreviations ...................................................................................................... 294.3.2 Command Descriptions ........................................................................................... 294.4 BSL Security ................................................................................................................ 304.5 BSL Core Responses ...................................................................................................... 314.5.1 Abbreviations ...................................................................................................... 31
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4.5.2 BSL Core Messages .............................................................................................. 314.5.3 BSL Version Number ............................................................................................. 324.5.4 Example Sequences .............................................................................................. 32
5 Bootstrap Loader Hardware ....................................................................................... 335.1 Hardware Description ...................................................................................................... 335.1.1 Power Supply ...................................................................................................... 335.1.2 Serial Interface ..................................................................................................... 345.1.3 Target Connector .................................................................................................. 355.1.4 Parts List ........................................................................................................... 36
6 Differences Between Devices and Bootstrap Loader Versions ....................................... 376.1 Special Consideration for the MSP430F543x BSL .................................................................... 376.2 Special Consideration for ROM BSL Version 1.10 .................................................................... 376.3 BSL Known issues ......................................................................................................... 38
7 Bootstrap Loader PCB Layout Suggestion .................................................................. 47
8 MSP430 Programming Via the JTAG Interface .............................................................. 518.1 Introduction .................................................................................................................. 518.2 Interface and Instructions ................................................................................................. 528.2.1 JTAG Interface Signals ........................................................................................... 528.2.2 JTAG Access Macros ............................................................................................. 548.2.3 Spy-Bi-Wire (SBW) Timing and Control ....................................................................... 578.2.4 JTAG Communication Instructions .............................................................................. 618.3 Memory Programming Control Sequences ............................................................................. 668.3.1 Start-Up ............................................................................................................. 668.3.2 General Device (CPU) Control Functions ...................................................................... 698.3.3 Accessing Non-Flash Memory Locations With JTAG ........................................................ 778.3.4 Programming the Flash Memory (Using the Onboard Flash Controller) ................................... 818.3.5 Erasing the Flash Memory (Using the Onboard Flash Controller) .......................................... 868.3.6 Reading From Flash Memory .................................................................................... 908.3.7 Verifying the Flash Memory ...................................................................................... 908.4 JTAG Access Protection .................................................................................................. 908.4.1 Burning the JTAG Fuse - Function Reference for 1xx/2xx/4xx Families ................................... 908.4.2 Programming the JTAG Lock Key - Function Reference for 5xx Family................................... 928.4.3 Testing for a Successfully Protected Device .................................................................. 938.5 JTAG Function Prototypes ................................................................................................ 938.5.1 Low-Level JTAG Functions ...................................................................................... 938.5.2 High-Level JTAG Routines ....................................................................................... 958.6 References .................................................................................................................. 998.7 Third-Party Support ........................................................................................................ 99
9 JTAG Programming Hardware and Software Implementation ....................................... 1019.1 Implementation History ................................................................................................... 1019.2 Implementation Overview ................................................................................................ 1019.3 Software Operation ....................................................................................................... 1029.4 Software Structure ........................................................................................................ 1039.5 Programmer Operation ................................................................................................... 1059.6 Hardware Setup ........................................................................................................... 1059.6.1 Host Controller ................................................................................................... 1059.6.2 Target Connection ............................................................................................... 105
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9.6.3 Host Controller/Programmer Power Supply .................................................................. 107
10 Internal MSP430 JTAG Implementation ...................................................................... 10910.1 TAP Controller State Machine .......................................................................................... 10910.2 MSP430 JTAG Restrictions (Non-Compliance With IEEE Std 1149.1) ............................................ 109
A Errata and Revision Information ............................................................................... 111
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List of Figures
2-1 Standard RESET Sequence .............................................................................................. 122-2 BSL Entry Sequence at Shared JTAG Pins ............................................................................ 122-3 BSL Entry Sequence at Dedicated JTAG Pins ......................................................................... 135-1 Bootstrap Loader Interface Schematic .................................................................................. 337-1 Universal BSL Interface PCB Layout, Top .............................................................................. 477-2 Universal BSL Interface PCB Layout, Bottom .......................................................................... 477-3 Universal BSL Interface Component Placement ....................................................................... 487-4 Universal BSL Interface Component Placement ....................................................................... 498-1 Spy-Bi-Wire Basic Concept ............................................................................................... 538-2 Timing Example for IR_SHIFT (0x83) Instruction ...................................................................... 548-3 Data Register I/O: DR_SHIFT16 (0x158B) (TDO Output Is 0x55AA) ............................................... 558-4 Address Register I/O: DR_SHIFT20 (0x12568) (TDO Output Is 0xA55AA) ........................................ 568-5 SetTCLK ..................................................................................................................... 568-6 ClrTCLK ..................................................................................................................... 568-7 Timing Diagram (Alternative Timing) .................................................................................... 578-8 SBW-to-JTAG Interface Diagram ........................................................................................ 588-9 Detailed SBW Timing Diagram ........................................................................................... 598-10 Synchronization of TDI/TCLK During Run-Test/Idle ................................................................... 608-11 JTAG Access Entry Sequences (for Devices Supporting SBW) ..................................................... 678-12 Fuse Check and TAP Controller Reset .................................................................................. 688-13 Accessing Flash Memory.................................................................................................. 848-14 Flash Access Code Binary Image Map .................................................................................. 858-15 Fuse Blow Timing .......................................................................................................... 929-1 Replicator Application Schematic ....................................................................................... 10610-1 TAP Controller State Machine .......................................................................................... 109
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List of Tables
3-1 Data Frame of BSL Commands .......................................................................................... 173-2 Recommendations for MSP430F149 ['F449] (T
A
= 25 °C, V
CC
= 3.0 V, f
max
= 6.7 MHz) .......................... 213-3 Recommendations for MSP430F2131 (T
A
= 25 °C, V
CC
= 3.0 V, f
max
= 6.7 MHz) .................................. 214-1 UART Protocol Interface .................................................................................................. 274-2 UART Error Messages..................................................................................................... 284-3 BSL Core Commands ..................................................................................................... 294-4 BSL Core Responses ...................................................................................................... 314-5 BSL Core Messages ....................................................................................................... 315-1 Serial-Port Signals and Pin Assignments ............................................................................... 345-2 RS-232 Levels .............................................................................................................. 345-3 Pin Assignment of Target Connector .................................................................................... 355-4 Universal BSL Interface Parts List ....................................................................................... 366-1 BSL Version 1.10 on F13x, F14x(1), F11x, and F11x1 ............................................................... 396-2 BSL Version 1.30 on F41x, F11x, and F11x1 .......................................................................... 406-3 BSL Version 1.40 on F12x ................................................................................................ 416-4 BSL Version 1.60 on F11x2, F12x2, F43x, F44x, FE42x, FW42x, FG43x, F415, F417 .......................... 426-5 BSL Version 1.61 on F16x, F161x, F42x0, F149 rev AA (and later) ................................................ 436-6 BSL Version 2.02 on F21xx, F22xx, F24x, F23x ....................................................................... 446-7 BSL Version 2.12/2.13 on FG46xx, F261x, F471xx .................................................................. 456-8 Flash BSL Software Version Codes ..................................................................................... 458-1 Standard 4-Wire JTAG Signals ........................................................................................... 528-2 JTAG Signal Implementation Overview ................................................................................. 538-3 JTAG Communication Macros ............................................................................................ 548-4 Memory Access Instructions .............................................................................................. 618-5 JTAG Control Signal Register for 1xx/2xx/4xx Families .............................................................. 638-6 JTAG Control Signal Register for 5xx Family .......................................................................... 648-7 Shared JTAG Device Pin Functions ..................................................................................... 668-8 Erase/Program Minimum TCLK Clock Cycles .......................................................................... 818-9 Flash Memory Parameters (f
FTG
= 450 kHz) ............................................................................ 888-10 MSP430 Device JTAG Interface (Shared Pins) ........................................................................ 908-11 MSP430 Device Dedicated JTAG Interface ............................................................................ 908-12 JTAG Features Across Device Families ................................................................................ 98A-1 Revision History ........................................................................................................... 111
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List of Tables8 SLAU265 – February 2009Submit Documentation Feedback

Chapter 1SLAU265 – February 2009
Overview of MSP430 Programming
Most MSP430 devices have nonvolatile flash memory that can store data or machine code for execution.This flash can be written using three primary methods: the MSP430 CPU/DMA, JTAG, or the bootstraploader (BSL).
Due to differences among the device families, flash programming via the CPU or DMA is excluded fromthis user's guide. Information regarding this can be found in the family-specific user's guide for the devicebeing used.
This user's guide focuses on the programming of MSP430 flash using JTAG and the BSL. The chapterthat describes JTAG programming can be applied to all supported MSP430 families. BSL programming onthe MSP430 can be broken into two primary methods: using the ROM-based BSL of the 1xx, 2xx, and 4xxfamilies, and using the flash-based BSL of the 5xx family. While each methods has its own protocol andthus separate chapter, the hardware and reset sequences are common across all devices. The chaptersthat describe reset and hardware can, therefore, be applied to all families of BSL.
The goal of this user's guide is to remain general so as to cover all flash-based MSP430 devices. Thespecific details of flash properties, timing, and other operating conditions can be found in thedevice-specific data sheets.
Associated code files and additional information are available from http://www.ti.com/lit/zip/slau265 .
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2.1 Introduction
Chapter 2SLAU265 – February 2009
MSP430 Programming Via the Bootstrap Loader
The MSP430 BSL enables users to communicate with embedded memory in the MSP430 microcontrollerduring the prototyping phase, final production, and in service. Both the programmable memory (flashmemory) and the data memory (RAM) can be modified as required. Do not confuse the bootstrap loaderwith programs found in some digital signal processors (DSPs) that automatically load program code (anddata) from external memory to the internal memory of the DSP. These programs are often referred to asbootstrap loaders as well.
The commonly used UART protocol with RS232 interface is supported, allowing flexible use of bothhardware and software.
To use the bootstrap loader, a specific BSL entry sequence must be applied to specific device pins. Anadded sequence of commands initiates the desired function. A boot-loading session can be exited bycontinuing operation at a defined user program address or by the reset condition.
If the device is secured by disabling JTAG, it is still possible to use the BSL. Access to the MSP430memory via the BSL is protected against misuse by a user-defined password.
This bootstrap loader provides a method to program the flash memory during MSP430 projectdevelopment and updates. It can be activated by a utility that sends commands via the UART protocol.The BSL enables the user to control the activity of the MSP430 and to exchange data using a personalcomputer or other device that supports a UART protocol.
To avoid accidental overwriting of the BSL code, this code is stored in a secure memory location, eitherROM or specially protected flash. To prevent unwanted source readout, any BSL command that directly orindirectly allows data reading is password protected.
To invoke the bootstrap loader, a BSL entry sequence must be applied to dedicated pins. After that, asynchronization character, followed by the data frame of a specific command, initiates the desiredfunction.
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2.2 Standard RESET and BSL Entry Sequence
2.2.1 MSP430 20-Pin and 28-Pin Flash Devices With Shared JTAG Pins
RST
DTR
/NMI
( )
TEST
( )RTS
User Program Starts
Bootstrap Loader Starts
RST
DTR
/NMI
( )
TEST
( )RTS
Standard RESET and BSL Entry Sequence www.ti.com
Applying an appropriate entry sequence on the RST/NMI and TEST pins forces the MSP430 to startprogram execution at the BSL RESET vector instead of at the RESET vector located at address FFFEh.
If the application interfaces with a computer UART, these two pins may be driven by the DTR and RTSsignals of the serial communication port (RS232) after passing level shifters. Detailed descriptions of thehardware and related considerations can be found in Chapter 5 . The normal user reset vector at FFFEh isused, if TEST is kept low while RST/NMI rises from low to high (standard method, see Figure 2-1 ).
Figure 2-1. Standard RESET Sequence
The BSL program execution starts when the TEST pin has received a minimum of two positive transitionsand if TEST is high while RST/NMI rises from low to high (BSL entry method, see Figure 2-2 ). Thislevel/transition triggering improves BSL startup reliability.
Figure 2-2. BSL Entry Sequence at Shared JTAG Pins
The TEST signal is normally used to switch the port pins P1.7 to P1.4 between their application functionand the JTAG function. If the second rising edge at the TEST pin is applied while RST/NMI is still low, theTEST signal is kept low internally (application mode).
The BSL is not started via the BSL RESET vector if:•There are fewer than two positive edges at the TEST pin while RST/NMI is low.•TEST is low when RST/NMI rises from low to high.•JTAG has control over the MSP430 resources.•Supply voltage, V
CC
, drops below its threshold, and a power-on reset (POR) is executed.•RST/NMI pin is configured for NMI functionality (NMI bit is set).
Note: The minimum timing for this sequence must be within the limits specified for thecorresponding pin in the data sheet.
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2.2.2 MSP430 Flash Devices With Dedicated JTAG Pins
RST
DTR
/NMI
( )
TEST
( )RTS Bootstrap Loader Starts
2.3 UART Protocol
www.ti.com UART Protocol
Devices with dedicated JTAG pins use the TCK pin instead of the TEST pin.
The BSL program execution starts whenever the TCK pin has received a minimum of two negativetransitions and TCK is low while RST/NMI rises from low to high (BSL entry method, see Figure 2-3 ). Thislevel/transition triggering improves BSL start-up reliability.
Figure 2-3. BSL Entry Sequence at Dedicated JTAG Pins
Note: The minimum timing for this sequence must be within the limits specified for thecorresponding pin in the data sheet.
The BSL is not started via the BSL RESET vector if•There are fewer than two negative edges at TCK pin while RST/NMI is low.•TCK is high if RST/NMI rises from low to high.•JTAG has control over the MSP430 resources.•Supply voltage, V
CC
, drops below its threshold, and a power-on reset (POR) is executed.•RST/NMI pin is configured for NMI functionality (NMI bit is set).
The UART protocol applied here is defined as:•Baud rate is fixed to 9600 baud in half duplex mode (one sender at a time).•Start bit, 8 data bits (LSB first), an even parity bit, 1 stop bit.•Handshake is performed by an acknowledge character.•Minimum time delay before sending new characters after characters have been received from theMSP430 BSL: 1.2 ms
Note: Applying baud rates other than 9600 baud at initialization results in communication problemsor violates the flash memory write timing specification. The flash memory may be extensivelystressed or may react with unreliable program/erase operations.
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3.1 Synchronization Sequence
3.2 Commands
3.2.1 Unprotected Commands
3.2.2 Password Protected Commands
Chapter 3SLAU265 – February 2009
ROM-Based Bootstrap Loader Protocol
Before sending any command to the BSL, a synchronization character (SYNC) with its value of 80h mustbe sent to the BSL. This character is necessary to calculate all the essential internal parameters, whichmaintain UART and flash memory program/erase timings. It provides the BSL system time reference.Once this is received, an acknowledge DATA_ACK = 90h is sent back by the BSL to confirm successfulreception.
This sequence must be done before every command that is sent to the BSL.
Note: The synchronization character is not part of the Data Frame described later.
Two categories of commands are available: commands that require a password and commands that donot require a password. The password protection safeguards every command that potentially allows director indirect data access.
•Receive password•Mass erase (erase entire flash memory, main as well as information memory)•Transmit BSL version (V1.50 or higher or in loadable BL_150S_14x.txt but not 2.x BSLs)•Change baud rate (V1.60 or V1.61 or V2.01+ or in loadable BL_150S_14x.txt)
•Receive data block to program flash memory, RAM, or peripherals•Transmit data block•Erase segment•Erase check (Present in V1.60 or higher or in loadable BL_150S_14x.txt)•Set Memory Offset (Present in V2.12 or higher)•Load program counter and start user program•Change baud rate
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3.3 Programming Flow
Programming Flow www.ti.com
The write access (RX data block command) to the flash memory/RAM or peripheral modules area isexecuted online. That means a data byte/word is processed immediately after receipt and the write cycleis finished before a following byte/word has completely arrived. Therefore, the entire write time isdetermined by the baud rate, and no buffering mechanism is necessary.
Data sections located below the flash memory area address are assumed to be loaded into the RAM orperipheral module area and, thus, no specific flash control bits are affected.
Note: When losing control over the UART protocol, either by line faults or by violating the dataframe conventions, the only way to recover is to rerun the BSL entry sequence to initiateanother BSL session.
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3.4 Data Frame
3.4.1 Data-Stream Structure
www.ti.com Data Frame
To ensure high data security during the data transmission, a data frame protocol called serial standardprotocol (SSP) is used. The BSL is considered the receiver in Table 3-1 .
•The first eight bytes (HDR through LH) are mandatory (xx represents dummy data).•Data bytes D1 to Dn are optional.•Two bytes (CKL and CKH) for checksum are mandatory.•Acknowledge done by the BSL is mandatory, except with the TX data block and TX BSL versioncommands.
Table 3-1. Data Frame of BSL Commands
(1) (2) (3) (4) (5) (6)
Received
BSL HDR CMD L1 L2 AL AH LL LH D1 D2 …Dn CKL CKH ACKCommand
RX data block 80 12 n n AL AH n–4 0 D1 D2 …Dn–4 CKL CKH ACKRX password 80 10 24 24 xx xx xx xx D1 D2 …D20 CKL CKH ACKErase segment 80 16 04 04 AL AH 02 A5 – – – – CKL CKH ACKErase main or info 80 16 04 04 AL AH 04 A5 – – – – CKL CKH ACKMass erase 80 18 04 04 xx xx 06 A5 – – – – CKL CKH ACKErase check 80 1C 04 04 AL AH LL LH – – – – CKL CKH ACKChange baud rate 80 20 04 04 D1 D2 D3 xx – – – – CKL CKH ACKSet mem offset 80 21 04 04 xx xx AL AH – – – – CKL CKH ACKLoad PC 80 1A 04 04 AL AH xx xx – – – – CKL CKH ACKTX data block 80 14 04 04 AL AH n 0 – – – – CKL CKH –BSL responds 80 xx n n D1 D2 ... ... …... …Dn CKL CKH –TX BSL version 80 1E 04 04 xx xx xx xx – – – – CKL CKH –BSL responds 80 xx 10 10 D1 D2 ... ... … … … D10 CKL CKH –
(1)
All numbers are bytes in hexadecimal notation.(2)
ACK is sent back by the BSL.(3)
The synchronization sequence is not part of the data frame.(4)
The erase check and TX BSL version commands are members of the standard command set in BSLs V1.50 or higher butexcluding 2.x BSLs.(5)
The change baud rate command is not a member of the standard command set (V1.60 or higher or in loadableBL_150S_14x.txt).
(6)
Abbreviations
HDR Header: Any value between 80h and 8Fh (normally 80h).
CMD Command identification
L1, L2 Number of bytes consisting of AL through DnRestrictions: L1 = L2, L1 < 255, L1 even
AL, AH Block start address or erase (check) address or jump address LO/HI byte
LL, LH Number of pure data bytes (250 max) or erase information LO/HI byte or block length of erase check (FFFFh max)
D1 …Dn Data bytes
CKL, CKH 16-bit checksum LO/HI byte
xx Can be any data
-- No character (data byte) received/transmitted
ACK The acknowledge character returned by the BSL. Can be either DATA_ACK = 90h: Frame was received correctly, command wasexecuted successfully, or DATA_NAK = A0h: Frame not valid (e.g., wrong checksum, L1 ≠L2), command is not defined, is notallowed, or was executed unsuccessfully.
nNumber of bytes consisting of AL through Dn
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3.4.2 Checksum
3.4.3 Example Sequence
3.4.4 Commands – Detailed Description
3.4.4.1 General
3.4.4.2 RX Data Block
Data Frame www.ti.com
The 16-bit (2 bytes) checksum is calculated over all received/transmitted bytes B1 ... Bn in the data frame,except the checksum bytes themselves, by XORing words (2 successive bytes) and inverting the result.
This means that B1 is always the HDR byte and Bn is the last data byte just before the CKL byte.
Formula
CHECKSUM = INV [ (B1 + 256 ×B2) XOR (B3 + 256 ×B4) XOR …XOR (Bn–1 + 256 ×Bn) ]or
CKL = INV [ B1 XOR B3 XOR …XOR Bn–1 ]CKH = INV [ B2 XOR B4 XOR …XOR Bn ]
The following example shows a request to read the memory of the MSP430 from location 0x0F00. Allvalues shown below are represented in hexadecimal format.
TO BSL: 80
(Synchronization character sent to the BSL)FROM BSL: 90
(Acknowledge from BSL)TO BSL: 80 14 04 04 F0 0F 0E 00 85 E0(Send Command to read memory from 0x0F00, length 0x000E)FROM BSL: 80 00 0E 0E F2 13 40 40 00 00 00 00 00 00 02 01 01 01 C0 A2(Returned values from BSL)
See Table 3-1 .
Besides the header byte HDR (80h) and the command identification CMD, the frame length bytes L1 andL2 (which must be equal) hold the number of bytes following L2, excluding the checksum bytes CKL andCKH.
Bytes AL, AH, LL, LH, D1...Dn are command-specific. However, the checksum bytes CKL (low byte) andCKH (high byte) are mandatory.
If the data frame has been received correctly and the command execution was successful, anacknowledge character DATA_ACK = 90h is sent back by the BSL. Incorrectly received data frames,unsuccessful operations, and commands that are locked or not defined are confirmed with a DATA_NAK =A0h.
Note: BSL versions lower than V1.30 support only byte-access operations. Therefore, theperipheral module addresses at 0100h to 01FFh cannot be accessed correctly, because theyare word-oriented. From version V1.30 and up, addresses 0000h to 00FFh are accessed inbyte mode; all others are accessed in word mode.
The receive data block command is used for any write access to the flash memory/RAM or peripheralmodule control registers at 0000h to 01FFh. It is password protected.
The 16-bit even-numbered block start address is defined in AL (low byte) and AH (high byte). The 16-biteven-numbered block length is defined in LL (low byte) and LH (high byte). Because pure data bytes arelimited to a maximum of 250, LH is always 0.
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3.4.4.3 RX Password
3.4.4.4 Mass Erase
3.4.4.5 Erase Segment
www.ti.com Data Frame
The following data bytes are succeeded by the checksum bytes CKL (low byte) and CKH (high byte). Ifthe receipt and programming of the appropriate data block was successful, an acknowledge characterDATA_ACK is sent back by the BSL. Otherwise, the BSL confirms with a DATA_NAK.
Note: BSL versions V1.40 and higher support online verification inside the MSP430 for addresses0200h to FFFFh, which reduces programming/verification time to 50%. Online verificationmeans that the data is immediately verified with the data that is written into the flash withouttransmitting it again. In case of an error, the loadable bootstrap loader BL_150S_14x.txtadditionally stores the first incorrectly written location address+3 into the error address bufferin the RAM at address 0200h (021Eh for F14x devices).
The receive password command is used to unlock the password-protected commands, which performreading, writing, or segment-erasing memory access. It is not password protected.
Neither start address nor block length information is necessary, because the 32-byte password is alwayslocated at addresses FFE0h to FFFFh. Data bytes D1 to D20h hold the password information starting withD1 at address FFE0h.
If the receipt and verification of the password is correct, a positive acknowledge DATA_ACK is sent backby the BSL, and the password-protected commands become unlocked. Otherwise the BSL confirms with aDATA_NAK.
Once the protected commands become unlocked, they remain unlocked until another BSL entry isinitiated.
The mass erase command erases the entire flash memory area (main memory plus information memory,see corresponding data sheet). It is not password protected.
All parameters shown in Table 3-1 are mandatory. After erasing, an acknowledge character DATA_ACK issent back by the BSL.
Mass erase initializes the password area to 32 times 0FFh.
Note: BSL versions V2.01 and higher support automatic clearing of the LOCKA bit protectinginformation flash memory. When the BSL is entered from a reset condition, LOCKA iscleared by the BSL in order to mass erase the flash, including information memory. Whenthe BSL is entered in-application, user software should take care that LOCKA is written as 1prior to initiating the BSL. Otherwise, information flash will not be erased during a BSL masserase.
The erase segment command erases specific flash memory segments. It is password protected.
The address bytes AL (low byte) and AH (high byte) select the appropriate segment. Any even-numberedaddress within the segment to be erased is valid. After segment erasing, an acknowledge characterDATA_ACK is sent back by the BSL (V1.40 or lower).
BSL versions V1.60 or higher perform a subsequent erase check of the corresponding segment andrespond with a DATA_NAK if the erasure was not successful. In this case, the first non-erased locationaddress + 1 is stored in the error address buffer in the RAM at address 0200h (021Eh for F14x devices).In this version, a problem occurs if only one of the information memory segments is erased. In this case,an error is reported, because an automatic erase check over the whole information memory is performed.As a solution, either erase the whole information memory or do a separate erase check after the erase,even if the erase reported an error.
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3.4.4.6 Erase Main or Info
3.4.4.7 Erase Check
3.4.4.8 Change Baud Rate
Data Frame www.ti.com
Erase segment 0 clears the password area and, therefore, the remaining password is 32 times 0FFh.
When applying LL = 0x04 and LH = 0xA5, a mass erasure of only the main memory is performed. Indeed,this command must be executed a minimum of 12 times to achieve a total erasure time of >200 ms. Nosubsequent erase check of the entire main memory is done. Use the erase check command additionally.Check the device data sheet for more information on the cumulative (mass) erase time that must be metand the number of erase cycles required.
The erase main or info command erases specific flash memory section. It is password protected.
The address bytes AL (low byte) and AH (high byte) select the appropriate section of flash (Main orINFO). Any even-numbered address within the section to be erased is valid.
The erase check command verifies the erasure of flash memory within a certain address range. It ispassword protected.
The 16-bit block start address is defined in AL (low byte) and AH (high byte). The 16-bit block length isdefined in LL (low byte) and LH (high byte). Both can be either even or odd numbered to allow oddboundary checking.
If the erase check of the appropriate data block was successful (all bytes contain 0FFh), an acknowledgecharacter DATA_ACK is sent back by the BSL. Otherwise, the BSL confirms with a DATA_NAK and thefirst non-erased location address + 1 is stored in the error address buffer at address 0200h (021Eh forF14x devices).
Note: This command is not a member of the standard command set. It is implemented in BSLversion V1.60 and higher or in the loadable bootstrap loader BL_150S_14x.txt.
The change baud rate command offers the capability of transmissions at higher baud rates than thedefault 9600 baud. With faster data transition, shorter programming cycles can be achieved, which isespecially important with large flash memory devices. This command is not password protected.
Three control bytes (D1 to D3) determine the selected baud rate. D1 and D2 set the processor frequency(f ≥f
min
), D3 indirectly sets the flash timing generator frequency (f
FTGmin
≤f
FTG
≤f
FTGmax
). In detail:
D1: F1xx: Basic clock module control register DCOCTL (DCO.2 to DCO.0)F2xx: Basic clock module control register DCOCTL (DCO.2 to DCO.0)F4xx: FLL+ system clock control register SCFI0 (D, FN_8 to FN_2)D2: F1xx: basic clock module control register BCSCTL1 (XT2Off, Rsel.2 to Rsel.0)F2xx: basic clock module control register BCSCTL1 (XT2Off, Rsel.2 to Rsel.0)F4xx: FLL+ system clock control register SCFI1 (N
DCO
)D3 0: 9600 Baud1: 19200 Baud2: 38400 Baud
After receiving the data frame, an acknowledge character DATA_ACK is sent back, and the BSL becomesprepared for the selected baud rate. It is recommended for the BSL communication program to waitapproximately 10 ms between baud rate alteration and succeeding data transmission to give the BSLclock system time for stabilization.
20 ROM-Based Bootstrap Loader Protocol SLAU265 – February 2009Submit Documentation Feedback