Texas Instruments TMS320C6000 DSP User manual

TMS320C6000 DSP
External Memory Interface (EMIF)
Reference Guide
Literature Number: SPRU266A
September 2003

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iiiRead This FirstSPRU266A
Preface
Read This First
About This Manual
This document describes the operation of the external memory interface
(EMIF) in the digital signal processors (DSPs) of the TMS320C6000DSP
family. For operation and registers unique in the TMS320C620x/C670x EMIF,
see Chapter 2. For operation and registers unique in the
TMS320C621x/C671x EMIF, see Chapter 3. For operation and registers
unique in the TMS320C64xEMIF, see Chapter 4.
Notational Conventions
This document uses the following conventions.
-Hexadecimal numbers are shown with the suffix h. For example, the
following number is 40 hexadecimal (decimal 64): 40h.
-Registers in this document are shown in figures and described in tables.
JEach register figure shows a rectangle divided into fields that represent
the fields of the register. Each field is labeled with its bit name, its
beginning and ending bit numbers above, and its read/write properties
below. A legend explains the notation used for the properties.
JReserved bits in a register figure designate a bit that is used for future
device expansion.
Related Documentation From Texas Instruments
The following documents describe the C6000devices and related support
tools. Copies of these documents are available on the Internet at www.ti.com.
Tip: Enter the literature number in the search box provided at www.ti.com.
TMS320C6000 CPU and Instruction Set Reference Guide (literature
number SPRU189) describes the TMS320C6000CPU architecture,
instruction set, pipeline, and interrupts for these digital signal processors.
TMS320C6000 DSP Peripherals Overview Reference Guide (literature
number SPRU190) describes the peripherals available on the
TMS320C6000DSPs.

Trademarks
iv SPRU266A
TMS320C6000 Technical Brief (literature number SPRU197) gives an
introduction to the TMS320C62xand TMS320C67xDSPs, develop-
ment tools, and third-party support.
TMS320C64x Technical Overview (SPRU395) gives an introduction to the
TMS320C64xDSP and discusses the application areas that are
enhanced by the TMS320C64x VelociTI.
TMS320C6000 Programmer’s Guide (literature number SPRU198)
describes ways to optimize C and assembly code for the
TMS320C6000DSPs and includes application program examples.
TMS320C6000 Code Composer Studio Tutorial (literature number
SPRU301) introduces the Code Composer Studiointegrated develop-
ment environment and software tools.
Code Composer Studio Application Programming Interface Reference
Guide (literature number SPRU321) describes the Code Composer
Studioapplication programming interface (API), which allows you to
program custom plug-ins for Code Composer.
TMS320C6x Peripheral Support Library Programmer’s Reference
(literature number SPRU273) describes the contents of the
TMS320C6000peripheral support library of functions and macros. It
lists functions and macros both by header file and alphabetically,
provides a complete description of each, and gives code examples to
show how they are used.
TMS320C6000 Chip Support Library API Reference Guide (literature
number SPRU401) describes a set of application programming interfaces
(APIs) used to configure and control the on-chip peripherals.
Trademarks
Code Composer Studio, C6000, C62x, C64x, C67x, TMS320C6000,
TMS320C62x, TMS320C64x, TMS320C67x, and VelociTI are trademarks of
Texas Instruments.
Related Documentation From Texas Instruments / Trademarks

Contents
vContentsSPRU266A
Contents
1 Overview 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Provides an overview and describes the common operation of the external memory interface
(EMIF) in the digital signal processors (DSPs) of the TMS320C6000 DSP family.
1.1 Overview 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Command-to-Command Turnaround Time 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 SDRAM Interface 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.1 SDRAM Initialization 1-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.2 Monitoring Page Boundaries 1-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.3 SDRAM Refresh Mode 1-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.4 SDRAM Deactivation (DCAB and DEAC) 1-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.5 SDRAM Activation (ACTV) 1-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 SBSRAM Interface 1-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 Asynchronous Interface 1-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5.1 Programmable ASRAM Parameters 1-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5.2 Asynchronous Reads 1-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5.3 Asynchronous Writes 1-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5.4 Ready Input 1-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5.5 C620x/C670x DSP Illegal Access to Asynchronous Memory 1-26. . . . . . . . . . . . .
1.6 Resetting the EMIF 1-27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6.1 Valid EMIF Clock During Reset 1-27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.7 Hold Interface 1-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.7.1 TMS320C62x/C67x EMIF Reset Considerations With the Hold Interface 1-29. . .
1.7.2 TMS320C64x EMIF Reset Considerations With the Hold Interface 1-29. . . . . . . .
1.8 Boundary Conditions When Accessing EMIF Registers 1-30. . . . . . . . . . . . . . . . . . . . . . . . .
1.9 Clock Output Enabling 1-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.10 Emulation Halt Operation 1-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.11 Power Down 1-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 TMS320C620x/C670x EMIF 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Describes the operation and registers of the EMIF in the TMS320C620x/C670x DSP.
2.1 Overview 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 EMIF Interface Signals 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.1 C6201/C6701 EMIF 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.2 C6202(B)/C6203(B)/C6204/C6205 EMIF 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Memory Width and Byte Alignment 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents
vi SPRU266A
2.4 SDRAM Interface 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.1 C620x/C670x Bootmode 2-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.2 Monitoring Page Boundaries 2-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.3 Address Shift 2-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.4 SDRAM Refresh Mode 2-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.5 Mode Register Set (MRS) 2-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.6 Timing Requirements 2-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.7 SDRAM Read 2-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.8 SDRAM Write 2-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 SBSRAM Interface 2-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.1 SBSRAM Read 2-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.2 SBSRAM Write 2-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6 ROM Access Modes 2-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.1 8-Bit ROM Mode 2-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.2 16-Bit ROM Mode 2-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7 Memory Request Priority 2-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8 EMIF Registers 2-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8.1 EMIF Global Control Register (GBLCTL) 2-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8.2 EMIF CE Space Control Registers (CECTL0−3) 2-27. . . . . . . . . . . . . . . . . . . . . . . .
2.8.3 EMIF SDRAM Control Register (SDCTL) 2-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8.4 EMIF SDRAM Timing Register (SDTIM) 2-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 TMS320C621x/C671x EMIF 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Describes the operation and registers of the EMIF in the TMS320C621x/C671x DSP.
3.1 Overview 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 EMIF Interface Signals 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Memory Width and Byte Alignment 3-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 SDRAM Interface 3-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.1 Monitoring Page Boundaries 3-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.2 Address Shift 3-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.3 SDRAM Refresh Mode 3-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.4 Mode Register Set (MRS) 3-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.5 Timing Requirements 3-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.6 SDRAM Read 3-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.7 SDRAM Write 3-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5 SBSRAM Interface 3-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.1 SBSRAM Read 3-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.2 SBSRAM Write 3-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6 Memory Request Priority 3-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7 EMIF Registers 3-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.1 EMIF Global Control Register (GBLCTL) 3-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.2 EMIF CE Space Control Registers (CECTL0−3) 3-27. . . . . . . . . . . . . . . . . . . . . . . .
3.7.3 EMIF SDRAM Control Register (SDCTL) 3-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.4 EMIF SDRAM Timing Register (SDTIM) 3-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.5 EMIF SDRAM Extension Register (SDEXT) 3-34. . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents
viiContentsSPRU266A
4 TMS320C64x EMIF 4-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Describes the operation and registers of the EMIF in the TMS320C64x DSP.
4.1 Overview 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 EMIF Interface Signals 4-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 Memory Width and Byte Alignment 4-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4 SDRAM Interface 4-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.1 Monitoring Page Boundaries 4-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.2 Address Shift 4-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.3 SDRAM Refresh Mode 4-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.4 SDRAM Self-Refresh Mode 4-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.5 Mode Register Set (MRS) 4-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.6 Timing Requirements 4-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.7 SDRAM Read 4-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.8 SDRAM Write 4-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5 Programmable Synchronous Interface 4-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.1 SBSRAM Interface 4-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.2 Zero Bus Turnaround (ZBT) SRAM Interface 4-28. . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.3 Synchronous FIFO Interface 4-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6 Peripheral Device Transfer (PDT) 4-36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6.1 PDT Write 4-38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6.2 PDT Read 4-47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6.3 PDT Transfers with Multiple FIFOs on the Same Bus 4-51. . . . . . . . . . . . . . . . . . . .
4.6.4 PDT Transfers: Bus Width and DMA Considerations 4-55. . . . . . . . . . . . . . . . . . . .
4.7 Memory Request Priority 4-56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8 EMIF Registers 4-57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8.1 EMIF Global Control Register (GBLCTL) 4-57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8.2 EMIF CE Space Control Registers (CECTL0−3) 4-60. . . . . . . . . . . . . . . . . . . . . . . .
4.8.3 EMIF CE Space Secondary Control Registers (CESEC0−3) 4-63. . . . . . . . . . . . . .
4.8.4 EMIF SDRAM Control Register (SDCTL) 4-65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8.5 EMIF SDRAM Timing Register (SDTIM) 4-67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8.6 EMIF SDRAM Extension Register (SDEXT) 4-69. . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8.7 EMIF Peripheral Device Transfer Control Register (PDTCTL) 4-71. . . . . . . . . . . .
A Revision History A-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lists the changes made since the previous version of this document.

Figures
viii SPRU266A
Figures
1−1 SDRAM Refresh Timing Diagram 1-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−2 TMS320C6000 SDRAM Deactivate All Banks (DCAB) Command Timing Diagram 1-10. . . .
1−3 TMS320C621x/C671x and TMS320C64x SDRAM Deactivate Single Bank (DEAC)
Command Timing Diagram 1-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−4 TMS320C6000 SDRAM Activate (ACTV) Command Before an SDRAM Write
Timing Diagram 1-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−5 EMIF to 32-bit SRAM Interface Block Diagram 1-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−6 EMIF to 8-Bit ROM Interface Block Diagram 1-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−7 EMIF to 16-Bit ROM Interface Block Diagram 1-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−8 EMIF to 32-Bit ROM Interface Block Diagram 1-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−9 Asynchronous Read Timing Diagram 1-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−10 Asynchronous Write Timing Diagram 1-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−11 TMS320C620x/C670x EMIF Ready Operation Timing Diagram 1-24. . . . . . . . . . . . . . . . . . . .
1−12 TMS320C621x/C671x EMIF Ready Operation Timing Diagram 1-25. . . . . . . . . . . . . . . . . . . .
1−13 TMS320C64x EMIF Ready Operation Timing Diagram 1-26. . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−14 TMS320C64x EMIF Clock Block Diagram 1-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−1 TMS320C620x/C670x DSP Block Diagram 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−2 TMS320C6201/C6701 EMIF Interface Signals 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−3 TMS320C6202/C6203/C6204/C6205 EMIF Interface Signals 2-4. . . . . . . . . . . . . . . . . . . . . . .
2−4 EMIF to 16M-Bit SDRAM Interface Block Diagram 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−5 EMIF to 64M-Bit SDRAM Interface Block Diagram 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−6 Logical Address-to-Page Register Mapping 2-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−7 Mode Register Value 2-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−8 SDRAM Mode Register Set: MRS Command Timing Diagram 2-14. . . . . . . . . . . . . . . . . . . . .
2−9 SDRAM Read Timing Diagram 2-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−10 SDRAM Three-Word Write Timing Diagram 2-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−11 EMIF to SBSRAM Interface Block Diagram 2-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−12 SBSRAM Four-Word Read Timing Diagram 2-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−13 SBSRAM Four-Word Write Timing Diagram 2-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−14 EMIF Global Control Register (GBLCTL) (C6201/C6701 DSP) 2-24. . . . . . . . . . . . . . . . . . . . .
2−15 EMIF Global Control Register (GBLCTL) (C6202/C6203/C6204/C6205 DSP) 2-24. . . . . . . .
2−16 EMIF CE Space Control Register (CECTL) 2-27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−17 EMIF SDRAM Control Register (SDCTL) 2-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−18 EMIF SDRAM Timing Register (SDTIM) 2-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−1 TMS320C621x/C671x DSP Block Diagram 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−2 TMS320C621x/C671x EMIF Interface Signals 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−3 Byte Alignment by Endianness 3-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figures
ixFiguresSPRU266A
3−4 TMS320C621x/C671x EMIF to 16-bit SRAM (Big Endian) Block Diagram 3-8. . . . . . . . . . . . .
3−5 EMIF to 16M-Bit SDRAM Interface Block Diagram 3-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−6 Logical Address-to-Page Register Mapping for 32-Bit Logical Address 3-12. . . . . . . . . . . . . .
3−7 Mode Register Value 3-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−8 SDRAM Mode Register Set: MRS Command Timing Diagram 3-16. . . . . . . . . . . . . . . . . . . . .
3−9 SDRAM Three-Word Read Timing Diagram 3-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−10 SDRAM Three-Word Write Timing Diagram 3-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−11 EMIF to SBSRAM Interface Block Diagram 3-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−12 SBSRAM Six-Word Read Timing Diagram 3-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−13 SBSRAM Six-Word Write Timing Diagram 3-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−14 EMIF Global Control Register (GBLCTL) 3-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−15 EMIF CE Space Control Register (CECTL) 3-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−16 EMIF SDRAM Control Register (SDCTL) 3-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−17 EMIF SDRAM Timing Register (SDTIM) 3-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−18 EMIF SDRAM Extension Register (SDEXT) 3-34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−1 TMS320C64x DSP Block Diagram 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−2 TMS320C64x EMIFA and EMIFB Interface Signals 4-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−3 Byte Alignment by Endianness 4-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−4 EMIFA to 64M-Bit SDRAM Interface Block Diagram 4-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−5 Logical Address-to-Page Register Mapping for EMIFA 4-13. . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−6 Logical Address-to-Page Register Mapping for EMIFB 4-14. . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−7 Mode Register Value† 4-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−8 SDRAM Mode Register Set: MRS Command Timing Diagram 4-19. . . . . . . . . . . . . . . . . . . . .
4−9 SDRAM Read Timing Diagram 4-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−10 SDRAM Write Timing Diagram 4-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−11 EMIF to SBSRAM Interface Block Diagram 4-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−12 SBSRAM Six-Element Read Timing Diagram 4-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−13 SBSRAM Six-Element Write Timing Diagram 4-27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−14 EMIF to Zero Bus Turnaround (ZBT) SRAM Interface Block Diagram 4-28. . . . . . . . . . . . . . .
4−15 Zero Bus Turnaround (ZBT) SRAM Six-Element Write Timing Diagram 4-29. . . . . . . . . . . . . .
4−16 Read and Write Synchronous FIFO Interface With Glue Block Diagram 4-30. . . . . . . . . . . . .
4−17 Glueless Synchronous FIFO Read Interface in CE3 Space Block Diagram 4-31. . . . . . . . . . .
4−18 Glueless Synchronous FIFO Write Interface Block Diagram 4-31. . . . . . . . . . . . . . . . . . . . . . .
4−19 Standard Synchronous FIFO Read Timing Diagram (CE0, CE1, or CE2) 4-32. . . . . . . . . . . .
4−20 Standard Synchronous FIFO Read Timing Diagram (CE3 only) 4-33. . . . . . . . . . . . . . . . . . . .
4−21 Standard Synchronous FIFO Write Timing Diagram 4-34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−22 First Word Fall Through (FWFT) Synchronous FIFO Read Timing Diagram 4-35. . . . . . . . . .
4−23 PDT Write Transaction Timing Diagram 4-39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−24 Case A: Glueless PDT Write Interface From Synchronous FIFO Block Diagram 4-41. . . . . .
4−25 Case A: Glueless PDT Write Transfer From Synchronous FIFO Timing Diagram 4-42. . . . .
4−26 Case B: PDT Write Interface From FWFT FIFO With Glue Block Diagram 4-43. . . . . . . . . . .
4−27 Case B: PDT Write Transfer From FWFT FIFO With Glue Timing Diagram 4-44. . . . . . . . . . .
4−28 Case C: PDT Write Interface From Standard FIFO With Glue Block Diagram 4-45. . . . . . . . .
4−29 Case C: PDT Write Transfer From Standard FIFO With Glue Timing Diagram 4-46. . . . . . . .

Figures
xSPRU266A
4−30 PDT Read Transaction (CAS Latency is 3) Timing Diagram 4-48. . . . . . . . . . . . . . . . . . . . . . .
4−31 Case D: Glueless PDT Read Interface to Synchronous FIFO Block Diagram 4-49. . . . . . . . .
4−32 Case D: Glueless PDT Read Transfer to Synchronous FIFO Timing Diagram 4-50. . . . . . . .
4−33 Case E: PDT Read and Write Interface With Multiple FIFOs Block Diagram 4-52. . . . . . . . . .
4−34 Case E: PDT Write Transfer with Read and Write FIFOs in the System
(FWFT FIFO) Timing Diagram 4-53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−35 Case E: PDT Read Transfer with Read and Write FIFOs in the System
(FWFT FIFO) Timing Diagram 4-53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−36 EMIF Global Control Register (GBLCTL) 4-57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−37 EMIF CE Space Control Register (CECTL) 4-61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−38 EMIF CE Space Secondary Control Register (CESEC) 4-63. . . . . . . . . . . . . . . . . . . . . . . . . . .
4−39 EMIF SDRAM Control Register (SDCTL) 4-65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−40 EMIF SDRAM Timing Register (SDTIM) 4-68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−41 EMIF SDRAM Extension Register (SDEXT) 4-69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−42 EMIF Peripheral Device Transfer Control Register (PDTCTL) 4-71. . . . . . . . . . . . . . . . . . . . . .

Tables
xiTablesSPRU266A
Tables
1−1 Differences Between the C62x/C67x and C64x EMIF 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−2 TMS320C6000 EMIF SDRAM Commands 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−3 Truth Table for SDRAM Commands 1-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−4 TMS320C6000 SDRAM Signal Descriptions 1-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−5 TMS320C6000 SDRAM Interface Summary 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−6 TMS320C6000 SBSRAM Operating Speeds 1-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−7 TMS320C6000 SBSRAM Signal Descriptions 1-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−8 TMS320C6000 SBSRAM Interface Summary 1-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−9 Asynchronous Interface Signal Descriptions 1-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−10 TMS320C6000 ASRAM Interface Summary 1-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−11 EMIF Output Clock (ECLKOUTn) Operation 1-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−1 TMS320C620x/C670x EMIF Interface Signal Descriptions 2-5. . . . . . . . . . . . . . . . . . . . . . . . . .
2−2 Addressable Memory Ranges 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−3 TMS320C620x/C670x DSP Compatible SDRAM 2-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−4 Example C620x/C670x SDRAM Interface with Unused SDRAM Address Pins 2-9. . . . . . . . .
2−5 Byte Address-to-EA Mapping for SDRAM RAS and CAS 2-11. . . . . . . . . . . . . . . . . . . . . . . . . .
2−6 Implied SDRAM Configuration by MRS Command 2-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−7 SDRAM Timing Parameters 2-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−8 Byte Address to EA Mapping for Asynchronous Memory Widths 2-20. . . . . . . . . . . . . . . . . . .
2−9 EMIF Prioritization of Memory Requests 2-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−10 EMIF Registers for C620x/C670x DSP 2-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−11 EMIF Global Control Register (GBLCTL) Field Descriptions 2-25. . . . . . . . . . . . . . . . . . . . . . .
2−12 EMIF CE Space Control Register (CECTL) Field Descriptions 2-28. . . . . . . . . . . . . . . . . . . . .
2−13 EMIF SDRAM Control Register (SDCTL) Field Descriptions 2-30. . . . . . . . . . . . . . . . . . . . . . .
2−14 EMIF SDRAM Timing Register (SDTIM) Field Descriptions 2-31. . . . . . . . . . . . . . . . . . . . . . .
3−1 TMS320C621x/C671x EMIF Interface Signal Descriptions 3-5. . . . . . . . . . . . . . . . . . . . . . . . . .
3−2 Addressable Memory Ranges 3-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−3 TMS320C621x/C671x DSP Compatible SDRAM 3-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−4 Byte Address-to-EA Mapping for 8-, 16-, and 32-Bit Interface 3-14. . . . . . . . . . . . . . . . . . . . . .
3−5 Implied SDRAM Configuration by MRS Command 3-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−6 SDRAM Timing Parameters 3-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−7 Recommended Values for Command-to-Command Parameters 3-18. . . . . . . . . . . . . . . . . . . .
3−8 SBSRAM in Linear Burst Mode 3-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−9 EMIF Prioritization of Memory Requests 3-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Tables
xii SPRU266A
3−10 EMIF Registers for C621x/C671x DSP 3-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−11 EMIF Global Control Register (GBLCTL) Field Descriptions 3-26. . . . . . . . . . . . . . . . . . . . . . .
3−12 EMIF CE Space Control Register (CECTL) Field Descriptions 3-28. . . . . . . . . . . . . . . . . . . . .
3−13 EMIF SDRAM Control Register (SDCTL) Field Descriptions 3-30. . . . . . . . . . . . . . . . . . . . . . .
3−14 EMIF SDRAM Timing Register (SDTIM) Field Descriptions 3-33. . . . . . . . . . . . . . . . . . . . . . .
3−15 EMIF SDRAM Extension Register (SDEXT) Field Descriptions 3-34. . . . . . . . . . . . . . . . . . . . .
4−1 TMS320C64x EMIFA Bus Widths 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−2 TMS320C64x EMIF Interface Signal Descriptions 4-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−3 Addressable Memory Ranges 4-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−4 TMS320C64x DSP Compatible SDRAM 4-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−5 Byte Address-to-EA Mapping for 8-, 16-, 32-, 64-Bit Interface 4-16. . . . . . . . . . . . . . . . . . . . . .
4−6 Implied SDRAM Configuration by MRS Command 4-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−7 SDRAM Timing Parameters 4-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−8 Recommended Values for Command-to-Command Parameters 4-21. . . . . . . . . . . . . . . . . . . .
4−9 Programmable Synchronous Pins 4-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−10 Peripheral Device Transfer (PDT) Signal Description 4-37. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−11 Supported Set Ups for PDT Write Transfers 4-40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−12 Limitations on the Number of Additional Peripherals for a PDT Transfer 4-54. . . . . . . . . . . . .
4−13 DMA Configuration for a PDT Transfer 4-55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−14 EMIF Prioritization of Memory Requests 4-56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−15 EMIF Registers for C64x DSP 4-57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−16 EMIF Global Control Register (GBLCTL) Field Descriptions 4-58. . . . . . . . . . . . . . . . . . . . . . .
4−17 EMIF CE Space Control Register (CECTL) Field Descriptions 4-61. . . . . . . . . . . . . . . . . . . . .
4−18 EMIF CE Space Secondary Control Register (CESEC) Field Descriptions 4-64. . . . . . . . . . .
4−19 EMIF SDRAM Control Register (SDCTL) Field Descriptions 4-65. . . . . . . . . . . . . . . . . . . . . . .
4−20 EMIF SDRAM Timing Register (SDTIM) Field Descriptions 4-68. . . . . . . . . . . . . . . . . . . . . . .
4−21 EMIF SDRAM Extension Register (SDEXT) Field Descriptions 4-69. . . . . . . . . . . . . . . . . . . . .
4−22 EMIF Peripheral Device Transfer Control Register (PDTCTL) Field Descriptions 4-71. . . . . .
A−1 Document Revision History A-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-1OverviewSPRU266A
Overview
This chapter provides an overview and describes the common operation of the
external memory interface (EMIF) in the digital signal processors (DSPs) of
the TMS320C6000DSP family. For operation and registers unique in the
TMS320C620x/C670x EMIF, see Chapter 2. For operation and registers
unique in the TMS320C621x/C671x EMIF, see Chapter 3. For operation and
registers unique in the TMS320C64xEMIF, see Chapter 4.
Topic Page
1.1 Overview 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Command-to-Command Turnaround Time 1-3. . . . . . . . . . . . . . . . . . . . . . .
1.3 SDRAM Interface 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 SBSRAM Interface 1-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 Asynchronous Interface 1-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6 Resetting the EMIF 1-27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.7 Hold Interface 1-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.8 Boundary Conditions When Accessing EMIF Registers 1-30. . . . . . . .
1.9 Clock Output Enabling 1-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.10 Emulation Halt Operation 1-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.11 Power Down 1-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 1

Overview
Overview1-2 SPRU266A
1.1 Overview
The external memory interfaces (EMIFs) of all C6000devices support a
glueless interface to a variety of external devices, including:
-Pipelined synchronous-burst SRAM (SBSRAM)
-Synchronous DRAM (SDRAM)
-Asynchronous devices, including SRAM, ROM, and FIFOs
-An external shared-memory device
Table 1−1 summarizes the differences between the C6000 EMIFs.
Table 1−1. Differences Between the C62x/C67x and C64x EMIF
C62x/C67x EMIF C64x EMIF‡
EMIFA EMIFB
Feature C6201/C6701
Other
C620x/C670x C621x/C671x†
C6416/15/14/12,
DM642
C6411,
DM640/641 C6416/15/14
Bus width 32-bit 32-bit 32-bit†64-bit 32-bit 16-bit
Number of
memory
spaces
4 4 4 4 4 4
Addressable
space
(Mbytes)
52 52 512†1024 512 256
Synchronous
clocking
CPU clock
and/or 1/2×
CPU clock
1/2×CPU
clock
Independent
ECLKIN
Independent
ECLKIN, 1/4×
CPU clock or
1/6×CPU
clock
Independent
ECLKIN,
1/4×CPU
clock or 1/6×
CPU clock
Independent
ECLKIN,
1/4×CPU
clock or 1/6×
CPU clock
Width support 32 bit;
8-/16-bit ROM
32 bit;
8-/16-bit ROM
8-/16-bit,
32-bit†
8-, 16-, 32-,
or 64-bit
8-, 16-, or
32-bit
8-bit or
16-bit
Supported
memory type
at CE1
Asynchronous
memory
Asynchronous
memory
All types All types All types All types
Control
signals
Separate Muxed
synchronous
signals
Muxed all
control
signals
Muxed all
control
signals
Muxed all
control
signals
Muxed all
control
signals
†On the C6712/C6712C DSP, the EMIF is only 16-bits wide. Addressable space is 256M bytes. It supports memory widths
of 8 bits and 16 bits.
‡On the C64x DSP, the EMIFA bus width is device specific, either 64-bit or 32-bit wide. EMIFB has a 16-bit bus width.

Command-to-Command Turnaround Time
1-3OverviewSPRU266A
Table 1−1. Differences Between the C62x/C67x and C64x EMIF (Continued)
C62x/C67x EMIF C64x EMIF‡
Feature
EMIFBEMIFA
C621x/C671x†
Other
C620x/C670x
C6201/C6701Feature C6416/15/14
C6411,
DM640/641
C6416/15/14/12,
DM642
C621x/C671x†
Other
C620x/C670x
C6201/C6701Feature
Synchronous
memory in
system
Both SDRAM
and SBSRAM
Either
SDRAM or
SBSRAM
Both SDRAM
and SBSRAM
All synchro-
nous
All synchro-
nous
All synchro-
nous
Additional
registers
— — SDEXT SDEXT
CESEC
SDEXT
CESEC
SDEXT
CESEC
PDT support No No No Yes Yes Yes
ROM/Flash n n n n n n
Asynchronous
memory I/O
n n n n n n
Pipeline
SBSRAM
n n n n n n
Flow thru
SBSRAM
n n n
ZBT SRAM n n n
Standard
Synchronous
FIFO
n n n
FWFT FIFO n n n
†On the C6712/C6712C DSP, the EMIF is only 16-bits wide. Addressable space is 256M bytes. It supports memory widths
of 8 bits and 16 bits.
‡On the C64x DSP, the EMIFA bus width is device specific, either 64-bit or 32-bit wide. EMIFB has a 16-bit bus width.
1.2 Command-to-Command Turnaround Time
The C6000 EMIF has a one cycle command-to-command turnaround time. At
least 1 data dead cycle is always included between commands so that read
data and write data are never driven in the same cycle.
Overview / Command-to-Command Turnaround Time

SDRAM Interface
Overview1-4 SPRU266A
1.3 SDRAM Interface
The C6000 EMIF supports the SDRAM commands shown in Table 1−2.
Table 1−3 shows the signal truth table for the SDRAM commands. The 16-bit
EMIF, 32-bit EMIF, and 64-bit EMIF table entries refer to the total bus width of
the EMIF and not the size of the transfer. Table 1−4 summarizes the pin
connection and related signals specific to SDRAM operation. Table 1−5
summarizes the similarities and differences on the C6000 SDRAM interface.
Table 1−2. TMS320C6000 EMIF SDRAM Commands
Command Function
ACTV Activates the selected bank and selects the row
DCAB Deactivates (also known as PRECHARGE) all banks
DEAC†Deactivates a single bank
MRS Mode register set, configures SDRAM mode register
READ Inputs the starting column address and begins the read operation
REFR Autorefresh cycle with internal address
SLFREFR‡Self-refresh mode
WRT Inputs the starting column address and begins the write operation
†TMS320C621x/C671x/C64x DSP only.
‡TMS320C64x DSP only.

SDRAM Interface
1-5OverviewSPRU266A
Table 1−3. Truth Table for SDRAM Commands
SDRAM: CKE CS RAS CAS W A[19:16] A[15:11] A10 A[9:0]
16-bit
EMIF:†SDCKE CE SDRAS SDCAS SDWE EA[20:17]‡EA[16:12] EA11 EA[10:1]
32-bit
EMIF:†SDCKE§CE SDRAS SDCAS SDWE EA[21:18]¶EA[17:13] EA12#EA[11:2]k
64-bit
EMIF:†SDCKE CE SDRAS SDCAS SDWE EA[22:19]‡EA[18:14] EA13 EA[12:3]||
ACTV H L L H H 0001b
or
0000b¶
Bank/Row Row Row
READ H L H L H X Bank/
Column
L Column
WRT H L H L L X Bank/
Column
L Column
MRS H L L L L L L/Mode Mode Mode
DCAB H L L H L X X H X
DEAC H L L H L X Bank/X L X
REFR H L L L H X X X X
SLFREFR L L L L H X X X X
Legend: Bank = Bank Address; Row = Row Address; Column = Column Address; L = Low = 0b; H = High = 1b; X = Previous
value; Mode = Mode Select
†16-bit EMIF includes C64x EMIFB; 32-bit EMIF includes all C62x/C67x EMIF, both 32-bit and 16-bit interfaces; 64-bit EMIF
includes C64x EMIFA, both 64-bit and 32-bit interfaces.
‡For C64x DSP, upper address bits are used during ACTV to indicate non-PDT (0001b) vs. PDT (0000b) access. During all other
accesses, address bits indicated with X hold previous value.
§SDCKE does not exist on C62x/C67x DSP.
¶For C62x/C67x DSP, upper address bits are reserved for future use. Undefined.
#SDA10 is used on C620x/C670x DSP. EA12 is used on C621x/C671x DSP.
|| EMIF address numbering for the C64x 32-bit EMIFA begins with EA3 to maintain signal name compatibility with the C64x 64-bit
EMIFA.
kEMIF address numbering for the C6712/C6712C 16-bit EMIF begins with EA2 to maintain signal name compatibility with the
C62x/C67x 32-bit EMIF.

SDRAM Interface
Overview1-6 SPRU266A
Table 1−4. TMS320C6000 SDRAM Signal Descriptions
EMIF Signal
SDRAM
Signal SDRAM Function
BEx DQMx Data/output mask. DQM is an input/output buffer control signal. When high, it
disables writes and places outputs in the high impedance state during reads.
DQM has a 2-CLK-cycle latency on reads and a 0-CLK-cycle latency on writes.
DQM pins serve as byte strobes and are connected to BE outputs.
CE3, CE2,
CE1‡, or CE0
CS Chip select and command enable. CS must be active (low) for a command to be
clocked into the SDRAM. CE1 does not support SDRAM on C620x/C670x DSP.
CLKOUT2 CLK SDRAM clock input. Runs at 1/2 the CPU clock rate. Used for synchronous
memory interface on the C6202(B)/C6203(B)/C6204/C6205 DSP.
ECLKOUT CLK SDRAM clock input. Used for synchronous memory interface on the
C621x/C671x/C64x DSP. For C6713 DSP, runs at either ECLKIN or SYSCLK3
(programmable divide-down clock with PLL output as reference clock), configur-
able using EKSRC bit in DEVCFG. For C621x/C671x DSP, runs at ECLKIN
rate. For C64x DSP, ECLKOUT1 is used. ECLKOUT1 runs at EMIF input clock
rate (ECLKIN, CPU/4 clock, or CPU/6 clock).
SDA10†A10 Address line A10/autoprecharge disable. Serves as a row address bit during
ACTV commands and also disables the autoprecharging function of SDRAM.
(C620x/C670x DSP only)
SDCAS CAS Column address strobe and command Input. Latched by the rising edge of CLK
to determine current operation. Valid only if CS is active (low) during that clock
edge.
SDCKE§CKE CKE clock enable. For C64x DSP, SDCKE is connected to CKE to minimize
SDRAM power consumption when self-refresh mode is enabled. For
C62x/C67x SDRAM interface, CKE is tied high (on the SDRAM device) since
the Self Refresh command is not supported.
SDCLK CLK SDRAM clock input. Runs at 1/2 the CPU clock rate. Used for SDRAM interface
on C6201/C6701 DSP.
SDRAS RAS Row address strobe and command input. Latched by the rising edge of CLK to
determine current operation. Valid only if CS is active (low) during that clock edge.
SDWE WE Write strobe and command input. Latched by the rising edge of CLK to determine
current operation. Valid only if CS is active (low) during that clock edge.
†SDA10 is used on C620x/C670x DSP. EA12 is used on C621x/C671x DSP. EA13 is used on C64x EMIFA; EA11 is used on
C64x EMIFB.
‡For C620x/C670x DSP, CE1 does not support SDRAM.
§SDCKE exists on C64x DSP only.

SDRAM Interface
1-7OverviewSPRU266A
Table 1−5. TMS320C6000 SDRAM Interface Summary
C62x/C67x EMIF C64x EMIF
EMIFA EMIFB
Feature C6201/C6701
Other
C620x/C670x†C621x/C671x‡
C6416/15/14/12,
DM642
C6411,
DM640/641 C6416/15/14
Interface width 32-bit 32-bit 32-, 16-, 8-bit 64-, 32-, 16-,
8-bit
32-, 16-, 8-bit 16-, 8-bit
SDRAM clock SDCLK CLKOUT2 ECLKOUT ECLKOUT1 ECLKOUT1 ECLKOUT1
Registers for
SDRAM timing
parameters
SDCTL,
SDTIM
SDCTL,
SDTIM
SDCTL,
SDTIM,
SDEXT
SDCTL,
SDTIM,
SDEXT
SDCTL,
SDTIM,
SDEXT
SDCTL,
SDTIM,
SDEXT
SDRAM
control signals
Dedicated
SDRAM
control signals
MUXed with
SBSRAM
control signals
MUXed with
SBSRAM and
Async control
signals
MUXed with
Async and
Programmable
Sync control
signals
MUXed with
Async and
Program-
mable Sync
control signals
MUXed with
Async and
Program-
mable Sync
control signals
Number of
open pages
Single open
page per CE
space
Single open
page per CE
space
4 open pages in
any CE space
4 open pages in
any CE space
4 open pages
in any CE
space
4 open pages
in any CE
space
Programmable
SDRAM
configuration
8- or 9-column
address bits
8- or 9-column
address bits
column, row,
and bank size
column, row,
and bank size
column, row,
and bank size
column, row,
and bank size
Burst mode Not supported.
Performs bursts
by issuing
back-to-back
commands
Not supported.
Performs bursts
by issuing
back-to-back
commands
Supports
SDRAM burst
mode with a
4-word burst
Supports
SDRAM burst
mode with a
4-word burst
Supports
SDRAM burst
mode with a
4-word burst
Supports
SDRAM burst
mode with a
4-word burst
Background
refresh
Yes Yes No No No No
Precharge pin SDA10 SDA10 EA12 EA13 EA13 EA11
SDRAM
self-refresh
mode
No No No Yes Yes No
Page
replacement
Fixed Fixed Random LRU LRU LRU
†This column applies to all C620x/C670x devices, except C6201/C6701 DSP.
‡C6712/C6712C DSP interfaces to 8-bit and 16-bit SDRAM only.

SDRAM Interface
Overview1-8 SPRU266A
1.3.1 SDRAM Initialization
After reset, none of the CE spaces are configured as SDRAM. The CPU should
initialize all of the CE space control registers and the SDRAM extension register
before performing SDRAM initialization by setting the INIT bit to 1. If SDRAM
does not exist in the system, you should not write a 1 to the INIT bit.
The EMIF performs the following steps when INIT is set to 1:
1) Sends a DCAB command to all CE spaces configured as SDRAM.
2) Sends eight refresh commands.
3) Sends an MRS command to all CE spaces configured as SDRAM.
For the duration of SDRAM initialization, the BE signals are inactive high. The
SDRAM initialization is noninterruptible by other EMIF accesses.
1.3.2 Monitoring Page Boundaries
SDRAM is a paged memory type, thus the EMIF SDRAM controller monitors
the active row of SDRAM so that row boundaries are not crossed during the
course of an access. To accomplish this priority, the EMIF stores the address
of the open row in internal page register(s), then performs compares against
that address for subsequent accesses to any SDRAM CE space.
For all C6000 devices, ending the current access is not a condition that forces
the active SDRAM row to be closed. The EMIF leaves the active row open until
it becomes necessary to close it. This decreases the deactivate-reactivate
overhead and allows the interface to capitalize fully on the address locality of
memory accesses.