Texas Instruments TMS320C6000 DSP User manual

TMS320C6000 DSP
Multichannel Audio Serial Port (McASP)
Reference Guide
Literature Number: SPRU041C
July 2003

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iiiContentsSPRU041C
Preface
Read This First
About This Manual
This document describes the multichannel audio serial port (McASP) in the
digital signal processors (DSPs) of the TMS320C6000tDSP family. The
McASPfunctionsasageneral-purposeaudioserialportoptimizedfortheneeds
ofmultichannelaudio applications.TheMcASP isusefulfor time-divisionmul-
tiplexed (TDM) stream, Inter-Integrated Sound (I2S) protocols, and intercom-
ponent digital audio interface transmission (DIT).
Notational Conventions
This document uses the following conventions.
-Hexadecimal numbers are shown with the suffix h. For example, the fol-
lowing number is 40 hexadecimal (decimal 64): 40h.
-Registers in this document are shown in figures and described in tables.
JEachregister figureshowsa rectangledivided intofields that represent
thefieldsoftheregister.Eachfieldislabeledwithitsbitname, itsbegin-
ningandendingbitnumbersabove,anditsread/writepropertiesbelow.
A legend explains the notation used for the properties.
JReservedbits in aregisterfigure designate abitthat is usedfor future
device expansion. Reads from this reserved bit always return the de-
faultvalue.Writestothisreservedbitareignored.Ifwritingtothisfield,
always write the default value for future device compatibility.
31 10
Reserved†Bit
R-0 R/W-0
Legend: R = Read only; R/W = Read/Write; -n= value after reset
†If writing to this field, always write the default value for future device compatibility.

Related Documentation From Texas Instruments
iv SPRU041C
Related Documentation From Texas Instruments
The following documents describe the C6000devices and related support
tools. Copies of these documents are available on the Internet at www.ti.com.
Tip: Enter the literature number in the search box provided at www.ti.com.
TMS320C6000 CPU and Instruction Set Reference Guide (literature
number SPRU189) describes the TMS320C6000CPU architecture,
instruction set, pipeline, and interrupts for these digital signal processors.
TMS320C6000 Peripherals Reference Guide (literature number SPRU190)
describes the peripherals available on the TMS320C6000DSPs.
TMS320C6000 Technical Brief (literature number SPRU197) gives an
introduction to the TMS320C62xand TMS320C67xDSPs,
development tools, and third-party support.
TMS320C64x Technical Overview (SPRU395) gives an introduction to the
TMS320C64xDSP and discusses the application areas that are
enhanced by the TMS320C64x VelociTI.
TMS320C6000 Programmer’s Guide (literature number SPRU198)
describes ways to optimize C and assembly code for the
TMS320C6000DSPs and includes application program examples.
TMS320C6000 Code Composer Studio Tutorial (literature number
SPRU301) introduces the Code Composer Studiointegrated
development environment and software tools.
Code Composer Studio Application Programming Interface Reference
Guide (literature number SPRU321) describes the Code Composer
Studioapplication programming interface (API), which allows you to
program custom plug-ins for Code Composer.
TMS320C6x Peripheral Support Library Programmer’s Reference
(literature number SPRU273) describes the contents of the
TMS320C6000peripheral support library of functions and macros. It
lists functions and macros both by header file and alphabetically,
provides a complete description of each, and gives code examples to
show how they are used.
TMS320C6000 Chip Support Library API Reference Guide (literature
numberSPRU401) describes aset of applicationprogramming interfaces
(APIs) used to configure and control the on-chip peripherals.
Trademarks
Code Composer Studio, C6000, C62x, C64x, C67x, TMS320C6000,
TMS320C62x, TMS320C64x, TMS320C67x, and VelociTI are trademarks of
Texas Instruments.
Related Documentation From Texas Instruments / Trademarks

Contents
vContentsSPRU041C
Contents
1 Overview 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Provides an overview of the multichannel audio serial port (McASP). Included are the features
of the McASP, protocols the McASP supports, and definitions of terms used within this docu-
ment.
1.1 Features 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Protocols Supported 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 System Level Connections 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Considerations When Using a McASP 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4.1 Clocks 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4.2 Data Pins 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4.3 Data Format 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4.4 Data Transfers 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 Definition of Terms 1-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6 TDM Format 1-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6.1 TDM Format 1-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6.2 Inter-Integrated Sound (I2S) Format 1-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.7 S/PDIF Coding Format 1-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.7.1 Biphase-Mark Code (BMC) 1-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.7.2 Subframe Format 1-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.7.3 Frame Format 1-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Architecture 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Discusses the architecture of the McASP.
2.1 Overview 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Clock and Frame Sync Generators 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.1 Transmit Clock 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.2 Receive Clock 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.3 Frame Sync Generator 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.4 Clocking Examples 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Serializers 2-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Format Unit 2-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 State Machine 2-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6 TDM Sequencer 2-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7 Clock Check Circuit 2-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8 Pin Function Control 2-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8.1 McASP Pin Control-Transmit and Receive 2-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8.2 GPIO Pin Control 2-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents
vi SPRU041C
3 Operation 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Discusses the operation of the McASP.
3.1 Setup and Initialization 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.1 Transmit/Receive Section Initialization 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.2 Separate Transmit and Receive Initialization 3-5. . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.3 Importance of Reading Back GBLCTL 3-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.4 Synchronous Transmit and Receive Operation (ASYNC = 0) 3-6. . . . . . . . . . . . . .
3.1.5 Asynchronous Transmit and Receive Operation (ASYNC = 1) 3-6. . . . . . . . . . . . .
3.2 Transfer Modes 3-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.1 Burst Transfer Mode 3-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.2 Time-Division Multiplexed (TDM) Transfer Mode 3-9. . . . . . . . . . . . . . . . . . . . . . . . .
3.2.3 Digital Audio Interface Transmit (DIT) Transfer Mode 3-13. . . . . . . . . . . . . . . . . . . .
3.3 Data Transmission and Reception 3-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.1 Data Ready Status and Event/Interrupt Generation 3-19. . . . . . . . . . . . . . . . . . . . .
3.3.2 Transfers through the Data Port (DAT) 3-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.3 Transfers through the Configuration Bus (CFG) 3-21. . . . . . . . . . . . . . . . . . . . . . . . .
3.3.4 Using the CPU for McASP Servicing 3-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.5 Using the EDMA for McASP Servicing 3-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 Formatter 3-27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.1 Transmit Bit Stream Data Alignment 3-27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.2 Receive Bit Stream Data Alignment 3-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5 Interrupts 3-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.1 Transmit Data Ready Interrupt 3-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.2 Receive Data Ready Interrupt 3-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.3 Error Interrupts 3-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.4 Audio Mute (AMUTE) Function 3-34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.5 Multiple Interrupts 3-36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6 Error Handling and Management 3-37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.1 Unexpected Frame Sync Error 3-37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.2 Buffer Underrun Error - Transmitter 3-38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.3 Buffer Overrun Error - Receiver 3-39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.4 DMA Error - Transmitter 3-39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.5 DMA Error - Receiver 3-39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.6 Clock Failure Detection 3-40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7 Loopback Modes 3-45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.1 Loopback Mode Configurations 3-46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Registers 4-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Describes the registers of the McASP.
4.1 Registers 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.1 Peripheral Identification Register (PID) 4-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.2 Power Down and Emulation Management Register (PWRDEMU) 4-8. . . . . . . . . .
4.1.3 Pin Function Register (PFUNC) 4-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents
viiContentsSPRU041C
4.1.4 Pin Direction Register (PDIR) 4-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.5 Pin Data Output Register (PDOUT) 4-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.6 Pin Data Input Register (PDIN) 4-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.7 Pin Data Set Register (PDSET) 4-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.8 Pin Data Clear Register (PDCLR) 4-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.9 Global Control Register (GBLCTL) 4-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.10 Audio Mute Control Register (AMUTE) 4-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.11 Digital Loopback Control Register (DLBCTL) 4-28. . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.12 DIT Mode Control Register (DITCTL) 4-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.13 Receiver Global Control Register (RGBLCTL) 4-30. . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.14 Receive Format Unit Bit Mask Register (RMASK) 4-32. . . . . . . . . . . . . . . . . . . . . . .
4.1.15 Receive Bit Stream Format Register (RFMT) 4-33. . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.16 Receive Frame Sync Control Register (AFSRCTL) 4-36. . . . . . . . . . . . . . . . . . . . . .
4.1.17 Receive Clock Control Register (ACLKRCTL) 4-37. . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.18 Receive High-Frequency Clock Control Register (AHCLKRCTL) 4-39. . . . . . . . . .
4.1.19 Receive TDM Time Slot Register (RTDM) 4-41. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.20 Receiver Interrupt Control Register (RINTCTL) 4-42. . . . . . . . . . . . . . . . . . . . . . . . .
4.1.21 Receiver Status Register (RSTAT) 4-44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.22 Current Receive TDM Time Slot Registers (RSLOT) 4-47. . . . . . . . . . . . . . . . . . . .
4.1.23 Receive Clock Check Control Register (RCLKCHK) 4-48. . . . . . . . . . . . . . . . . . . . .
4.1.24 Receiver DMA Event Control Register (REVTCTL) 4-50. . . . . . . . . . . . . . . . . . . . . .
4.1.25 Transmitter Global Control Register (XGBLCTL) 4-51. . . . . . . . . . . . . . . . . . . . . . . .
4.1.26 Transmit Format Unit Bit Mask Register (XMASK) 4-53. . . . . . . . . . . . . . . . . . . . . .
4.1.27 Transmit Bit Stream Format Register (XFMT) 4-54. . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.28 Transmit Frame Sync Control Register (AFSXCTL) 4-57. . . . . . . . . . . . . . . . . . . . .
4.1.29 Transmit Clock Control Register (ACLKXCTL) 4-58. . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.30 Transmit High-Frequency Clock Control Register (AHCLKXCTL) 4-60. . . . . . . . .
4.1.31 Transmit TDM Time Slot Register (XTDM) 4-62. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.32 Transmitter Interrupt Control Register (XINTCTL) 4-63. . . . . . . . . . . . . . . . . . . . . . .
4.1.33 Transmitter Status Register (XSTAT) 4-65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.34 Current Transmit TDM Time Slot Register (XSLOT) 4-68. . . . . . . . . . . . . . . . . . . . .
4.1.35 Transmit Clock Check Control Register (XCLKCHK) 4-69. . . . . . . . . . . . . . . . . . . .
4.1.36 Transmitter DMA Event Control Register (XEVTCTL) 4-71. . . . . . . . . . . . . . . . . . . .
4.1.37 Serializer Control Registers (SRCTLn) 4-72. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.38 DIT Left Channel Status Registers (DITCSRA0-DITCSRA5) 4-74. . . . . . . . . . . . .
4.1.39 DIT Right Channel Status Registers (DITCSRB0-DITCSRB5) 4-74. . . . . . . . . . . .
4.1.40 DIT Left Channel User Data Registers (DITUDRA0-DITUDRA5) 4-75. . . . . . . . . .
4.1.41 DIT Right Channel User Data Registers (DITUDRB0-DITUDRB5) 4-75. . . . . . . . .
4.1.42 Transmit Buffer Registers (XBUFn) 4-76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.43 Receive Buffer Registers (RBUFn) 4-76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A Register Bit Restrictions A-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The bit fields that have restrictions on when they may be changed.

Figures
viii SPRU041C
Figures
1-1 McASP as Digital Audio Decoder 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-2 McASP as Digital Audio Encoder 1-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-3 McASP as 16 Channel Digital Processor 1-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-4 Definition of Bit, Word, and Slot 1-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-5 Bit Order and Word Alignment Within a Slot Examples 1-10. . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-6 Definition of Frame and Frame Sync Width 1-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-7 TDM Format—6 Channel TDM Example 1-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-8 TDM Format Bit Delays from Frame Sync 1-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-9 Inter-Integrated Sound (I2S) Format 1-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-10 Biphase-Mark Code (BMC) 1-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-11 S/PDIF Subframe Format 1-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-12 S/PDIF Frame Format 1-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-1 McASP Block Diagram 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-2 Transmit Clock Generator Block Diagram 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-3 Receive Clock Generator Block Diagram 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-4 Frame Sync Generator Block Diagram 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-5 Individual Serializer and Connections Within McASP 2-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-6 Receive Format Unit 2-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-7 Transmit Format Unit 2-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-8 McASP I/O Pin Control Block Diagram 2-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-9 McASP I/O Pin to Control Register Mapping 2-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-1 Burst Frame Sync Mode 3-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-2 Transmit EDMA Event (AXEVT) Generation in TDM Time Slots 3-12. . . . . . . . . . . . . . . . . . . .
3-3 EDMA Events in an Audio Example 3-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4 EDMA Event Triggered on Each Time Slot (AXEVT/AREVT) 3-24. . . . . . . . . . . . . . . . . . . . . . .
3-5 Two Alternating EDMA Events Triggered for Each Time Slot 3-25. . . . . . . . . . . . . . . . . . . . . . .
3-6 Audio Example Odd and Even 3-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-7 Data Flow Through Transmit Format Unit, Illustrated 3-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-8 Data Flow Through Receive Format Unit, Illustrated 3-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-9 Audio Mute (AMUTE) Block Diagram 3-35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-10 Transmit Clock Failure Detection Circuit Block Diagram 3-42. . . . . . . . . . . . . . . . . . . . . . . . . . .
3-11 Receive Clock Failure Detection Circuit Block Diagram 3-44. . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-12 Serializers in Loopback Mode 3-46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-1 Peripheral Identification Register (PID) 4-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-2 Power Down and Emulation Management Register (PWRDEMU) 4-8. . . . . . . . . . . . . . . . . . .
4-3 Pin Function Register 4-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figures
ixContentsSPRU041C
4-4 Pin Direction Register (PDIR) 4-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-5 Pin Data Output Register (PDOUT) 4-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-6 Pin Data Input Register (PDIN) 4-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-7 Pin Data Set Register (PDSET) 4-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-8 PDCLR Pin Data Clear Register (PDCLR) 4-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-9 Global Control Register (GBLCTL) 4-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-10 Audio Mute Control Register (AMUTE) 4-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-11 Digital Loopback Control Register (DLBCTL) 4-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-12 DIT Mode Control Register (DITCTL) 4-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-13 Receiver Global Control Register (RGBLCTL) 4-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-14 Receive Format Unit Bit Mask Register (RMASK) 4-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-15 Receive Bit Stream Format Register (RFMT) 4-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-16 Receive Frame Sync Control Register (AFSRCTL) 4-36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-17 Receive Clock Control Register (ACLKRCTL) 4-37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-18 Receive High-Frequency Clock Control Register (AHCLKRCTL) 4-39. . . . . . . . . . . . . . . . . . .
4-19 Receive TDM Time Slot Register (RTDM) 4-41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-20 Receiver Interrupt Control Register (RINTCTL) 4-42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-21 Receiver Status Register (RSTAT) 4-44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-22 Current Receive TDM Time Slot Register (RSLOT) 4-47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-23 Receive Clock Check Control Register (RCLKCHK) 4-48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-24 Receiver DMA Event Control Register (REVTCTL) 4-50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-25 Transmitter Global Control Register (XGBLCTL) 4-51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-26 Transmit Format Unit Bit Mask Register (XMASK) 4-53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-27 Transmit Bit Stream Format Register (XFMT) 4-54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-28 Transmit Frame Sync Control Register (AFSXCTL) 4-57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-29 Transmit Clock Control Register (ACLKXCTL) 4-58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-30 Transmit High Frequency Clock Control Register (AHCLKXCTL) 4-60. . . . . . . . . . . . . . . . . . .
4-31 Transmit TDM Time Slot Register (XTDM) 4-62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-32 Transmitter Interrupt Control Register (XINTCTL) 4-63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-33 Transmitter Status Register (XSTAT) 4-65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-34 Current Transmit TDM Time Slot Register (XSLOT) 4-68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-35 Transmit Clock Check Control Register (XCLKCHK) 4-69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-36 Transmitter DMA Event Control Register (XEVTCTL) 4-71. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-37 Serializer Control Registers (SRCTLn) 4-72. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-38 DIT Left Channel Status Registers (DITCSRA0-DITCSRA5) 4-74. . . . . . . . . . . . . . . . . . . . . . .
4-39 DIT Right Channel Status Registers (DITCSRB0-DITCSRB5) 4-74. . . . . . . . . . . . . . . . . . . . . .
4-40 DIT Left Channel User Data Registers (DITUDRA0-DITUDRA5) 4-75. . . . . . . . . . . . . . . . . . . .
4-41 DIT Right Channel User Data Registers (DITUDRB0-DITUDRB5) 4-75. . . . . . . . . . . . . . . . . .
4-42 Transmit Buffer Registers (XBUFn) 4-76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-43 Receive Buffer Registers (RBUFn) 4-76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Tables
xSPRU041C
Tables
1-1 Biphase-Mark Encoder 1-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-1 Biphase-Mark Encoder 1-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-2 Preamble Codes 1-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-1 Channel Status and User Data for Each DIT Block 3-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-2 Transmit Bitstream Data Alignment 3-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-3 Receive Bitstream Data Alignment 3-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-1 McASP Registers Accessed Through Configuration Bus 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . .
4-2 McASP Registers Accessed Through Data Port 4-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-3 Peripheral Identification Register (PID) Field Descriptions 4-7. . . . . . . . . . . . . . . . . . . . . . . . . .
4-4 Power Down and Emulation Management Register (PWRDEMU) Field Descriptions 4-8. . .
4-5 Pin Function Register (PFUNC) Field Descriptions 4-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-6 Pin Direction Register (PDIR) Field Descriptions 4-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-7 Pin Data Output Register (PDOUT) Field Descriptions 4-15. . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-8 Pin Data Input Register (PDIN) Field Descriptions 4-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-9 Pin Data Set Register (PDSET) Field Descriptions 4-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-10 Pin Data Clear Register (PDCLR) Field Descriptions 4-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-11 Global Control Register (GBLCTL) Field Descriptions 4-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-12 Audio Mute Control Register (AMUTE) Field Descriptions 4-25. . . . . . . . . . . . . . . . . . . . . . . . .
4-13 Digital Loopback Control Register (DLBCTL) Field Descriptions 4-28. . . . . . . . . . . . . . . . . . . .
4-14 DIT Mode Control Register (DITCTL) Field Descriptions 4-29. . . . . . . . . . . . . . . . . . . . . . . . . . .
4-15 Receiver Global Control Register (RGBLCTL) Field Descriptions 4-30. . . . . . . . . . . . . . . . . . .
4-16 Receive Format Unit Bit Mask Register (RMASK) Field Descriptions 4-32. . . . . . . . . . . . . . . .
4-17 Receive Bit Stream Format Register (RFMT) Field Descriptions 4-33. . . . . . . . . . . . . . . . . . . .
4-18 Receive Frame Sync Control Register (AFSRCTL) Field Descriptions 4-36. . . . . . . . . . . . . . .
4-19 Receive Clock Control Register (ACLKRCTL) Field Descriptions 4-38. . . . . . . . . . . . . . . . . . .
4-20 Receive High-Frequency Clock Control Register (AHCLKRCTL) Field Descriptions 4-39. . .
4-21 Receive TDM Time Slot Register (RTDM) Field Descriptions 4-41. . . . . . . . . . . . . . . . . . . . . . .
4-22 Receiver Interrupt Control Register (RINTCTL) Field Descriptions 4-42. . . . . . . . . . . . . . . . . .
4-23 Receiver Status Register (RSTAT) Field Descriptions 4-44. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-24 Current Receive TDM Time Slot Register (RSLOT) Field Descriptions 4-47. . . . . . . . . . . . . .
4-25 Receive Clock Check Control Register (RCLKCHK) Field Descriptions 4-48. . . . . . . . . . . . . .
4-26 Receiver DMA Event Control Register (REVTCTL) Field Values 4-50. . . . . . . . . . . . . . . . . . . .
4-27 Transmitter Global Control Register (XGBLCTL) Field Descriptions 4-51. . . . . . . . . . . . . . . . .

Tables
xiContentsSPRU041C
4-28 Transmit Format Unit Bit Mask Register (XMASK) Field Descriptions 4-53. . . . . . . . . . . . . . .
4-29 Transmit Bit Stream Format Register (XFMT) Field Descriptions 4-54. . . . . . . . . . . . . . . . . . .
4-30 Transmit Frame Sync Control Register (AFSXCTL) Field Descriptions 4-57. . . . . . . . . . . . . .
4-31 Transmit Clock Control Register (ACLKXCTL) Field Descriptions 4-59. . . . . . . . . . . . . . . . . . .
4-32 Transmit High-Frequency Clock Control Register (AHCLKXCTL) Field Descriptions 4-60. . .
4-33 Transmit TDM Time Slot Register (XTDM) Field Descriptions 4-62. . . . . . . . . . . . . . . . . . . . . .
4-34 Transmitter Interrupt Control Register (XINTCTL) Field Descriptions 4-63. . . . . . . . . . . . . . . .
4-35 Transmitter Status Register (XSTAT) Field Descriptions 4-65. . . . . . . . . . . . . . . . . . . . . . . . . . .
4-36 Current Transmit TDM Time Slot Register (XSLOT) Field Descriptions 4-68. . . . . . . . . . . . . .
4-37 Transmit Clock Check Control Register (XCLKCHK) Field Descriptions 4-69. . . . . . . . . . . . .
4-38 Transmitter DMA Event Control Register (XEVTCTL) Field Values 4-71. . . . . . . . . . . . . . . . . .
4-39 Serializer Control Registers (SRCTLn) Field Descriptions 4-72. . . . . . . . . . . . . . . . . . . . . . . . .
A-1 Bits With Restrictions on When They May be Changed A-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-1OverviewSPRU041C
Overview
This chapter provides an overview of the multichannel audio serial port
(McASP)in thedigitalsignal processors (DSPs)of the TMS320C6000tDSP
family.IncludedarethefeaturesoftheMcASP,protocolstheMcASPsupports,
and definitions of terms used within this document.
The multichannel audio serial port (McASP) functions as a general-purpose
audio serial port optimized for the needs of multichannel audio applications.
The McASP is useful for time-division multiplexed (TDM) stream, Inter-Inte-
grated Sound (I2S) protocols, and intercomponent digital audio interface
transmission (DIT).
The McASP consists of transmit and receive sections that may operate syn-
chronized, or completely independently with separate master clocks, bit
clocks, and frame syncs, and using different transmit modes with different bit-
streamformats.TheMcASPmodulealsoincludesupto16serializersthatcan
be individually enabled to either transmit or receive. In addition, all of the
McASP pins can be configured as general-purpose input/output (GPIO) pins.
Topic Page
1.1 Features 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Protocols Supported 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 System Level Connections 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Considerations When Using a McASP 1-7. . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 Definition of Terms 1-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6 TDM Format 1-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.7 S/PDIF Coding Format 1-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 1

Features
Overview1-2 SPRU041C
1.1 Features
Features of the McASP include:
-Two independent clock generator modules for transmit and receive
JClocking flexibility allows the McASP to receive and transmit at differ-
entrates.Forexample,theMcASPcanreceivedataat48kHzbutout-
put up-sampled data at 96 kHz or 192 kHz.
-Independent transmit and receive modules, each includes:
JProgrammable clock and frame sync generator
JTDM streams from 2 to 32, and 384 time slots
JSupport for time slot sizes of 8, 12, 16, 20, 24, 28, and 32 bits
JData formatter for bit manipulation
-Individually assignable serial data pins (up to 16 pins)
-Glueless connection to audio analog-to-digital converters (ADC), digital-
to-analog converters (DAC), codec, digital audio interface receiver (DIR),
and S/PDIF transmit physical layer components
-Wide variety of I2S and similar bit-stream format
-Integrated digital audio interface transmitter (DIT) supports:
JS/PDIF, IEC60958-1, AES-3 formats
JUp to 16 transmit pins
JEnhanced channel status/user data RAM
-384-slot TDM with external digital audio interface receiver (DIR) device
JFor DIR reception, an external DIR receiver integrated circuit should
be used with I2S output format and connected to the McASP receive
section.
-Extensive error checking and recovery
JTransmit underruns and receiver overruns due to the system not
meeting real-time requirements
JEarly or late frame sync in TDM mode
JOut-of-range high-frequency master clock for both transmit and re-
ceive
JExternal error signal coming into the AMUTEIN input
JDMA error due to incorrect programming

Protocols Supported
1-3OverviewSPRU041C
1.2 Protocols Supported
The McASP supports a wide variety of protocols.
-Transmit section supports
JWide variety of I2S and similar bit-stream formats
JTDM streams from 2 to 32 time slots
JS/PDIF, IEC60958–1, AES-3 formats
-Receive section supports
JWide variety of I2S and similar bit-stream formats
JTDM streams from 2 to 32 time slots
JTDM stream of 384 time slots specifically designed for easy interface
to external digital interface receiver (DIR) device transmitting DIR
frames to McASP using the I2S protocol (one time slot for each DIR
subframe)
The transmit and receive sections may each be individually programmed to
support the following options on the basic serial protocol:
-Programmable clock and frame sync polarity (rising or falling edge):
ACLKR/X, AHCLKR/X, and AFSR/X
-Slotlength (numberofbits pertime slot): 8,12, 16,20,24, 28,32bits sup-
ported
-Wordlength (bitsperword):8,12,16,20,24,28, 32bits; alwaysless than
or equal to the time slot length
-First-bit data delay: 0, 1, 2 bit clocks
-Left/right alignment of word inside slot
-Bit order: MSB first or LSB first
-Bit mask/pad/rotate function
JAutomatically aligns data for DSP internally in either Q31 or integer
formats
JAutomaticallymasksnonsignificant bits(setsto0,1, orextends value
of another bit)
In DIT mode, additional features of the transmitter are:
-Transmit-only mode–384 time slots (subframe) per frame
-Bi-phase encoded 3.3 V output
-Support for consumer and professional applications
-Channel status RAM (384 bits)
-User data RAM (384 bits)
-Separate valid bit (V) for subframe A, B

System Level Connections
Overview1-4 SPRU041C
On C6000 DSPS in I2S mode, the transmit and receive sections can support
simultaneoustransfersonuptoallserialdatapinsoperatingas192kHzstereo
channels.
On C6000 DSPS in DIT mode, the transmitter can support a 192 kHz frame
rate (stereo) on up to all serial data pins simultaneously (note that the internal
bit clock for DIT runs two times faster than the equivalent bit clock for I2S
mode, due to the need to generate Biphase Mark Encoded Data).
1.3 System Level Connections
Figure 1–1, Figure 1–2, and Figure 1–3 show examples of McASP usage in
digital audio encoder/decoder systems.
Figure 1–1. McASP as Digital Audio Decoder
(a) McASP to Parallel 2-Channel DACs
TXRX
McASP
C6000 DSP
DIR
DVD
player
Coaxial/
optical
S/PDIF
encoded
I2S
Amp
2-ch
DAC
DAC
2-ch Amp
2-ch
DAC Amp
DAC
2-ch Amp
Stereo I2S
Protocols Supported / System Level Connections

System Level Connections
1-5OverviewSPRU041C
Figure 1–1.McASP as Digital Audio Decoder (Continued)
(b) McASP to 6-Channel DAC and 2-Channel DAC
TXRX
McASP
C6000 DSP
DIR
DVD
player
Coaxial/
optical
S/PDIF
encoded
I2S
2-ch
DAC Amp
6-ch
DAC Amp
Stereo
I2S
(c) McASP to Digital Amplifier
TXRX
McASP
C6000 DSP
DIR
DVD
player
Coaxial/
optical
S/PDIF
encoded
I2S
PWM
generator
Stereo I2S Digital
amp
Digital
amp
Digital
Digital
amp
amp
generator
PWM
generator
generator
PWM
PWM

System Level Connections
Overview1-6 SPRU041C
Figure 1–2. McASP as Digital Audio Encoder
TXRX
McASP
C6000 DSP
DIT S/PDIF
encoded
2-ch ADC
2-ch ADC
2-ch ADC
LF, RF
C, LFE
LS, RS
Stereo I2S
Figure 1–3. McASP as 16 Channel Digital Processor
2-ch ADC
2-ch ADC
2-ch ADC
2-ch ADC
2-ch ADC
2-ch ADC
2-ch ADC
2-ch ADC RX DIT TX
C6000 DSP 8 S/PDIF
encoded
outputs

Considerations When Using a McASP
1-7OverviewSPRU041C
1.4 Considerations When Using a McASP
The following is a list of things to be considered for systems using a McASP:
1.4.1 Clocks
For each receive and transmit section:
-External or internal generated bit clock and high frequency clock?
-If internally generated, what is the bit clock speed and the high frequency
clock speed?
-Clock polarity?
-External or internal generated frame sync?
-If internally generated, what is frame sync speed?
-Frame sync polarity?
-Frame sync width?
-Transmit and receive sync or asynchronous?
1.4.2 Data Pins
For each pin of each McASP:
-McASP or GPIO?
-Input or output?
1.4.3 Data Format
For each transmit and receive data:
-Internal numeric representation (integer, Q31 fraction)?
-I2S or DIT (transmit only)?
-Time slot delay (0, 1, or 2 bit)?
-Alignment (left or right)?
-Order (MSB first, LSB first)?
-Pad (if yes, pad with what value)?
-Slot size?
-Rotate?
-Mask?
1.4.4 Data Transfers
-Internal: EDMA or CPU?
-External: TDM or burst?
-Bus: configuration bus (CFG) or data port (DAT)?

Definition of Terms
Overview1-8 SPRU041C
1.5 Definition of Terms
TheserialbitstreamtransmittedorreceivedbytheMcASPisalongsequence
of 1s and 0s, either output or input on one of the audio transmit/receive pins
(AXR[n]). However, the sequence has a hierarchical organization that can be
described in terms of frames of data, slots, words, and bits.
A basic synchronous serial interface consists of three important components:
clock, frame sync, and data. Figure 1–4 shows two of the three basic compo-
nents—the clock (ACLK) and the data (AXR[n]). Figure 1–4 does not specify
whethertheclockisfortransmit(ACLKX)orreceive(ACLKR)becausethedef-
initionsoftermsapplytobothreceiveandtransmitinterfaces.Inoperation,the
transmitter uses ACLKX as the serial clock, and the receiver uses ACLKR as
the serial clock. Optionally, the receiver can use ACLKX as the serial clock
whenthetransmitterandreceiveroftheMcASPareconfiguredtooperatesyn-
chronously.
Bit A bit is the smallest entity in the serial data stream. The beginning
and end of each bit is marked by an edge of the serial clock. The
durationof a bit isa serial clock period.A 1 is representedby a logic
high on the AXR[n] pin for the entire duration of the bit. A 0 is
represented by a logic low on the AXR[n] pin for the entire duration
of the bit.
Word A word is a group of bits that make up the data being transferred
between the DSP and the external device. Figure 1–4 shows an
8-bit word.
Slot A slot consists of the bits that make up the word, and may consist
ofadditionalbitsusedtopadthewordtoaconvenientnumberofbits
for the interface between the DSP and the external device. In
Figure 1–4,theaudiodataconsistsofonly8bitsofusefuldata(8-bit
word),butitispadded with4zeros(12-bitslot) tosatisfy thedesired
protocol in interfacing to an external device. Within a slot, the bits
may be shifted in/out of the McASP on the AXR[n] pin either MSB
or LSB first. When the word size is smaller than the slot size, the
word may be aligned to the left (beginning) of the slot or to the right
(end) of the slot. The additional bits in the slot not belonging to the
word may be padded with 0, 1, or with one of the bits (the MSB or
the LSB typically) from the data word. These options are shown in
Figure 1–5.

Definition of Terms
1-9OverviewSPRU041C
Figure 1–4. Definition of Bit, Word, and Slot
b7 b6 b5 b4 b3 b2 b1 b0 P P P P
bit
ACLK
AXR[n]
word
slot
Notes: 1) b7:b0 –bits. Bits b7 to b0 form a word
2) P –pad bits. Bits b7 to b0, together with the four pad bits, form a slot.
3) In this example, the data is transmitted MSB first, left aligned.