Texas Instruments LDC5072-Q1 User manual

LDC5072-Q1 Inductive Position Sensor Front-End With Sin/Cos Interface
1 Features
• AEC-Q100 qualified with the following results:
– Device temperature grade 0: –40°C to +160°C
ambient operating temperature
• Integrated analog front-end IC for contact-less,
inductive position sensors for absolute rotary
position from 0° to 360°
• Removes the need for magnets, lowering system
cost
• Supports operation in harsh environments;
immune to stray magnetic fields, dirt, and
contamination
• High resolution and accuracy of ≤ 1 degree at
rotational speeds up to 480,000 RPM
• Differential signal paths with sine and cosine
outputs supporting a wide dynamic input range
• 5-V and 3.3-V input supply operating modes
• Integrated LC oscillator in the 2.4-MHz to 5-MHz
band to excite the inductive sensor coil
• Differential output drivers with high-voltage
protection and large capacitive load capability
• Automatic and manual gain control to maximize
dynamic range of output drivers
• Functional Safety-Compliant
– Developed for functional safety applications
– Documentation available to aid ISO 26262
system design
– Systematic capability up to ASIL C(D)
– Hardware capability up to ASIL C
• Extensive IC, sensor input, output, and supply pin
diagnostics
• Reverse voltage and overvoltage protection on
input supply and output pins from –15 V to 30 V
• Supports redundant mode for functional safety
2 Applications
• Rotary Position Sensors for:
– EV/HEV traction motor inverters
– Electric power steering
– Brake boost motors
– Integrated starter generators
• Small angular or arc-motion sensors for:
– Pedal position
– Valves and actuators
– Robots
3 Description
The LDC5072-Q1 IC is an analog front-end for
contact-less, inductive position sensors targeted for
absolute rotary position in automotive and industrial
applications. The LDC5072-Q1 excites a coil that is
typically printed on a printed circuit board (PCB). The
excitation is coupled back into two sets of receiver
coils on the same PCB using a conductive target
that is placed in close proximity of the PCB. The
conductive target can also be a pattern printed on
another PCB. The coil PCB stays stationary and the
target moves with the motor, actuator, or valve. The
excitation coil generates a secondary voltage on the
receiver coils depending on the position of the target
relative to the receiver coils. A signal representation
of the position is obtained by reading in the voltages
from the receiver coils, processing it, and giving
analog outputs representing the Sine and Cosine
components of the position of the target.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
LDC5072-Q1 TSSOP (16) 5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Control Board
1LCIN
2LCOUT
3TM0
4IN0P
5IN1P
6IN0N
7IN1N
8AGC_EN
16
VCC
15
GND
14
VREG
13
OUT0P
12
OUT0N
11
OUT1P
10
OUT1N
9
TOUT
C8
From Input
Supply
C2
To MCU for
Angle Calc.
Inductive
Sensor
LCIN
LCOUT
C1
C3
C7
R1
L4
L3
L2
L1
R2
RPU RPU
RPD RPD
C4 C5 C6
RINFLT
RINFLT
RINFLT
RINFLT CINFLT
CINFLT
CINFLT
CINFLT
GND
LCIN
LCOUT
10K
10K
VREG
VREG
LDC5072-Q1 Typical Application Diagram
LDC5072-Q1
SNOSD47C – DECEMBER 2018 – REVISED JULY 2023
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Description (cont.)...........................................................5
6 Pin Configuration and Functions...................................5
7 Specifications.................................................................. 6
7.1 Absolute Maximum Ratings ....................................... 6
7.2 ESD Ratings .............................................................. 6
7.3 Recommended Operating Conditions ........................6
7.4 Thermal Information ...................................................6
7.5 Electrical Characteristics ............................................7
7.6 Diagnostics .............................................................. 10
7.7 Switching Characteristics .........................................12
7.8 Typical Characteristics..............................................13
8 Detailed Description......................................................14
8.1 Overview...................................................................14
8.2 Functional Block Diagram.........................................15
8.3 Feature Description...................................................15
8.4 Device Functional Modes..........................................22
9 Application and Implementation..................................26
9.1 Application Information............................................. 26
9.2 Typical Applications.................................................. 26
10 Power Supply Recommendations..............................33
10.1 Mode 1: VCC = 5 V, VREG = 3.3 V.........................33
10.2 Mode 2: VCC = VREG = 3.3 V................................33
11 Layout........................................................................... 34
11.1 Layout Guidelines................................................... 34
11.2 Layout Example...................................................... 34
12 Device and Documentation Support..........................35
12.1 Receiving Notification of Documentation Updates..35
12.2 Support Resources................................................. 35
12.3 Trademarks.............................................................35
12.4 Electrostatic Discharge Caution..............................35
12.5 Glossary..................................................................35
13 Mechanical, Packaging, and Orderable
Information.................................................................... 35
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (August 2021) to Revision C (July 2023) Page
• Changed data sheet status visibility to public release........................................................................................1
Changes from Revision A (September 2020) to Revision B (August 2021) Page
• Updated the numbering format for tables, figures, and cross-references throughout the document................. 1
• The application diagrams in the Description section and Figures 9-1, 9-3, 9-4, and 9-5 were updated. .......... 1
• Separated output comparator short into positive and negative limits............................................................... 10
• The tPRWR_ON_DT in the “Switching Characteristics” is incorrectly specified. The values “360/400/440” will
be changed to “302/336/370”............................................................................................................................12
• The AGC rate change is imprecisely specified in Automatic Gain Control: “1 code each second” was updated
to “one code approximately every 840mS”. Added eight codes every 3.2uS during start-up in the fast AGC
region................................................................................................................................................................18
• Updated application diagram in 5-V Supply Mode and updated Table 9-1 to include connection instructions for
the AGC_EN pin............................................................................................................................................... 26
• The resistor R2 in the example design in AGC Mode was updated to 1.5KΩ. ................................................ 27
• Changed Figure 9-3 .........................................................................................................................................29
Changes from December 7, 2018 to September 30, 2020 (from Revision * (December 2018) to
Revision A (September 2020)) Page
• Updated Device Max Ambient Operating Temperature to 160°C. .....................................................................1
• Updated Functional Safety Capability text..........................................................................................................1
• Updated pin description for better clarity replacing inverted and non-inverted with negative and positive
respectively. ....................................................................................................................................................... 5
• Updated TA to 160℃ in Absolute Maximum Ratings .........................................................................................6
• Updated TJ to 170℃ in Absolute Maximum Ratings ......................................................................................... 6
• Added 4000V HBM ESD information to ESD Ratings........................................................................................ 6
• Changed INL to ErrINL and updated definition and values in Signal Path section of Electrical
Characteristics ...................................................................................................................................................7
• Changed maximum value of tPROP_CH over temperature and changed maximum TA to 160°C in Signal Path
section of Electrical Characteristics ...................................................................................................................7
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• Changed maximum value of tPROP_DIFF in Signal Path section of Electrical Characteristics ............................. 7
• Added VOUT_SE in Signal Path section of Electrical Characteristics .................................................................. 7
• Changed maximum value of VOUT_DIFF_TC over temperature and changed maximum TA to 160°C in Signal
Path section of Electrical Characteristics ...........................................................................................................7
• Added GMIS_SIG_PATH parameter in Signal Path section of Electrical Characteristics ........................................ 7
• Added Vin_off parameter in Signal Path section of Electrical Characteristics ..................................................... 7
• Added nSIG_PATH_SE parameter in Signal Path section of Electrical Characteristics .......................................... 7
• Added nSIG_PATH_DIFF parameter in Signal Path section of Electrical Characteristics ........................................7
• Split VAMP_LC between 25°C and over temperature and specified values wnen VREG is below regulation
voltage in Excitation section of Electrical Characteristics ..................................................................................7
• Split VDC_LC between 25°C and over temperature and specified values wnen VREG is below regulation
voltage in Excitation section of Electrical Characteristics ..................................................................................7
• Changed limits and test conditions for ILIM_LC in Excitation section of Electrical Characteristics ..................... 7
• Added Internal Pull Up resistor parameter RPU_LCx in Excitation section of Electrical Characteristics ............. 7
• Added Internal Pull down resistor parameter RPD_LCx in Excitation section of Electrical Characteristics ......... 7
• Expanded limits for input differential input signal amplitude VDIFF_REC in Receiver section of
Electrical Characteristics ................................................................................................................................... 7
• Added Internal pull-up resistor parameter RPU_INxN in Receiver section of Electrical Characteristics ............... 7
• Added Internal pull-down resistor parameter RPD_INxP in Receiver section of Electrical Characteristics ...........7
• Split RACG_EN_AUTO parameter into RAGC_EN_MIN and RAGC_EN_MAX in AGC section of
Electrical Characteristics ................................................................................................................................... 7
• Added internal pull-up resistor RPU_AGC_EN parameter in AGC section of Electrical Characteristics ................7
• Updated definition of AGC_Target, AGC_FH, AGC_SH, AGC_SL and AGC_FL for clarity and
split parameter across temperature and VCC in AGC section of Electrical Characteristics ............................. 7
• Changed VILIM_OUT to IILIM_OUT for clarity in Output Stage section of Electrical Characteristics ........................7
• Removed required conditions for VCC and GND connection to be valid and added min, and max values for
RPD_OUT and RPU_OUT parameters in Output Stage section of Electrical Characteristics ..................................7
• Added IOUT_NOVCC_* and IOUT_NOGND_* parameters in Output Stage section of Electrical Characteristics ........ 7
• Removed required conditions for VCC and GND connection to be valid and added test conditions for
VOUT_FLT_LOW and VOUT_FLT_HIGH parameters in Output Stage section of Electrical Characteristics .................7
• Split VOUT_FLT_HIGH and VOUT_FLT_LOW parameters across temperature and VCC in Output Stage section of
Electrical Characteristics ................................................................................................................................... 7
• Added IOUT_LK_PU parameter in Output Stage section of Electrical Characteristics ...........................................7
• Added internal impedance parameters IPD_INx*_BIST in Diagnostics .................................................................10
• Added pin BIST comparator thresholds VTH_FALL_INx*_BIST in Diagnostics .......................................................10
• Added internal impedance parameter IPU_AGC_EN_BIST on AGC_EN pin in Diagnostics .................................10
• Added value for VREG capacitor loss CLOSS_VREG in Diagnostics .................................................................. 10
• Moved VPOR_VREG_xth to Diagnostics ..............................................................................................................10
• Added LC Frequency fault detection parameter fFLTH_LC in Diagnostics ......................................................... 10
• Added internal impedance on LCx pins parameters, IPx_LCx_BIST in Diagnostics ............................................ 10
• Added tMIN_PH_IMB in Diagnostics .....................................................................................................................10
• Added AGC fault limits, VALAGC_INP_OOR_x in Diagnostics ...............................................................................10
• Added input out-of-range pin and low-pass filter parameters, VOOR_H_INx_x in Diagnostics ............................ 10
• Added common mode fault parmeters for output pin, VCM_x_OUTx_PIN in Diagnostics ..................................... 10
• Added VOUTx_SHRT_CMP_OFF in Diagnostics ..................................................................................................... 10
• Added internal regulator under voltage parameter, VUV_DVDD in Diagnostics ..................................................10
• Added VTOGGLE_AGC_EN in Diagnostics ............................................................................................................10
• Added thermal shutdown parameters TTSD_x in Diagnostics ...........................................................................10
• Combined VCC out of range fault degltich times in tVCC_FLT_DT and updated value in Switching
Characteristics .................................................................................................................................................12
• Added VREG over voltage deglitch time tVREG_OV_DT in Switching Characteristics ........................................ 12
• Added LC amplitude fault deglitch times in Switching Characteristics ............................................................ 12
• Updated values for tAGC_EN_x_DT parameters Switching Characteristics ......................................................... 12
• Added input pin and low pass filter fault deglitch times in Switching Characteristics ...................................... 12
• Added and updated outpin fault deglitch times tOUT_x_DT in Switching Characteristics ................................... 12
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• Added AGC deglitch times tAGC_x_DT in Switching Characteristics ..................................................................12
• Renamed tFLT_SIGNAL to tFLT_RECOV in Switching Characteristics .....................................................................12
• Added power on degltich time tPWR_ON_DT in Switching Characteristics ......................................................... 12
• Added Figure 7-6 for OUTx leakage current.....................................................................................................13
• Updated text in Signal Processing Block for clarity.......................................................................................... 16
• Updated Fixed Gain Control section based on new design..............................................................................18
• Updated variable name in Equation 8 for clarity............................................................................................... 18
• Updated text in Automatic Gain Control to add information on time-step of the AGC block.............................18
• Added details on output pin diagnostics and output ratiometricity to VCC in Output Stage . .......................... 19
• Added Undervoltage Diagnostics, Initialization Diagnostics, Normal State Diagnostics and Fault State
Diagnostics to list details on the diagnsostics available in LDC5072-Q1 ........................................................ 20
• Added details for device functional modes. Added Figure 8-5 and described each of the states in LDC5072-
Q1 ....................................................................................................................................................................22
• Updated application diagram in 5-V Supply Mode and updated Table 9-1 with new optional component values
for EMC robustness..........................................................................................................................................26
• Updated application diagram in 3.3-V Supply Mode with new optional component values for
EMC robustness............................................................................................................................................... 29
• Updated application diagram in Section 9.2.3 with new optional component values for EMC robustness.......31
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5 Description (cont.)
The LDC5072-Q1 can be supplied either with a 3.3-V or 5-V input, and the analog Sine and Cosine outputs can
be connected to an MCU to calculate the angle. The device provides ESD, EMC/EMI immunity, reverse battery
protection, and reverse current protection on short to high voltage on output pins. The supply and output pins are
all high-voltage compliant. The device provides immunity against motor noise and can filter out-of-band low- and
high-frequency noise. The LDC5072-Q1 has extensive diagnostic features to detect sensor faults such as shorts
and opens, along with internal diagnostics such as current limit, overvoltage, and undervoltage detection. The
LDC5072-Q1 is designed according to ISO 26262 specifications that target functional safety applications.
6 Pin Configuration and Functions
1LCIN 16 VCC
2LCOUT 15 GND
3TM0 14 VREG
4IN0P 13 OUT0P
5IN1P 12 OUT0N
6IN0N 11 OUT1P
7IN1N 10 OUT1N
8AGC_EN 9 TOUT
Not to scale
Figure 6-1. PW Package 16-Pin TSSOP Top View
Table 6-1. Pin Functions
PIN TYPE(1) DESCRIPTION
NO. NAME
1 LCIN I/O LC oscillator input
2 LCOUT I/O LC oscillator output
3 TM0 I/O Test Mode Input
4 IN0P I Input channel 0 positive
5 IN1P I Input channel 1 positive
6 IN0N I Input channel 0 negative
7 IN1N I Input channel 1 negative
8 AGC_EN I Automatic Gain Control Enable and Fixed Gain Setting
9 TOUT I/O Test Mode Output
10 OUT1N O Output channel 1 negative
11 OUT1P O Output channel 1 positive
12 OUT0N O Output channel 0 negative
13 OUT0P O Output channel 0 positive
14 VREG I/O Regulated 3.3-V Supply output
15 GND G Ground
16 VCC P Input Voltage Supply
(1) I = input, O = output, I/O = input and output, G = ground, P = power
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Input Supply voltage -15 30
V
OUT0P, OUT0N, OUT1P, OUT1N Output pin voltage -15 30
VREG Regulator output voltage -0.3 5.5
GND Ground Pin voltage -0.3 0.3
LCOUT, LCIN LC Oscillator pin voltage -0.3 5.5
AGC_EN, TM0, TOUT, IN0P, IN0N, IN1P, IN1N All other pin voltage -0.3 5.5
TA Operating free air temperature -40 160
°CTJ Operating junction temperature -40 170
Tstg Storage temperature range -65 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
7.2 ESD Ratings
VALUE UNIT
V(ESD) Electrostatic discharge
Human-body model (HBM), per AEC Q100-002
(1)
HBM ESD Classification Level 2
All pins ±2000
V
OUT0x, OUT1x, IN0x, IN1x,
LCIN, LCOUT, VCC to GND
only
±4000
Charged-device model (CDM), per AEC
Q100-011
CDM ESD Classification Level C4B
All pins ±500
Corner pins (1, 8, 9, 16) ±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCC_50 VCC input voltage (5V input mode) 4.5 5 5.6 V
VCC_33 VCC and VREG input voltage (3.3V input mode) 3.15 3.3 3.6
IQDuring startup and in operation (excluding LC oscillator load and OUTxx load) 22 mA
7.4 Thermal Information
THERMAL METRIC(1)
LDC5072-Q1
UNITPW (TSSOP)
16 PINS
RθJA Junction-to-ambient thermal resistance 93.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 24.1 °C/W
RθJB Junction-to-board thermal resistance 39.7 °C/W
ψJT Junction-to-top characterization parameter 0.9 °C/W
ψJB Junction-to-board characterization parameter 39.1 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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7.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
over recommended Vcc range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input Supply
VCCRamp Allowed VCC ramp up rate 0.17 100e6 V/s
CEXT_VCC External VCC decoupling capacitor range 80 100 nF
Internal LDO Regulator VREG
VVREG Internal LDO output voltage 3.15 3.3 3.6
VVPOR_VREG_UTH VREG power-on upper threshold 3.15
VPOR_VREG_LTH VREG power-on lower thershold 2.91
ILOAD_REG_EXT
Maximum external load on VREG (used
for setting voltage on AGC_EN pin
externally) (Information Only)
1mA
ILIM_VREG VREG current limit 40 90
CEXT_VREG External VREG decoupling capacitor 180 2000 nF
Signal Path
ErrINL
Integral Non-Linearity error(3) of the signal
path transfer function for each channel
measured as:
Maximum % deviation of output from a
best fit line through measured outputs
when input is swept from minium to
maximum value.
For static inputs; VCC=5V;
-3.5V ≤( VOUTxP-VOUTxN) ≤
3.5V
1% 2.5 %
tPROP_CH
Propagation Delay through receive stage
at room temperature.
Measured as zero crossing
of diffrential input (INx) to
zero crossing of differential
output (OUTx)
COUT on each pin = 10nF
3.3 4.6
μs
Propagation Delay through receive stage
across temperature (-40℃ to 160℃). 3 5
tPROP_DIFF Propagation Delay difference between two
channels across temperature
Measured as delay
between the zero crossings
of the diffrential outputs.
500 ns
VOUT_SE Difference between single ended outputs
calculated at VOUT0P-VOUT1P
Measured for static inputs
only for VCC=5V; -1.75V ≤
( VOUT0P-VOUT1P) ≤ 1.75V
50 65 mV
VOUT_DIFF
Difference between differential output
calculated as (VOUT0P-VOUT0N) - (VOUT1P-
VOUT1N) at room temperature Measured for static inputs
only for VCC=5V; -3.5V ≤
( VOUTxP-VOUTxN) ≤ 3.5V
100
mV
VOUT_DIFF_TC
Deviation of VOUT_DIFF at -40℃ from room
temperature 20
Deviation of VOUT_DIFF at 160℃ from room
temperature 38
GMIS_SIG_PATH
Gain mismatch between Channel
1 and Channel 2 signal
path calculated as (Gainout1-Gainout0)/
((Gainout1+Gainout0)*0.5)(2)
Fixed Gain Mode;
VCC=3.3V 4.55%VREG <
VAGC_EN < 95.45%VREG
-40℃ ≤ TA ≤ 160°C
-0.4 0.4
%
Fixed Gain Mode;
VCC=5.0V; 4.55%VREG <
VAGC_EN < 95.45%VREG
-40℃ ≤ TA ≤ 160°C
-0.35 0.55
Vin_off
Input referred offset for IN0 channel(2)
measured with input shorted and exciter
coil connected
VCC=3.3V, 5.0V;
Fixed Gain Mode;
30%VREG < VAGC_EN <
95.45%VREG
-40℃ ≤ TA ≤ 160°C
150 170 µV
Input referred offset for IN1 channel(2)
measured with input shorted and exciter
coil connected
50 100 µV
nSIG_PATH_SE
Input referred noise for the complete
signal path for single ended output for
each channel(2) 25 nV/√Hz
nSIG_PATH_DIFF
Input referred noise for the complete
signal path for differential output for each
channel(2) 36 nV/√Hz
Excitation
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over operating free-air temperature range (unless otherwise noted)
over recommended Vcc range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VAMP_LC
LC oscillator differential amplitude
3.15V ≤ VVREG ≤ 3.6;
TA=25°C 70 75.8 81.5
%Vreg
3.15V ≤ VVREG ≤ 3.6; -40°C
< TA < 160°C 64 87
LC oscillator differential amplitude when
VVREG is below regulation voltage
VPOR_VREG_LTH ≤ VVREG ≤
VPOR_VREG_UTH; TA=25°C 69.5 82.5
VPOR_VREG_LTH ≤ VVREG ≤
VPOR_VREG_UTH; -40°C < TA
< 160°C
63 88
VDC_LC
DC operating point for LC oscillator
3.15V ≤ VVREG ≤ 3.6;
TA=25°C 47 50 52.5
%VREG
3.15V ≤ VVREG ≤ 3.6; -40°C
< TA < 160°C 43.5 56.5
DC operating point for LC oscillator when
VVREG is below regulation voltage
VPOR_VREG_LTH ≤ VVREG ≤
VPOR_VREG_UTH; TA=25°C 47.5 53
VPOR_VREG_LTH ≤ VVREG ≤
VPOR_VREG_UTH; -40°C < TA
< 160°C
42.5 57.5
ILIM_LC (2) RMS value of LC oscillator current limit 13 30 mA
fOSC_LC (2) LC oscillator resonant frequency 2.4 5 MHz
THDLC (2) Total harmonic distortion of oscillator
output (VLCIN-VLCOUT)-30 dB
RPU_LCx Internal pull up resistance to VREG on
LCIN and LCOUT pins 220 330 KΩ
RPD_LCx Internal pull down resistance to GND on
LCIN and LCOUT pins 220 330 KΩ
Rp Allowed range for equivalent parallel
resistance of LC oscillator coil 167 5000 Ω
LAllowed range of inductance of excitation
coil resonator 5 μH
CLC1, CLC2 Allowed range for capacitors for excitation
coil 100 370 pF
CMIS Allowed capacitor mismatch (between
CLC1 and CLC2)-10 10 %
Receiver
VDIFF_REC Allowed range for differential input signal
amplitude
In fixed gain mode, voltage
on AGC_EN pin adjusted to
set gain to avoid clipping
5 400 mVp-p
VCOM_REC Common mode voltage forced on input
signals 45 50 55 %VREG
fLF_BPF_REC Bandpass filter lower cutoff frequency(1) 430 600 760 kHz
fUF_BPF_REC Bandpass filter upper cutoff frequency(1) 12 20 26 MHz
fLPF_REC Low pass filter (after demodulation) 65 100 125 kHz
VN_DIFF_REC
Amplitude of differential noise on input
rejected by receive path for fundamental
frequency between 10KHz to 20KHz
Differential input signal
>20mVpp, VCC=5V,
Sqaure wave noise signal
ramp time = 8µs
1
Vpp
VN_COM_REC
Amplitude of common mode noise on
input rejected by receive path for
fundamental frequency between 10KHz to
20KHz
Differential input signal
>20mVpp, VCC=5V,
Sqaure wave noise signal
ramp time = 8µs
1
RPU_INxN Internal pull up resistor to VREG on each
of the INxN pins 0.8 1 1.2
MΩ
RPD_INxP Internal pull down resistor to GND on
each of the INxP pins 0.8 1 1.2
LREC Typical Receiver coil inductance
(Information only) 0.2 μH
RREC Typical Receiver coil resistance
(Information only) 6 Ω
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over operating free-air temperature range (unless otherwise noted)
over recommended Vcc range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Automatic Gain Control
VAGC_EN_AUTO Voltage on AGC_EN pin to set AGC in
auto mode 2
%VREG
VAGC_EN_MANUAL Voltage range on AGC_EN pin to
manually set different AGC gains 4.55 95.45
RAGC_EN_MIN
Minimum value of required external
resistor on AGC_EN to ground to enable
AGC mode (Information Only)
1 KΩ
RAGC_EN_MAX
Maximum value of required external
resistor on AGC_EN to ground to enable
AGC mode (Information Only)
16.3 KΩ
RPU_AGC_EN Internal pull up resistor to VREG on
AGC_EN 0.8 1 1.2 MΩ
AGC_Target(4) Value of √(OUT02 + OUT12)
VCC = VCC_33; TA=25°C 54.5 59.5 64.5
%VCC
VCC = VCC_33;
-40°C≤TA≤160°C 53.5 65
VCC = VCC_50; TA=25°C 55 60 65
VCC = VCC_50;
-40°C≤TA≤160°C 54 66
AGC_FH Automatic gain control - fast regulation
region high threshold.
VCC = VCC_33; TA=25°C 75.5 78.9 83
%VCC
VCC = VCC_33;
-40°C≤TA≤160°C 75 83.5
VCC = VCC_50; TA=25°C 77 80.1 84
VCC = VCC_50;
-40°C≤TA≤160°C 76 85
AGC_SH Automatic gain control - slow regulation
region high threshold.
VCC = VCC_33; TA=25°C 66 68.8 73.5
%VCC
VCC = VCC_33;
-40°C≤TA≤160°C 65.5 74
VCC = VCC_50; TA=25°C 67 70 74
VCC = VCC_50;
-40°C≤TA≤160°C 66.5 74.8
AGC_SL Automatic gain control - slow regulation
region low threshold.
VCC = VCC_33; TA=25°C 45 48.6 52
%VCC
VCC = VCC_33;
-40°C≤TA≤160°C 44.5 52.5
VCC = VCC_50; TA=25°C 46.5 49.8 53
VCC = VCC_50;
-40°C≤TA≤160°C 46 53.5
AGC_FL Automatic gain control - fast regulation
region low threshold.
VCC = VCC_33; TA=25°C 34.5 38.3 42.5
%VCC
VCC = VCC_33;
-40°C≤TA≤160°C 34 43
VCC = VCC_50; TA=25°C 36.7 39.9 42.7
VCC = VCC_50;
-40°C≤TA≤160°C 36 43.5
Output Stage
VOUT Output signal range OUTxy pins single-ended
measurement 7 93 %VCC
VREF_OUT Output reference voltage 48 50 52
IILIM_OUT Current limit source or sink on output pins 3 20 mA
IOUT Load current on output pins 1.5
RPD_OUT
Allowed range for resistor on OUT pins
to GND for output pins during a detected
fault condition. Refer to VOUT_FLT_LOW for
error band
4 20
kΩ
RPU_OUT
Allowed range for resistor on OUT pins to
VCC for output pin during a detected fault
condition. Refer to VOUT_FLT_HIGH for error
band
4 20
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over operating free-air temperature range (unless otherwise noted)
over recommended Vcc range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
COUT Capacitors on OUT pins (Information
Only)
RPD_OUT = RPU_OUT =
10kΩ, 8kHz rotation speed 1 8
nF
COUT Capacitors on OUT pins (Information
Only)
Maximum rotational speed
limited 8 200
ISCB_OUT Short circuit current into OUT pins when
shorted to voltage higher than VCC VOUT>8V; VCC=5V 5 mA
IOUT_NOVCC_DIFF
Leakage current in to each OUT pin when
VCC is lost; Outputs used in differential
mode.
VCC pin open; RPU_OUT
=5K on each OUTx pin;
VCC=3.3V
12
µA
VCC pin open; RPU_OUT
=5K on each OUTx pin;
VCC=5.0V
25
IOUT_NOVCC_SE
Leakage current in to each OUT pin when
VCC is lost; Outputs used in single-ended
mode.
VCC pin open; RPU_OUT
=5K on each OUTxP pins;
VCC=3.3V
17
VCC pin open; RPU_OUT
=5K on each OUTxP pins;
VCC=5.0V
35
IOUT_NOGND_DIFF
Leakage current out of each OUT pin
when GND is lost; Outputs used in
differential mode.
GND pin open; RPD_OUT
= 5K on each OUTx pin;
VCC=3.3V
30
µA
GND open; RPD_OUT =
5K on each OUTx pin;
VCC=5.0V
50
IOUT_NOGND_SE
Leakage current out of each OUT pin
when GND is lost; Outputs used in single-
ended mode.
GND pin open; RPD_OUT =
5K on each OUTxP pin;
VCC=3.3V
35
GND pin open; RPD_OUT =
5K on each OUTxP pin;
VCC=5.0V
60
VOUT_FLT_LOW
Voltage on OUT pins in fault state with
external pulldown resistors to ground on
OUT pins
4KΩ ≤ RPD_OUT ≤ 20KΩ
on each OUTx pin;
VCC=3.3V;5.0V;
-40°C ≤ TA ≤ 160°C
4 %VCC
VOUT_FLT_HIGH
Voltage on OUT pins in fault state with
external pullup resistors to VCC on OUT
pins
4KΩ ≤ RPU_OUT ≤ 5KΩ on
each OUTx pin; VCC=3.3V;
-40°C ≤ TA ≤ 160°C
96
%VCC
4KΩ ≤ RPU_OUT ≤ 10KΩ on
each OUTx pin; VCC=5.0V;
-40°C ≤ TA ≤ 160°C
96
IOUT_LK_PU (2)
Leakge current on OUT pins in fault state
with external pullup resistors to VCC on
OUT pins when VOUTx > VOUT_FLT_HIGH
5KΩ ≤ RPU_OUT ≤ 20KΩ on
each OUTx pin; VCC=3.3V;
-40°C ≤ TA ≤ 160°C
30
µA
10KΩ ≤ RPU_OUT ≤ 20KΩ
on each OUTx pin;
VCC=5.0V;
-40°C ≤ TA ≤ 160°C
20
(1) Guaranteed by design
(2) Not tested in production
(3) This INL error is not same as INL error in calculated angle in the external MCU
(4) (AGC_SH-AGC_TARGET) and (AGC_TARGET-AGC_SL) ≥ 3% across temperature and allowed VCC range
7.6 Diagnostics
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IPD_INxN_BIST Pull down current to GND during startup
on INxN pins for sensor BIST 150 200 270
μA
IPU_INxP_BIST Pull up current from VREG during startup
on INxP pins for sensor BIST 150 200 270
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over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VTH_FALL_INxP_BIST Falling threshold of window comparator
for sensor BIST on INxP pins 22.7 25 30
%VREG
VTH_FALL_INxN_BIST Falling threshold of window comparator
for sensor BIST on INxN pins 70 75 77.3
IPU_AGC_EN_BIST
Pull up current from VREG during startup
BIST on AGC_EN pin to check short to
ground
200 250 350 μA
VUVUTH_VCC VCC under voltage upper threshold(1) 4.5
V
VUVLTH_VCC VCC under voltage lower threshold(1) 3.6
VOVUTH_VCC VCC over voltage upper threshold 6.5
VOVLTH_VCC VCC over voltage lower threshold 5.6
CLOSS_VREG
VREG external capacitor loss check.
Capacitor values below this will trigger a
fault.
5V VCC mode only 1 nF
VOVUTH_VREG (3) VREG overvoltage upper threshold 4.2 V
VOVLTH_VREG VREG overvoltage lower threshold 3.6
VPOR_VREG_uth VREG power-on upper threshold 3.15 V
VPOR_VREG_lth VREG power-on lower thershold 2.91
fFLTH_LC LC oscillator frequency too high fault
detection 5.3 6.2
MHz
fFLTL_LC LC oscillator frequency too low fault
detection 2.0 2.4
IPU_LCx_BIST Pull up current from VREG during startup
on LCOUT and LCIN pins for sensor BIST 1.7 2.6 4.0
mA
IPD_LCx_BIST Pull down current to GND during startup
on LCOUT and LCIN pins for sensor BIST 1.7 2.6 4.0
tMIN_PH_IMB
Minimum time between zero crossing
of sine output and the following zero
crossing of cosine output and vice versa
to not signal a phase imbalance fault(2).
8.5 10 11.5 μs
VALAGC_INP_OOR_L
AGC quantized step out of 256 (min to
max gain) in auto gaib mode to signal
FAULT when input signal is very low
amplitude
251
AGC code
VALAGC_INP_OOR_H
AGC quantized step out of 256 (min to
max gain) in auto gain modet o signal
FAULT when input signal is very high
amplitude
4
VOOR_H_INx_PIN Out of range single ended fault threshold
voltage for each IN pin - High 70 75 77.3 %VREG
VOOR_L_INx_PIN Out of range single ended fault threshold
voltage for each IN pin - Low 22.7 25 30 %VREG
VOOR_H_INx_LPF Out of range single ended fault threshold
voltage at low pass filter output - High 87.5 92.5 98 %VREG
VOOR_L_INx_LPF Out of range single ended fault threshold
voltage at low pass filter output - Low 1 7.5 12 %VREG
VOOR_H_OUTx_PIN Out of range single ended fault threshold
voltage for each OUT pin - High 93 95 97 %VCC
VOOR_L_OUTx_PIN Out of range single ended fault threshold
voltage for each OUT pin - Low 3 5 7 %VCC
VCM_H_OUTx_PIN Deviation of output common mode above
VREF_OUT to trigger a FAULT 0.8 10 %VCC
VCM_L_OUTx_PIN Deviation of output common mode below
VREF_OUT to trigger a FAULT 0.8 10 %VCC
VOUTx_SHRT_P_CMP_OFF
Offset between internal AGC diffrential
output value and OUTxP differential value
before short between OUTxP pins is
detected.
+100 +250 +440 mV
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over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOUTx_SHRT_N_CMP_OFF
Offset between internal AGC diffrential
output value and OUTxN differential value
before short between OUTxN pins is
detected.
-380 -250 -100 mV
VUV_DVDD Internal Digital Supply undervoltage
check. 1.2 1.3 V
VTOGGLE_AGC_EN
Checks if the comparator on
AGC_EN toggles after AGC_EN status
determination
50 200 mV
TTSD_rise Abmient temperature above which thermal
shutdown fault is triggered. 190 ℃
TTSD_fall Abmient temperature below which thermal
shutdown fault is cleared 160 ℃
(1) Continuously checked in VCC = 5V mode. Ignored in VCC=VREG=3.3V mode
(2) Fault is signaled only at occurance of 3 consecutive violations of the minimum time.
(3) Device will continue normal operation until the over-voltage threshold on VREG triggered
7.7 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tVCC_FLT_DT Deglitch time for VCC over voltage and
under voltage detection 180 200 220 µs
tVREG_OV_DT Deglitch time for VREG over voltage
detection 180 200 220 µs
tLC_FLT_DT Deglitch times for LC amplitude related
faults 180 200 220 µs
tAGC_EN_DT Deglitch time for AGC_EN pin for AGC
mode detection 2.7 3 3.3 µs
tAGC_EN_TGL_DT Deglitch time on AGC_EN pin toggle fault
after power up into normal state 450 500 550 µs
tIN_OOR_DT Deglitch time applied to each input out of
range signal individually 180 200 220 µs
tINx_FLT_DT
Deglitch time applied to the fault signal
determined by OR of all individual input
out of range faults which are deglitched
for tIN_OOR_DT
180 200 220 µs
tLPF_OOR_DT Deglitch time for AFE Low Pass Filter Out
of Range check 180 200 220 µs
tOUT_OOR_DT Deglitch time for output voltage out of
range fault. 180 200 220 µs
tOUTx_SHORT_DT Degltich time for AFE Output Short
detection 450 500 550 µs
tOUT_CM_DT Deglitch time for OUT pin common mode
check 90 100 110 µs
tOUT_ZC_DT Deglitch time for OUT differential output
zero crossing fault detection 9 10 11 µs
tAGC_ZC_DT Deglitch time for AGC differential output
zero crossing fault detection 9 10 11 µs
tAGC_CMP_DT
Deglitch time to detect AGC fast/slow
amplitude regulation threshold has been
crossed
180 200 220 ns
tAGC_VAL_DT Deglitch time for AGC OOR range faults 180 200 220 µs
tFLT_RECOV
Fault recovery time once device
tranistions from FAULT to DIAGNOSTIC
state
CEXT_VREG=680nF, 2.2µF 12 16 ms
tPWR_ON From VREG power on until OUTx pins are
released from HI-Z state. CEXT_VREG=680nF, 2.2µF 10 14 ms
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over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPRWR_ON_DT Deglitch time after tPWR_ON for which
OUTx faults are ignored. 302 336 370 µs
7.8 Typical Characteristics
Rotation Frequency (Hz)
Angle Error in Degrees
1000 2000 3000 4000 5000 6000 7000 8000
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
VCC = 5V, LCfreq=5MHz, Ideal Inputs, No offset and gain correction
Signal path delay compensated
-40qC
10nF
-40qC
49nF
25qC
10nF
25qC
49nF
125qC
10nF
125qC
49nF
170qC
10nF
170qC
49nF
Figure 7-1. Angle Error VCC = 5 V, COUT < 50 nF
Rotation Frequency (Hz)
Angle Error in Degrees
1000 2000 3000 4000 5000 6000 7000 8000
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
VCC = 5V, LCfreq=5MHz, Ideal Inputs, With offset and gain correction
Signal path delay compensated
-40qC
10nF
-40qC
49nF
25qC
10nF
25qC
49nF
125qC
10nF
125qC
49nF
170qC
10nF
170qC
49nF
Figure 7-2. Angle Error VCC = 5 V, COUT < 50 nF
Rotation Frequency (Hz)
Angle Error in Degrees
1000 2000 3000 4000 5000 6000 7000 8000
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2
VCC = 3.3V, LCfreq=5MHz, Ideal Inputs, No offset and gain correction
Signal path delay compensated
-40qC
10nF
-40qC
49nF
25qC
10nF
25qC
49nF
125qC
10nF
125qC
49nF
170qC
10nF
170qC
49nF
Figure 7-3. Angle Error VCC = 3.3 V, COUT < 50 nF
Rotation Frequency (Hz)
Angle Error in Degrees
1000 2000 3000 4000 5000 6000 7000 8000
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
VCC = 3.3V, LCfreq=5MHz, Ideal Inputs, With offset and gain correction
Signal path delay compensated
-40qC
10nF
-40qC
49nF
25qC
10nF
25qC
49nF
125qC
10nF
125qC
49nF
170qC
10nF
170qC
49nF
Figure 7-4. Angle Error VCC = 3.3 V, COUT < 50 nF
Rotation Frequency (Hz)
Angle Error in Degrees
1000 2000 3000 4000 5000 6000 7000 8000
0
1
2
3
4
5
6
7
8
9
VCC = 5V, LCfreq=5MHz, Ideal Inputs, With offset and gain correction
Signal path delay compensated
-40qC
149nF
-40qC
230nF
25qC
149nF
25qC
230nF
125qC
149nF
125qC
230nF
170qC
149nF
170qC
230nF
Figure 7-5. Angle Error VCC = 5 V, COUT > 100 nF
R Pull-up to VCC (K:)
Leakage Current in PA
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
5
7.5
10
12.5
15
17.5
20
22.5
25
27.5
30
32.5
35
37.5
40
-40.00qC
VCC=3.3V
-40.00qC
VCC=5.0V
25.00qC
VCC=3.3V
25.00qC
VCC=5.0V
170.00qC
VCC=3.3V
170.00qC
VCC=5.0V
Figure 7-6. OUTx Pin Leakage Current When Device is in a
SAFE State and Output Pulled to VCC With R Pull-up
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8 Detailed Description
8.1 Overview
The LDC5072-Q1 is an inductive position sensor front-end IC for use in automotive and industrial applications.
The sensor typically consists of an excitation coil and a set of two receiver coils, all drawn on the same PCB.
The sensor also has a metal target which is typically printed on another PCB. The coil PCB is mounted in a fixed
position on the motor and the metal target is mounted on a rotating shaft. The device excites the excitation coil,
which then couples to the receiver coils. The amount of coupling from the excitation to receiver coils depends on
the relative position of the metal target to the receiver coils and also on the air gap between the coil PCB and the
target. The LDC5072-Q1 has an LC oscillator driver that can drive an excitation coil with a constant amplitude
and supports a wide range of LC combinations.
Two receiver coils are placed such that the LDC5072-Q1 outputs are shifted by 90°. These Sine and Cosine
outputs are ratiometric to each other and can be used to calculate the angle at any given instant. The LDC5072-
Q1 receiver filters out the out-of-band noise, demodulates, and amplifies the signal. The device has a gain block
that can be either set manually or in automatic mode. In automatic mode, the LDC5072-Q1 will regulate output
amplitude to a fixed band, which can remove sensor variability such as the lifetime variation of air gap. The
device has two differential output drivers that can drive a wide range of capacitive loads. Typically these are
digitized by an ADC of an MCU for further angle calculation, for motor control, or for linear position information
extraction.
Figure 8-1. LDC5072-Q1 Typical Output
The LDC5072-Q1 was developed in accordance with ISO 26262 to support functional safety. The device
implements a pin-level built-in self-test at power up to check for sensor pins open, shorts to supplies, and short
between the coils. The device also has analog and digital built-in self-test to test internal safety mechanisms.
The LDC5072-Q1 also implements run-time checks to continuously monitor sensor functionality. In an event that
a fault is detected, the output drivers are driven to high-impedance state.
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8.2 Functional Block Diagram
LDO Regulator &
Protection
Diagnostics
LCOUT
LCIN
VCC
OUT0P
OUT0N
OUT1P
OUT1N
GND
Diagnostics
Diag
Output
AGC_EN
Excitation Signal
Fault Detection
State Machine
Digital
TOUT
VREG
IN0P
IN0N
IN1P
IN1N
Diag
Signal Processing
Diagnostics
+
-
+
-
Protection
LC Oscillator
Vref
AGC
Analog Front End
Copyright © 2018, Texas Instruments Incorporated
TM0
Oscillator
Diag
8.3 Feature Description
8.3.1 Input Supply Voltage
The main voltage supply for this device is on the VCC pin. The VCC pin can be supplied either by a 3.3-V
or 5-V regulator. This pin is protected internally from possible negative voltages on the pin and from possible
back-feeding of current from the device to the regulator. The pin can also withstand voltages as high as 30 V. For
3.3-V mode, the VREG and VCC pins are shorted together on the PCB.
There is an internal 3.3-V regulator with a capacitor on the VREG pin. This regulator is the supply for all internal
blocks, the LC oscillator, and the regulator is also used as a reference block for various sections of the signal
chain. Additionally, an internal 1.5-V regulator supplies the digital logic. This device has two modes of operation:
a 5-V supply mode and a 3.3-V supply mode. For 5-V supply mode, 5 V is required on the VCC pin that the
internal regulator will use to generate voltage on VREG. For 3.3-V supply mode, the VREG and VCC pins must
be connected externally and supplied with regulated 3.3 V. This will change the common-mode voltage on the
device outputs, because this voltage is derived from half the value on the VCC pin. The device includes an
automatic check to figure out which mode the device is in during power up.
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8.3.2 Excitation Signal
The excitation signal is generated by an LC oscillator. The LCIN and LCOUT pins will be connected to the
excitation coil. The oscillator signal driver automatically regulates the signal to VAMP_LC. The user can adjust the
external capacitors on LCIN and LCOUT to select the excitation frequency. For best performance, two capacitors
should be used. One should be placed from LCIN to ground and the other from LCOUT to ground (C1 and C2).
This is instead of using one capacitor between LCIN and LCOUT.
Use Equation 1 to calculate the excitation frequency.
OSC _ LC
1 2
1 2
1
f
C C
2 L C C
§ ·
§ ·
u
S u u
¨ ¸
¨ ¸
¨ ¸
¨ ¸

© ¹
© ¹
(1)
where
• L is inductance of excitation coil
• C1, C2 are the external capacitors on LCIN and LCOUT, respectively
8.3.3 Signal Processing Block
The inputs to the signal processing block come from the outputs of the receiver coils of the position sensor.
This block will demodulate the position signals, filter out noise, and amplify the signal in preparation for angle
calculation by an external control unit. The first stage of the signal processing block contains ESD protection
circuitry and sets the common-mode voltage. The second stage of this block is an EMC filter to eliminate noise.
The next stage of this block is a demodulator for the input signals. This demodulation uses the frequency of the
LC oscillator as a reference. The signals will then go through a low-pass filter with fixed gain. The last stage
in the signal processing block is a gain stage where the gain is either set by an automatic gain control routine
(AGC_EN pin pulled to GND through an external resistor), or set to a fixed gain by the voltage on the AGC_EN
pin. The signal path gain for both channels is same and are matched very closely by careful design.
Figure 8-2 shows a block diagram of the analog front-end in the IC that demodulates the incoming signal to
extract position information.
IN0P
IN0N
OUT0P
OUT0N
BPF
EMC & NOISE
BandPass filter
LPF
w/ GAIN
LowPass filter
AGC
Variable Gain stage
IN1P
IN1N
OUT1P
OUT1N
LPF
w/ GAIN
LowPass filter
AGC
Variable Gain stage
LO OSCILLATOR AGC CONTROL
DEMOD
DEMOD
CM BIAS & ESDCM BIAS & ESD
OUTPUT DRIVER
w/ OV PROTECTION
OUTPUT DRIVER
w/ OV PROTECTION
BPF
EMC & NOISE
BandPass filter
AFE
AFE
Figure 8-2. Signal Processing Block Diagram
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8.3.3.1 Demodulation
The receive path for the sine path can be modeled by Equation 2 through Equation 5.
 
 
sin AMP _ LC OSC _ LC
RXi V sin 2 f t sinu K u u S u u u 4
(2)
where
• RXisin: Receiver path sine coil input
• VAMP_LC: LC oscillator signal amplitude
• η: Coupling factor between exciter and receive coil
• fOSC_LC: LC oscillator excitation frequency
• Θ: Instantaneous motor angle
 
 
 
u u u K u 4 u u  u S u u
sin MIXER BPF AMP _ LC OSC _ LC
1
Demod G G V sin 1 sin 2 f t
2
(3)
where
• Demodsin: Demodulator sine path output
• VAMP_LC: LC oscillator signal amplitude
• η: Coupling factor between exciter and receive coil
• fOSC_LC: LC oscillator excitation frequency
• Θ: Instantaneous motor angle
• GMIXER: gain due to the mixer
• GBPF: gain due to the bandpass filter
 
u u u u u K u 4
sin MIXER BPF LPF AMP _ LC
1
LPF G G G V sin
2
(4)
where
• LPFsin: Low pass filter sine path output
• VAMP_LC: LC oscillator signal amplitude
• η: Coupling factor between exciter and receive coil
• Θ: Instantaneous motor angle
• GMIXER: gain due to the mixer
• GBPF: gain due to the bandpass filter
• GLPF: gain due to the lowpass filter
 
OUT _ SIN AMP _ LC
1
V G V sin
2
u u u K u 4
(5)
where
• Voutsin: Signal output at the end of sine path
• VAMP_LC: LC oscillator signal amplitude
• η: Coupling factor between exciter and receive coil
• Θ: Instantaneous motor angle
• G: Total combined gain of the signal path
The cosine path can be modeled in the same way as sine path.
The total gain of the system is a combination of the gain control, mixer gain, and fixed gain. It can be modeled by
Equation 6:
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FIXED MIXER GC
G G G Gu u
(6)
where
• GFIXED is the fixed gain in the signal path, including GLPF and GBPF
– GFIXED = 43.2 for VCC = 5 V
– GFIXED = 28.8 for VCC = 3.3 V
• GMIXER is the gain due to the mixer. The typical value is 0.637.
• GGC is the variable gain in the signal path. This is either selected by the AGC or the Fixed Gain Control
depending on the voltage on the AGC_EN pin.
8.3.3.2 Fixed Gain Control
To set the gain of the final gain stage, a voltage in the range of VAGC_EN_MANUAL must be applied to the AGC_EN
pin. This gain setting will be set during the DIAGNOSTICS state. A change in the voltage on AGC_EN affects the
AGC gain the next time the device enters the DIAGNOSTICS state, either during the next power up of the device
or during fault recovery. The nominal value of minimum gain of this stage is 0.375 and the maximum gain is
60.375. The gain is implemented as linear in dB scale with 256 steps. This gain is rotation frequency dependent.
For higher rotation speeds, the gain value will fall off. Equation 7 shows the gain in linear scale is related to the
voltage on AGC_EN pin as a percentage of VREG:
%V Re g 4.55
1.903 90.9
Gain 0.375 0.759 10 1
§ ·

§ ·
u
¨ ¸
¨ ¸
© ¹
© ¹
§ ·
¨ ¸
 u 
¨ ¸
¨ ¸
© ¹
(7)
where
• Gain is the effective gain set by gain control block.
• %VREG is the voltage on AGC_EN pin expressed as percentage of voltage on the VREG pin.
The voltage applied on AGC_EN pin should fall within VAGC_EN_MANUAL range.
8.3.3.3 Automatic Gain Control
When the voltage on the AGC_EN pin is below VAGC_EN_AUTO, the manual gain control function is disabled and
the Automatic Gain Control (AGC) is enabled.
In AGC mode, the device will change the gain of the last stage of the signal processing block to keep the
final output within an appropriate voltage range on VOUT. The AGC block uses the square root of the sum of
the squared amplitudes of the two channels to sense amplitude of output signals and set gain selection. Both
channels will have the same gain. This means that the AGC block will set the gain for sine and cosine channels
such that the quantity AGC_TARGET as defined in Equation 8 is within the ranges listed in Specifications.
   
2 2
OUT1P OUT1N OUT0P OUT0N
RADIUS
VCC
  
(8)
where
• OUTxx: Voltage on the output pins
• VCC: Voltage on the VCC pin
• AGC_TARGET: Regulation target for the AGC block
The AGC sets the gain in the DIAGNOSTICS state and then dynamically regulates it in NORMAL state. There
are two regions of regulation, the slow AGC regulation region and the fast AGC regulation region. This is shown
in Figure 8-3. The blue curve shows the ratio defined by Equation 8 as percentage of VCC. If the ratio rises
above AGC_FH or falls below AGC_FL, fast regulation becomes active, and the gain is changed by four gain
codes every nominal value of 819.2 μs. If the ratio falls between AGC_SH and AGC_FH, or between AGC_FL
and AGC_SL, slow regulation is active, and the gain is changed by one code approximately every 840mS. To
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allow for faster settling of the output during power up in diagnostic state, the device changes gain by one code
every 3.2 μs in slow AGC region and eight codes every 3.2 μs in the fast AGC region. The thresholds are listed
in Specifications. The gain step size is constant in dB scale and is approximately equal to 0.15 dB. Figure 8-3
shows the two cases: a fast change (for example, due to a transient), and a slow change due to lifetime drift.
The AGC block thus will try to compensate for changes in amplitude of the input signal or changes in VCC. If the
ratio, after reaching AGC_TARGET, stays between AGC_SH and AGC_SL, then AGC does not react and does
not change the gain. The AGC block engages if one of the thresholds is crossed, and it will try to change the
output amplitudes such that the ratio reaches AGC_TARGET again. Hence, the No Gain Control region in Figure
8-3 causes the AGC block to have some hysteresis.
t
%VCC
Fast AGC
Slow AGC
Slow AGC
AGC_SH
AGC_TARGET
AGC_FH
AGC_SL
Fast AGC
AGC_FL
No Gain Control
Fast
Change
Lifetime
Drift
Figure 8-3. AGC Regulation Bands
8.3.4 Output Stage
The output stage consists of buffers that drive each of the outputs differentially and maintain the output common
mode at VREF_OUT as specified in Specifications. There are two output stages, one at the OUT0x pins and the
other at the OUT1x pins, and each drive the pins in a push-pull manner. For a rotating input, one set of pins
will represent the sine angle information and other set will represent cosine angle information. The output stages
buffer the AGC output and outputs the final demodulated position information to be used by a microcontroller.
The output stage is designed such that it can drive a large range of capacitive loads.
The output stage requires external capacitors as specified by COUT and pullup or pulldown resistors as specified
by RPD_OUT and RPU_OUT. The OUTx pins enter a high impedance state in the case of a fault, so the pullup and
pulldown resistors are used to pull the voltage out of range for detection by the MCU. See External Diagnostics
Required for Loss of VCC or GND for details about external diagnostics required for loss of VCC or GND
conditions.
There is a possibility that wires connecting to OUT0 and OUT1 pins can be routed outside the sensor module,
so the output stage has both negative and high voltage protection to prevent the part from getting damaged in
the event of shorts. The output stage also has out-of-range fault detection. The diagnostic coverage on output
stage will also check if the output signal is being driven outside of the maximum allowable limit as defined
in Specifications as shown in Figure 8-4. In the event of a fault, the output stages are put in Hi-Z mode and
external pullup and pulldown resistors will drive OUTx pins to maximum and minimum signaling a fault to the
microcontroller. See Diagnostics for details.
xxxxxxxx
xxxxxxxx
FAULT
xxxxxxxx
FAULT
t
VOUT OOR+ ±95%
%VCC
VOUT OOR- ±5%
VOUT_CM
OUT0P OUT1P
OUT0N OUT1N
Figure 8-4. Out of Operation Fault Detection Range at the Output
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Note
The voltage at the OUTx pins is not ratiometric to VCC. In AGC mode, the calculated RADIUS in
Equation 8 value will change. Only if it crosses one of the threshold (depending on change magnitude
of VCC), then the gain of AGC will be adjusted accordingly to bring the RADIUS value back to
AGC_TARGET. In fixed-gain mode, the gain will not be adjusted even if VCC change by large
magnitude.
8.3.5 Diagnostics
The LDC5072-Q1 is equipped with numerous diagnostics features to detect, monitor, and report failures that
either existed before the power up or occurred during device operation. In the event of a failure, the LDC5072-
Q1 is placed either in IDLE, DISABLED, or FAULT state (based on the failure nature), the LC Oscillator is
turned off, the AFE is disabled, and the output pins are tri-stated, and consequently, are pulled up or down by
external resistors. From the FAULT state, the LDC5072-Q1 returns to DIAGNOSTICS state if the fault condition
is removed. From the DISABLED state, the LDC5072-Q1 is moved to IDLE state after a Power Cycle (see
Device Functional Modes).
The LDC5072-Q1 tri-states its output to signal a fault. As shown in Application and Implementation, it is
expected that a combination of pullup or pulldown resistors are added on OUTx pins at the termination site (that
is, at the microcontroller). The values of these resistors are specified as RPU_OUT and RPD_OUT in Specifications.
The resistors are generally pulled up to a supply (typically VCC) and pulled down to ground such that the ADC
code on the MCU is out of the expected range. This will signal a fault to the microcontroller.
8.3.5.1 Undervoltage Diagnostics
The LDC5072-Q1 continuously monitors the VREG and DVDD voltage while in DIAGNOSTICS, NORMAL,
FAULT, and DISABLED states. If the VREG or DVDD drops below the specified limits (see Electrical
Characteristics ), the LC Oscillator is turned off, the AFE is disabled, and the output pins are tri-stated if neither
were done so yet. Upon voltage recovery, the device transitions to the IDLE state and initiates regular Power-On
Reset.
8.3.5.2 Initialization Diagnostics
During power up in the DIAGNOSTICS state, the LDC5072-Q1 undergoes a number of self-diagnostics and
checks (for fault thresholds refer to Diagnostics and for de-glitch times refer to Switching Characteristics ):
1. EEPROM CRC check: the LDC5072-Q1 calculates the CRC value of the EEPROM register settings and
compares it to the recorded expected CRC value. In case of FAULT, the LDC5072-Q1 transitions to the
DISABLED state.
2. LBIST check: the LDC5072-Q1 undergoes automated self-testing pattern for the digital logic. In case of
FAULT, the LDC5072-Q1 transitions to the DISABLED state.
3. ABIST check: the LDC5072-Q1 undergoes automated self-testing pattern for the fault-monitoring circuits. In
case of FAULT, the LDC5072-Q1 transitions to the DISABLED state.
4. Sensor interface BIST check: the LDC5072-Q1 applies the automated test patterns to Sensor interface
(LCIN, LCOUT, IN0P, IN0N, IN1P, and IN1N) pins to check that they are open or shorted to GND or battery.
It also checks if there is a short between the coils of the sensor and if any of the coils are open. The
LDC5072-Q1 will also check if any impedance is present as specified by the RAGC_EN_AUTO or RPU_AGC_EN
on the AGC_EN pin and check if the AGC_EN pin is not shorted to GND.
5. VREG cap loss check: the LDC5072-Q1 uses the VREG cap to compare the internal time constant with the
external time constant (5-V VCC mode only). This check is only performed at power up and is not performed
if the device transitions from FAULT state to DIAGNOSTICS state. The maximum capacitance on VREG pin
that can trigger this fault is given by CLOSS_VREG.
6. The LDC5072-Q1 enables the LC oscillator and checks that VUVL_AMP_LC, VOVH_AMP_LC, VUVL_CM_LC, and
VOVH_CM_LC faults disappear within tLC_FLT_DT.
7. The LDC5072-Q1 enables the AFE, AGC, and Output stages in a staggered manner.
8. The LDC5072-Q1 the device resets all checks and faults for certain period of time to allow all internal signals
to settle and then starts monitor faults
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