Texas Instruments TIDM-1011 Guide

Design Guide: TIDM-1011
Tamagawa T-Format Absolute-Encoder Master Interface
Reference Design for C2000™ MCUs
Description
C2000™ microcontroller (MCU) Position Manager
technology offers an integrated solution to interface to
the most popular digital- and analog-position sensors,
which eliminates the necessity for external field-
programmable gate arrays (FPGAs) or application-
specific integrated circuits (ASICs). The Position
Manager BoosterPack™ is a flexible, cost-effective
platform intended for evaluating various encoder
interfaces and is designed to work with multiple
C2000 MCU LaunchPad™ development kits. The
software of this reference design specifically targets
implementation of the T-Format, which is a digital,
bidirectional interface for position encoders. The
highly optimized and easy-to-use software reference
implementation and examples included in this
reference design enable T-Format, position-encoder
operation using the Position Manager BoosterPack.
Resources
TIDM-1011 Design Folder
LAUNCHXL-F28379D
LAUNCHXL-F280039C
LAUNCHXL-F280049C
LAUNCHXL-F280025C
Tools Folder
SN65HVD78, TLV702, TPS22918-Q1 Product Folder
C2000WARE-MOTORCONTROL-SDK Tools Folder
Ask our TI E2E™ support experts
Features
• Flexible, low-voltage, BoosterPack evaluation
platform for position-encoder interfaces
• Integrated MCU solution for T-Format encoder
interface without additional FPGA requirements
• Easy interface T-Format commands through driver
functions and data structure provided by interface
function
• Support for unpacking received data and optimized
cyclic redundancy check (CRC) algorithm
• Supports a clock frequency of 2.5 MBPS and
verified operation up to 100-m cable length
• Includes evaluation software example showcasing
the T-Format implementation
Applications
•Industrial
•Motor Drives
TMS320F28379x
T-Format Master
Encoder
Supply
RS485
RS485
Connector
Connector
Motor Tamagawa
Absolute Position Encoder
Shielded Cable
DATA+
DATA–
Power
Ground
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1 System Description
Industrial drives, like servo drives, require accurate, highly-reliable, and low-latency position feedback. The T-
Format protocol, from Tamagawa, is designed for serial transfer of digital data between a sensor and a controller.
The sensor can be an encoder (linear, rotary, or angle), a touch probe, or an accelerometer. The subsequent
electronics, or controller, includes numerical controls, servo amplifiers, and programmable-logic controllers.
The TIDM-1011 design implements a T-Format encoder interface to a C2000 LaunchPad. T-Format is a pure-
serial, digital interface, based on the RS-485 standard. T-Format is capable of transmitting position values,
along with other physical quantities, and allows reading and writing of the internal memory of the encoder. The
transmitted-data types include absolute position, turns, temperature, parameters, and diagnostics. Commands
transmitted to the encoder from the interface select the response-data types.
Figure 1-1 shows a T-format encoder connected to a BOOSTXL_POSMGR plus F28379D LaunchPad encoder
interface.
TMS320F28379x
T-Format Master
Encoder
Supply
RS485
RS485
Connector
Connector
Motor Tamagawa
Absolute Position Encoder
Shielded Cable
DATA+
DATA–
Power
Ground
Figure 1-1. Industrial Servo Drive With T-Format Position Encoder Interface
The position encoder with T-Format connects to the TIDM-1011 device through a single, 4-wire, shielded cable.
RS-485 is used as the physical layer for T-Format encoders. The four wires used are:
• DATA+ and DATA- : differential signals for communication data
• Power and Ground: encoder power supply and ground
The Texas Instruments C2000 T-Format (PM_tformat) encoder interface implementation enables interfacing a
T-Format encoder to a C2000 device without external hardware such as an FPGA or CPLD. The reference
implementation features:
• 2.5 MBPS clock frequency as required by the T-Format protocol
• Integrated cable-propagation delay compensation to enable variable cable length, verified up to 100 m
• Software driver functions:
– Perform a transaction with the encoder. This consists of sending a request and receiving the response.
– Calculate a CRC
– Compare CRC received with a calculated CRC
– Packing and unpacking the data
This reference implementation includes all the source code. Any changes needed for the implementation can be
made by users as needed by their application.
Note
Only the basic interface drivers for the commands defined in the T-Format specification are provided.
All the higher-level application software must be developed by users using the basic interface
provided by this implementation.
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1.1 Key System Specifications
Table 1-1. Key System Specifications
PARAMETER SPECIFICATIONS DETAILS
Input voltage 5 V(1) Section 3.3.1
Output voltage (encoder) 5 V Section 3.3.1
Protocol supported T-Format Tamagawa
Frequency (encoder interface) Approximately 2.5 MBPS Tamagawa
Encoder bits T-Format protocol standard Tamagawa
CPU cycles C2000 T-Format encoder interface benchmarks Section 3.3.5
(1) The time of the encoder connected to the TIDM-1011 device determines the current limit of this supply. TI recommends a generic,
bench-top, adjustable, power supply with an adjustable current limit.
2 System Overview
The C2000 T-Format TIDM-1011 reference design is a combination of hardware and software. The core
hardware components are a C2000 real-time microcontroller (MCU) and a RS-485 transceiver. The C2000
LaunchPad and the TIDM-1011 boosterPack, which contains the RS-485 transceiver, are the boards used in
this implementation. The C2000 Motor Control SDK package contains the necessary software. This software
includes a library, which implements key T-format interface features, along with a system-level example to
demonstrate T-Format communication.
The T-Format encoder interface leverages the C2000 CLB (Configurable Logic Block) and the SPI (Serial
Peripheral Interface) modules. The CLB controls the SPI clock and compensates for cable propagation delay.
The CLB also controls the RS-485 transceiver transmit enable. The SPI module acts as the send/receive
interface to the RS-485 physical layer. The firmware, which is written in C, runs on the C28x of the C2000 MCU.
The C2000 LaunchPad can provide power for the TIDM-1011 RS-485 transceiver and 5V for the encoder. 5V
can also be supplied separately if the encoder specifications require a higher current than the LaunchPad can
provide.
During start-up, the application running on the C28x initializes the MCU clocks and configures the pin-mux. The
MCU's SPI and CLB are also configured as required to send and receive data.
2.1 Block Diagram
Motor
Secondary:
T-Format
Position Encoder
Connector
M12, 8-Pin
DATA+
DATA–
Power
Ground
8-Wire Cable,
Single Shielded
C2000 LaunchPad
Encoder Power
Enable
(TPS22918)
RS485
(SN65HVD78)
RS485
(SN65HVD78)
5-V IN
(J6)
Power
Supply
(TLV70233)
Abs-Enc1 (J7)
BoosterPack™ Connector
(J1, J3 and J4, J2)
TIDM-1011
BoosterPack
Primary: Encoder Interface and Controller
Figure 2-1. TIDM-1011 System Block Diagram
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2.2 Highlighted Products
The TIDM-1011 reference design hardware consists of a C2000 LaunchPad plus a BOOSTXL-POSMGR
BoosterPack. This section covers the key devices used. For more information on each of these devices, see
their respective product folders at TI.com.
2.2.1 C2000 Real-Time MCU LaunchPad
Multiple LaunchPad kits support the TIDM-1011 reference design (refer to Table 2-1). Each of the C2000
Real-Time Microcontrollers listed in Table 2-1 feature the Configurable Logic Block (CLB). The encoder interface
makes extensive use of the CLB. The CLB peripheral is exclusive to C2000 devices and allows users to
incorporate custom logic without the need for an external FPGA or CLPD. The CLB is composed of submodules
that combine together to enable custom digital logic. Submodules include: Finite State Machines (FSM), Lookup
Tables (LUT), and counters. The CLB also interfaces with existing on-chip control peripherals to enhance
functionality and provide design options.
To learn more about the CLB, visit the C2000 Academy Configurable Logic Block module.
Devices with the CLB include:
•TMS320F28379D MCU:
Provides 800 MIPS of total system performance between dual, 200-MHz, C28x CPUs and dual, 200-MHz,
real-time-control coprocessors (CLA). This powerful MCU contains 1MB of on-board flash and includes
highly-differentiated peripherals, such as 16-bit or 12-bit analog-to-digital converters (ADCs), comparators,
12-bit digital-to-analog converters (DACs), delta-sigma sync filters, HRPWMs, eCAPs, eQEPs, CANs, and
more. Find the full device features and specifications at the TMS320F28379D device product folder.
•TMS320F280039C MCU:
Provides 240 MIPS between a 120 MHz C28x CPU and 120 MHz CLA. This MCU contains up to 384 kB of
on-chip flash and includes 3 12-bit ADCs, enhanced Configurable Logic Blocks (CLB), and more. Find the full
device features and specifications at the TMS320F280039C device product folder.
•Table 2-1 lists other supported devices, their product folders, and their LaunchPad Development Kits.
Table 2-1. Supported Devices and LaunchPads
LaunchPad Development Kit MCU Device Product Folder (2)
LAUNCHXL-F28379D TMS320F28379D
LAUNCHXL-F280049C TMS320F280049C
LAUNCHXL-F280025C TMS320F280025C
LAUNCHXL-F280039C TMS320F280039C
Not Available (1) TMS320F28388D
(1) The TMS320F28388D device family does not have a LaunchPad development kit. You must supply the connections to an
RS-485 physical interface through another means. Options include (1) your own hardware, (2) a controlCard with wires to the
BOOSTXL_POSMGR, or (3) the TMXIDDK379D.
(2) The TIDM-1011 reference design requires a C2000 LaunchPad with an MCU featuring the Configurable Logic Block (CLB) type 1 or
later. Devices supported at the time of this release are shown. Additional devices may be available.
2.2.2 SN65HVD78
The SN65HVD78 device combines a differential driver and a differential receiver, which operate from a single,
3.3-V power supply. The differential outputs of the driver and the differential inputs of the receiver are internally
connected to form a bus port suitable for half-duplex (two-wire bus) communication. These devices feature a
wide, common-mode voltage range, which makes the devices suitable for multipoint applications over long cable
runs.
Find the full device features and specifications at the SN65HVD78 product folder.
2.2.3 TLV702
The TLV702 series of low-dropout (LDO) linear regulators are low-quiescent current devices with excellent line
and load-transient performance. All device versions have thermal shutdown and current limit for safety. The
devices regulate to specified accuracy with no output load.
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Find the full device features and specifications at the TLV702 product folder.
2.2.4 TPS22918-Q1
The TPS22918-Q1 is a single-channel load switch, with configurable rise time and configurable quick-output
discharge. The device contains an N-channel MOSFET that can support a maximum-continuous current of 2 A.
The switch is controlled by an on and off input, which can interface directly with low-voltage control signals.
Find the full device features and specifications at the TPS22918-Q1 product folder.
2.3 Design Considerations
This section provides:
1. Overview of the Tamagawa T-Format protocol.
2. Overview of the C2000 T-Format encoder interface.
3. TIDM-1011 hardware (BOOSTXL-POSMGR BoosterPack) implementation.
4. C2000 MCU implementation, including the required input/output, CRC calculations, and the CLB design.
5. Overview of the C2000 T-Format encoder interface software library.
Note
This section provides implementation details only. For information related to:
• Hardware requirements, setup and testing: Refer to Section 3.
• Software: Installing and running the software: Refer to: "C2000 T-Format Encoder Interface
Software Guide" (html, pdf). The software guide includes documentation for:
– Communication demonstration
– T-Format application programmer interface (API)
– Incorporating the library into your own solution
– Migration from previous versions
2.3.1 Tamagawa T-Format Protocol
Tamagawa is a manufacturer of encoder technology used for obtaining high-precision position information in
machine tools, robotics, motor drives and so forth. Tamagawa rotary encoders consist broadly of two types:
incremental or absolute. Incremental encoders provide a train of pulses, while the absolute-type provides
absolute digital values. Absolute encoders include both single-turn and multi-turn types.
The TIDM-1011 reference design focuses on an absolute-type which provides a digital output through an RS-485
line driver. The protocol format of the transaction supported by TIDM-1011 is known as T-Format.
Note
This section provides an overview of the T-Format protocol. For specific information, refer to the
T-format specification available from Tamagawa.
Note
Not all encoders produced by Tamagawa use the T-Format protocol. Check the specification of your
encoder.
The C2000 T-Format encoder interface provides the required physical layer for a controller to communicate with
an encoder. This encoder interface provides the RS-485 drive control to send and receive digital information with
the encoder. In this context, a T-Format transaction is the transmission of a request from the controller plus the
response back from the encoder. From the perspective of the encoder interface, a transaction can be divided
into FRAME_STATES shown in Figure 2-2:
1. IDLE: No RS-485 activity
2. TRANSMIT_DATA: The controller sends a request to the encoder
3. WAIT_FOR_START: Wait for the encoder's response
4. RECEIVE_DATA: The controller receives the encoder's response
5. Back to IDLE.
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This pattern is repeated for each transaction with the encoder.
WAIT_FOR_START
IDLE
TxEN
Driven by CLB
TRANSMIT_DATA RECEIVE_DATA
SPI SOMI
Request to
Encoder
SPI CLK (2.5 MHz)
Driven by CLB
0 0 1 0
IDLE
START
SINK DATAID + …..
… ...
IDLE
SPI SIMO
Response from
Encoder
… ...
… ...
… ...
0 0 1 0
IDLE
START
SINK
… ...
DATAID + …..
Cable Length DependentCycles are Command Dependent
Command Dependent Data
Command Dependent Response
… ...
… ...
… ...
… ...
Cycles are Command Dependent
FRAME_STATE
Transmit on the Falling Edge of SPICLK
Receive on the Rising Edge of SPICLK
Figure 2-2. T-Format Frame
Note
Figure 2-2 includes information related to the C2000 encoder interface implementation. For example,
the CLB drives the SPI CLOCK and the TxEN signal.
The T-format communication protocol is broadly classified into three types of transactions: data readout, reset,
and EEPROM access. Each transaction has a unique Data ID defined by the protocol. The Data ID is used to
identify the specific request made by the controller through the encoder interface.
Table 2-2. T-Format Transactions
Transaction Type Data ID Transaction
Readout ID 0 Absolute data in one revolution
ID 1 Multi-turn data
ID 2 Encoder ID
ID 3 All of the above plus the encoder error status
Reset ID 7 Reset absolute data in one revolution
ID 8 Reset multi-turn data
ID C Reset errors
EEPROM ID D Read encoder's EEPROM
ID 6 Write to encoders EEPROM
Each transaction consists of 10-bit fields. Each field has the format shown in Table 2-3. The first bit is a start bit
(always 0) and the last bit is a delimiter bit (always 1). The content of the 8-bits of data between the start bit and
delimiter depend on the specific type of field.
Table 2-3. T-Format Field Format
Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10
Content Start bit
Always 0
8 data bits: Least significant bit first.
The content depends on the specific field. These 8 bits of data are included in the CRC calculation.
Delimiter
bit
Always 1
The fields defined by the T-Format protocol are:
ControlField (CF) The first field in every request and every response. The ControlField includes the
unique Data ID for the transaction.
StatusField (SF) Status information from the encoder.
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DataFields (DFx) Information from the encoder. The content and number of DataFields depend on the
transaction. Examples of DataFields include the encoder's ID, position information, and
error codes. Up to 8 DataFields are possible.
CRCField An 8-bit Cyclic Redundancy Check (CRC) of the data. A CRCField is the last field of an
EEPROM read or write request. The CRCField is always the last field in the encoder's
response.
EEPROM
AddressField (ADF)
Address to be read or written in an EEPROM transaction.
EEPROM DataField
(EDF)
Contains the data read, or the data to be written, in an EEPROM transaction.
Note
For the specific contents of each field, refer to the T-Format specification available from Tamagawa.
The fields used in a request are shown in Table 2-4. To begin a transaction, the controller sends a request
through the encoder interface. The request starts with the ControlField which includes the Data ID. The encoder
uses the Data ID to identify the exact transaction requested. For a readout or reset request, only the ControlField
is required. In the case of an EEPROM read or write the controller also sends an EEPROM AddressField and an
EEPROM DataField (for a write) followed by a CRCField.
Table 2-4. T-Format Request Fields
Request type Fields Transmitted
Readout ControlField
Reset ControlField
EEPROM Write ControlField EEPROM AddressField EEPROM DataField CRCField(1)
EEPROM Read ControlField EEPROM AddressField CRCField
(1) The CRC calculation includes the 8-bits of data in the Control, EEPROM Address and EEPROM Data fields. The start bits and
delimiter bits are excluded.
The fields used in an encoder's response depend on the specific request. For readout and reset transactions
(Table 2-5), the encoder responds with an echo of the ControlField, follwed by a StatusField and one or more
DataFields. Lastly the encoder always sends a CRCField. The CRCField can be used as an integrity check of
the received data.
Table 2-5. T-Format Response Fields for Readout and Reset
Data ID Type Control
Field(1)
Status
Field
DataFields (DF0:DF1:….DF7) + CRC (2) (3)
ID 0 Read CF SF ABS0(4) ABS1 ABS2 CRC
ID 1 Read CF SF ABM0(5) ABM1 ABM2 CRC
ID 2 Read CF SF ENID(6) CRC
ID 3 Read CF SF ABS0 ABS1 ABS2 ENID ABM0 ABM1 ABM2 ALMC(7) CRC
ID 7 Reset CF SF ABS0 ABS1 ABS2 CRC
ID 8 Reset CF SF ABS0 ABS1 ABS2 CRC
ID C Reset CF SF ABS0 ABS1 ABS2 CRC
(1) CF: ControlField. Matches the ControlField sent in the request.
(2) DF: DataField. Up to 8 fields depending on the transaction.
(3) The CRCField is always transmitted immediately after the last used DataField. The CRC includes the 8-bits of data in the CF + SF +
DataFields used. The start-bit and delimiter of each field is excluded.
(4) ABS: Absolute data in one revolution. Uses 3 fields.
(5) ABM: Multi-turn data. Uses 3 fields.
(6) ENID: Encoder ID. One field.
(7) ALMC: Encoder error. One field
In the following data readout example, the controller requests the multi-turn data (Data ID 1). Referencing Table
2-5, the response DataFields correspond to the multi-turn data (ABM0:ABM1:ABM2).
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Table 2-6. Data Readout Example
Request: ControlField
for Data ID 1
Response: ControlField
for Data ID 1
StatusField DataField0 DataField1 DataField2 CRC
For a EEPROM transaction, the encoder responds with the ControlField + EEPROM AddressField + EEPROM
DataField + CRCField as shown in Table 2-7.
Table 2-7. EEPROM Read/Write Response Fields
Data ID Request Field 0 Field 1 Field 2 Field 3
ID 6 Write ControlField EEPROM
AddressField
EEPROM
DataField (1)
CRCField(3)
ID D Read ControlField EEPROM
AddressField
EEPROM
DataField (2)
CRCField
(1) Data read from the encoder's EEPROM.
(2) Data written to the EEPROM. This is an echo of the DataField in the request.
(3) The CRC calculation includes the 8-bits of data in the Control, EEPROM Address and EEPROM Data fields. The start bit and delimiter
of each field are excluded.
2.3.2 C2000 T-Format Encoder Interface Overview
Communication over a T-Format encoder interface is primarily achieved by the following components:
• CPU (C28x)
– Configures the device, CLB, and SPI
– Packs and unpacks data
– Calculates the transmit CRC for EEPROM commands
– F2837xD only: Calculates CRC for received data
– Compares calculated CRC with received CRC
• Configurable logic block (CLB)
– Controls the SPI clock
– Controls the transmit enable signal to the RS-485 transceiver
– Measures, and compensates for, cable propagation delay as required by the interface
– Calculates the CRC of the received data (feature not available on F2837xD)
• Serial peripheral interface (SPI)
– Performs the encoder-data transmit and receive
• Device interconnects (XBARs or CLB XBARs)
– Route signals into and out of the CLB and the device
• External interface block
– TIDM-1011 board with RS-485 differential line driver
Note
Depending on the device features, different methods are used to calculate CRCs. Refer to Section
2.3.5 for information.
Figure 2-3 shows the T-Format encoder interface connections.
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CLB
SPICLK
INPUT
XBAR
OUTPUT
XBAR
TxEn
C28x
CPU
SPI-B
Peripheral
SPICLK
SPISMO
SPISOMI
SPISTE
TMS320F28379D
TX_DIR
DATA_IN
DATA_OUT
GND
PWR CTL
Test Setup
Interface
Block
Figure 2-3. T-Format Implementation Diagram Inside TMS320F28379D
The remainder of this section describes the following aspects of the design:
• The TIDM-1011 hardware (BOOSTXL-POSMGR)
• C2000 MCU resources including the CLB design
• C2000 software used by the encoder interface
2.3.3 TIDM-1011 Board Implementation
The TIDM-1011 board provides the following:
• Differential line driver and receiver for RS-485 communication between a C2000 MCU and the encoder.
• TxEN signal routed from the MCU to the direction control of the RS-485 driver/receiver.
• SPICLK signal routed to a GPIO where it can be controlled by the CLB peripheral. This connection is optional
for all supported devices except the F2837x family.
Note
The TIDM-1011 daughter card is identical to the Position Manager BoosterPack plug-in module
(BOOSTXL-POSMGR), which means the TIDM-1011 can interface with several position-encoder
types. The board is fully populated by default. This reference design focuses on the T-Format absolute
encoder protocol, and the hardware blocks not used can be ignored.
Table 2-8 lists the connectors used by the TIDM-1011 T-Format implementation and their functions.
Table 2-8. TIDM-1011 Board and BOOSTXL-POSMGR Connectors
CONNECTOR DESCRIPTION USED BY TIDM-1011
Abs-Enc-1 (J7) T-Format and other absolute encoders Yes, LaunchPad Site 2
Abs-Enc-2 (J8) T-Format and other absolute encoders No
Abs-Enc-2 Breakout (J10) Allows two absolute encoders at site two
using jumpers
No
SinCos (J14) SinCos encoder No
Resolver (J14 and J15) Resolver interface with 15-V excitation
circuitry
No
PTO (J17) Pulse-train output No
J1, J3 and J4, J2 BoosterPack connector Yes
J6 5-V DC supply input Yes
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Table 2-8. TIDM-1011 Board and BOOSTXL-POSMGR Connectors (continued)
CONNECTOR DESCRIPTION USED BY TIDM-1011
J16 15-V DC resolver excitation input No
Figure 2-4 shows the encoder support on each site of the LaunchPad.
Site 1 (J1 J3 + J4 J2)
x x1 T-Format or other Absolute Encoder
and PTO
x x2 T-Format or other Absolute Encoder
(simultaneously)
x x1 PTO
x x1 Resolver and PTO
x x1 Absolute SinCos (Channels C and D,
requires two BOOSTXL-POSMGR)
Site 2 (J5 J7 + J8 J6)
x X1 SinCos Encoder
x x1 T-Format or other Absolute Encoder
and PTO
x x1 Resolver and PTO
x x1 PTO
x x1 Absolute SinCos (Channels A, B, I,
requires two BOOSTXL-POSMGR)
Figure 2-4. TIDM-1011 Board and BOOSTXL-POSMGR Encoder Support
As provided, TIDM-1011 uses LaunchPad Site 2 and BOOSTXL-POSMGR's Encoder 1 connections. Figure 2-5
shows the connections. The complete schematic of the TIDM-1011 BoosterPack can be downloaded from the
BOOSTXL-POSMGR product page.
Note
The F2837xD device requires an external connection between the CLB generated clock
(CLB_SPI_CLK) and the SPICLK pin. On all other devices the CLB can directly drive SPICLK and
an external connection is not required.
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60
59
GND
SPISTE
55 SPISIMO
54 SPISOMI
80
79
61
62
41
42
58
57
56
53
52
51
75
74
78
77
76
73
72
71
J8/J6J5/J7
63
64
65
66
67
68
69
70
43
44
45
46
47
48
49
50
SPICLK
TxEn
PWREN
LaunchPad BoosterPack Header Site 2,
BoosterPack Encoder 1
CLB_SPI_CLOCK On some devices the CLB_SPI_CLK to SPICLK
connection is internal to the device.
RS485
SN65HVD78D
D+
D-
TxEn
Encoder
Power Enable
TPS22918TDBVRQ1
5V
GND
Up to 100m
Figure 2-5. LaunchPad Site2 with BOOSTXL-POSMGR Encoder 1 Pinout
2.3.4 MCU Resource Requirements
Table 2-9 lists the C2000 Real-Time MCU resources used by the TIDM-1011 reference design. Specifics for
each device are described in Section 2.3.5.
Table 2-9. TIDM-1011 Resource Usage
RESOURCE NAME and Quantity TYPE PURPOSE
CLB x 2 1 Tile Provides the SPI clock, delay compensation, and
TxEn control. If the tile is changed, then routing
in/out of the CLB must also be updated.
1 Tile (Optional) Calculate the response CRC as the message is
received. This option is only available on devices
with CLB Type 2 or later.
GPIO x 2 I/O • CLB output, RS-485 direction control (TxEN)
• CPU encoder power control (PwrCtl)
GPIO x 1 I/O (F2837xD only) • CLB output of CLB_SPI_CLK
• CLB Type 1: route this pin externally to the
SPICLK input.
• CLB Type 2, or later: clock the SPI module
directly from the CLB. An external connection
is not required, but can be useful for test and
debug.
INPUTXBAR or CLB_INPUTXBAR x 1 Module, I/O Connect the SPI SIMO pin to the CLB.
OUTPUTXBAR or CLB_OUTPUTXBAR x 1 Module, I/O Connects the CLB to TxEN (direction control).
SPI x 1 Module and I/Os One SPI instance to transmit and receive on the
RS-485 physical layer. The SPI clock is controlled
by the CLB.
CPU and Memory Module CPU and memory use for various functions.
2.3.5 Device-Specific Resource Usage
Device-specific resources used by TIDM-1011 include:
• Resource to perform the CRC calculations.
• Input and output signals and the specific CLB tile instance(s) used.
2.3.5.1 CRC Calculations
Cyclic Redundancy Check (CRC) is an error detection mechanism used in communication networks and data
storage. The device resources available on a C2000 MCU to calculate a CRC have increased over time.
TIDM-1011 uses different resources depending on device features and whether the data is transmitted or
received. The resource usage is summarized in Table 2-10.
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Table 2-10. Resource Used for CRC Calculations
Device Receive Data CRC Transmit Data CRC
F2837xD C28x plus lookup table C28x plus lookup table
F28004x Configurable Logic Block C28x lookup table
All others Configurable Logic Block VCRC extension to C28x
•C28x Lookup Table is available on all C28x devices. This method, however, is the slowest and requries
RAM memory for look-up table storage. TIDM-1011 only uses a look-up table on devices without another
capability.
•Configurable Logic Block (CRC) is available on devices with CLB type 2, or later. The CLB calculates a
CRC using a counter configured as a Linear Feedback Shift Register (LFSR). This method has been used
to calculate the CRC of the encoder response as the data is being received. This frees C28x bandwidth as
no additional calculations are required. The C28x reads the CRC result directly from the counter register. The
cost of this method is CLB tile resources and code to configure the tile. The CLB CRC implementation is
documented in Section 2.3.7.
•VCRC is a C28x instruction set extension specifically for CRC calculations. The implementation is faster than
the C28x lookup-table for longer messages. In addition, the VCRC does not require RAM space to store a
lookup-table. For devices with the VCRC module, this method has been used to calculate the transmit data
CRC used in EEPROM read/write transactions.
Note
The CRC method can be selected in the T-Format library header file.
2.3.5.2 Input, Output Signals and CLB Tiles
This section describes the input/output and CLB tile connections used on each device.
Note
In the input/output diagrams, a letter in a colored circle indicates an off-page connection.
• Communication tile: Connectors A, B, C, and G are described in Section 2.3.6
• CRC tile: Connectors B, F, E, and A are described in Section 2.3.7
The GPIO pins and SPI module used depend on the device-specific LaunchPad and BOOSTXL-POSMGR
BoosterPack pinout. The connections into, and out of, the CLB depend on the features of that device.
The specific tile instances used depend on the capability of the tile to override other signals such as the
SPICLK.Table 2-11 summarizes the input/output resources used by each device family. The I/O figure for each
device details which GPIOs and CLB tiles were used.
Table 2-11. Input / Output and Tile Summary per Device
Device I/O Figure CLB RX CRC Tile (3) SPI Module CLB to SPICLK Other I/O
F2837xD Figure 2-6 No SPI-B Externally connected Tile 4 override of
EPWM4B. (1)
Device INPUTXBAR
and OUTPUTXBAR
F28004x Figure 2-7 Yes SPI-B Driven directly by tile
4
Device INPUTXBAR
and OUTPUTXBAR
F28003x
F28002x
Figure 2-8 Yes SPI-B Driven directly by tile
2
CLB_INPUTXBAR
and
CLB_OUTPUTXBAR
F2838x Figure 2-9 (2) Yes SPI-B Driven directly by tile
2
CLB_INPUTXBAR
and
CLB_OUTPUTXBAR
(1) CLB tile 4 overrides the EPWM4B output signal to control GPIO7. No other ePWM functionality is used.
(2) The F2838x family is not supported by the LaunchPad development platform. The pins used by the TMDXIDDKF273XD hardware
platform are shown in the I/O diagram.
(3) For devices with a CRC tile, connections between the communication tile and CRC tile are shown in the I/O diagrams.
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Note
At the time this document was published, the F2837xD and F28004x are supported by
TMDXIDDKF273XD development kit projects. For convenience, the GPIOs for both the
BOOSTXL_POSMGR and TMDXIDDKF273XD platform have been provided in the I/O diagrams.
GPREG.bit0
ENCODER_RESPONSE
INPUTXBAR1
F2837x CLB Input and Output Mapping
CLB_SPI_CLOCK Tile4_OUTLUT2
out2
GPIO7
(override ePWM4A)
SPI RX FIFO
RS485 Logic
T-format Communication Tile
C
RISING_EDGE
FILTER
Tile4_in0
Tile4_in1 FALLING_EDGE
FILTER A
ENCODER_RESPONSE
(falling edge)
START_OPERATION
TxEN
Tile4_in3 ANY_EDGE
FILTER G
CLB XBAR AUXSIG0
SPI TX FIFO
SPI SOMI Pin
GPIO64 BOOSTXL_POSMGR
GPIO25 TMDXIDDK379D
RS485 Logic
RS485 Logic
ENCODER
C28x CPU
C28x CPU
C28x CPU
OUTPUTXBAR1
Tile4_OUTLUT4
out 4
C28x CPU Power Enable
GPIO139 BOOSTXL_POSMGR
GPIO32 TMDXIDDK379D
SPI SIMO Pin
GPIO63 BOOSTXL_POSMGR
GPIO24 TMDXIDDK379D
GPIO to SPI CLK connection
is external to the MCU
OUTPUTXBAR6
Board dependent TXEN Pin
GPIO9 BOOSTXL_POSMGR
GPIO34 TMDXIDDK379D
SPI CLK Pin
GPIO65 BOOSTXL_POSMGR
GPIO26 TMDXIDDK379D
SPI STE Pin
GPIO66 BOOSTXL_POSMGR
GPIO27 TMDXIDDK379D GND
Tile 4 can override the ePWM4A pin directly
Interrupt
Figure 2-6. F2837xD Input, Output, and CLB Usage for BOOSTXL_POSMGR and TMDXIDDKF273XD
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SPICLK Test Point
Monitor this test point with an oscilloscope during test and
debug. This GPIO is not required for normal operation.
GPREG.bit0
ENCODER_RESPONSE
INPUTXBAR1
F28004x CLB Input and Output
CLB_SPI_CLOCK Tile4_OUTLUT0
SPICLKB (in)
GPIO6 (override ePWM4A)
Tile4_OUTLUT2
out 2
Tile4 can override SPICLK-B directly.
An external connection is not required.
SPI SIMO Pin
GPIO24 RX FIFO
Tile4_OUTLUT5
out 21
CLB
Global
MUX
Tile1_in0
B
Tile4_OUTLUT1
out17 Tile1_in1
Tile4_OUTLUT6
out 22 Tile1_in3
CLB_SPI_CLOCK
_RISING_EDGE
RS485 Logic
RECEIVE_DATA CRC Tile
out 8
out 0
T-format Communication Tile
FRAME_STATE
B
C
RISING_EDGE
FILTER
Tile4_in0
Tile4_in1 FALLING_EDGE
FILTER A
ENCODER_RESPONSE
(falling edge)
Tile4_in2 Tile4_OUTLUT7
out23 EENCODER_RESPONSE
Tile1_in2
Tile1_in4 FALLING_EDGE
FILTER
ENCODER_RESPONSE
Falling edge
FRAME_STATE
START_OPERATION
F
TxEN
Tile4_in3 ANY_EDGE
FILTER G
CLB XBAR AUXSIG0
SPI-B Peripheral
TX FIFO
SPI SOMI Pin
GPIO31 BOOSTXL_POSMGR
GPIO25 TMDXIDDK379D
RS485 Logic
RS485 Logic
ENCODER
C28x CPU
C28x CPU
C28x CPU
TXEN
GPIO7 BOOSTXL_POSMGR:(override ePWM4B)
GPIO34 TMDXIDDK379D
OUTPUTXBAR1
Tile4_OUTLUT4
out 4
Power Enable
GPIO28 BOOSTXL_POSMGR
GPIO10 TMDXIDDK379D
C28x CPU
SPISTE
GPIO27
GND
A
CLB_SPI_CLOCK
_RISING_EDGE
Figure 2-7. F28004x Input, Output, and CLB Usage for BOOSTXL_POSMGR and TMDXIDDKF273XD
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SPICLK Test Point
ENCODER_RESPONSE
CLB_INPUTXBAR1
F28003x or F28002x CLB Input and Output
CLB_OUTPUTXBAR2
CLB_SPI_CLOCK
CLB2_OUTLUT0
SPICLKB
CLB_OUTPUTXBAR8 F28002x: GPIO6
F28003x: GPIO0
Monitor this test point with an oscilloscope during test and
debug. This GPIO is not required for normal operation.
GPIO7
Tile2_OUTLUT4
out 4
On this device CLB Tile 2 can override
SPI-B signals directly. An external
connection is not required.
CLB
Global
MUX
Tile1_in0
B
Tile2_OUTLUT1
out17 Tile1_in1
Tile2_OUTLUT6
out 22 Tile1_in3
CLB_SPI_CLOCK_RISING_EDGE
TxEN RS485 Logic
RECEIVE_DATA CRC Tile
CLB2_OUT0
CLB2_OUT24
T-format Communication Tile
FRAME_STATE
B
Tile2_in2 Tile2_OUTLUT7
out23 E
ENCODER_RESPONSE
Tile1_in2
Tile1_in4 FALLING_EDGE
FILTER
ENCODER_RESPONSE
Falling edge
FRAME_STATE
F
SPI Peripheral
Input
Pipeline
TxEN
Tile2_in3 ANY_EDGE
FILTER G
s0
s1
Tile2_OUTLUT5
out21
F
Power Enable
GPIO35 F28002x BOOSTXL_PMGR
GPIO15 F28003x BOOSTXL_PMGR
SPI SIMO Pin
GPIO30 F28002x BOOSTXL_PMGR
GPIO60 F28003x BOOSTXL_PMGR
RX FIFO
TX FIFO
C28x CPU
Interrupt
SPI STE Pin
GPIO33 F28002x BOOSTXL_POSMGR
GPIO59 F28003x BOOSTXL_POSMGR GND
C28x CPU
SPI SOMI Pin
GPIO31 F28002x BOOSTXL_POSMGR
GPIO61 F28003x BOOSTXL_POSMGR
RS485 Logic ENCODER
GPREG.bit0
C
RISING_EDGE
FILTER
CLB2_IN0
CLB2_IN1 FALLING_EDGE
FILTER A
ENCODER_RESPONSE
(falling edge)
Figure 2-8. F28002x and F28003x Input, Output, and CLB Usage for BOOSTXL_POSMGR
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SPICLK Test Point
Monitor this test point with an oscilloscope during test and
debug. This GPIO is not required for normal operation.
GPREG.bit0
ENCODER_RESPONSE
CLB_INPUTXBAR1
F2838x CLB Input and Output (TMDXIDDK2879D)
CLB_SPI_CLOCK Tile2_OUTLUT0
SPICLKB (in)
GPIO2 (override ePWM2A)
Tile2 can override SPICLK-B directly.
An external connection is not required.
SPI SIMO
GPIO24 RX FIFO
Tile2_OUTLUT2
out 18
CLB
Global
MUX
Tile1_in0
B
Tile2_OUTLUT1
out 17 Tile1_in1
Tile2_OUTLUT3
out 19 Tile1_in3
CLB_SPI_CLOCK_
RISING_EDGE
RS485 Logic
RECEIVE_DATA CRC Tile
out 24
out 0
T-format Communication Tile
FRAME_STATE
B
C
RISING_EDGE
FILTER
Tile2_in0
Tile2_in1 FALLING_EDGE
FILTER A
ENCODER_RESPONSE
(falling edge)
Tile2_in2 Tile2_OUTLUT4
out 20 E
ENCODER_RESPONSE
Tile1_in2
Tile1_in4 FALLING_EDGE
FILTER
ENCODER_RESPONSE
Falling edge
FRAME_STATE
START_OPERATION
F
TxEN
Tile2_in3 ANY_EDGE
FILTER G
SPI-B Peripheral
TX FIFO
SPI SOMI
GPIO25 RS485 Logic
RS485 Logic
ENCODER
C28x CPU
C28x CPU
C28x CPU
TXEN
GPIO34
CLB_OUTPUTXBAR3
Tile2_OUTLUT5
out 13
Power Enable
GPIO32
C28x CPU
SPISTE
GPIO27
GND
Figure 2-9. F2838x Input and Output for TMDXIDDKF273XD
2.3.6 CLB T-Format Implementation Details
The CLB communications tile is responsible for:
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• Clocking the SPI to transmit the request.
• Monitoring the SPI SIMO pin for a response from the encoder.
• Aligning the SPICLK to the incoming response.
• Clocking the SPI to receive the response.
This section describes the design of the communication tile using three different approaches:
1. Visualization of the CLB behavior during each phase of the transaction using waveforms.
2. The CLB tile design including interconnect of the submodules.
3. Using a logic schematic lens.
2.3.6.1 Transaction Waveforms
When implementing a CLB design, first visualizing the required CLB behavior using waveforms can be helpful.
To do this, first consider an an example transaction. Recall a T-Format transaction consists of the request
transmission plus the encoder's response. A transmission can be broken up into FRAME_STATEs as shown in
Figure 2-10. The first step is to map each element of the transaction to a CLB submodule. Table 2-12 shows an
example mapping.
Table 2-12. T-Format Transaction to CLB Mapping
Transaction Behavior CLB Mapping
Track the FRAME_STATE Finite State Machine (FSM): transitions to a new state given the
previous state and current inputs.
Count the clocks generated A COUNTER: configured to increment a clock edge during the
TRANSMIT_DATA and RECEIVE_DATA states. The mode0 input
controls when the counter is active and when the counter is halted.
Leverage the COUNTER's match values to drive state transitions
(TRANSMIT_DATA to WAIT_FOR_START and RECEIVE_DATA to
IDLE).
Generate a clock signal of a specific width This requirement maps to a second COUNTER. Leverage the match
values to generate the timing for the the rising/falling edges. A
LUT (Lookup Table) then generates the actual edges based on this
timing.
Align the clock with the encoder's response The COUNTER generating the clock can be configured such that the
edge transition is properly aligned with the encoder's response.
Only allow the SPI to be clocked during transmit and receive A LUT blocks the clock when not needed.
Control the TxEN A LUT leverages the current FRAME_STATE to control the signal.
Tell the CLB to start the transaction The C28x configures the COUNTER and SPI for the transaction. The
CLB GPREG allows the C28x CPU to directly change a CLB input to
start a transaction.
WAIT_FOR_START
IDLE
TxEN
Driven by CLB
TRANSMIT_DATA RECEIVE_DATA
SPI SOMI
Request to
Encoder
SPI CLK (2.5 MHz)
Driven by CLB
0 0 1 0
IDLE
START
SINK DATAID + …..
… ...
IDLE
SPI SIMO
Response from
Encoder
… ...
… ...
… ...
0 0 1 0
IDLE
START
SINK
… ...
DATAID + …..
Cable Length DependentCycles are Command Dependent
Command Dependent Data
Command Dependent Response
… ...
… ...
… ...
… ...
Cycles are Command Dependent
FRAME_STATE
Transmit on the Falling Edge of SPICLK
Receive on the Rising Edge of SPICLK
Figure 2-10. T-Format Transaction Example
The next step is visualization of the specific submodule behavior. Start with a quick sketch and then add
additional detail as the design develops. Figure 2-11 shows an example waveform.
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SEND_DATA WAIT_FOR_START RECEIVE_DATAIDLE
1
2
4
6
IDLE
5
3
Figure 2-11. CLB Communication Waveform
Note
Figure 2-11 was generated using the CLB SystemC simulation model with a custom input as the
encoder's response. The transmitted request is not specifically shown in Figure 2-11. The SPI module
sends the request based on the CLB_SPI_CLK during the TRANSMIT_DATA (or SEND_DATA)
phase.
Markers 1 - 6 in Figure 2-11 are used in the following sections to describe specific behavior of the design with
respect to that marker. The markers are:
1. Transition from IDLE to TRANSMIT_DATA (or SEND_DATA)
2. Transition to WAIT_FOR_START
3. During WAIT_FOR_START
4. Transition to RECEIVE_DATA
5. During RECEIVE_DATA
6. Transition back to IDLE
Following the description of each FRAME_STATE, Section 2.3.6.2 presents the complete tile design. Refer to
Section 2.3.6.2 along with Figure 2-11while reading the descriptions of each state.
2.3.6.1.1 IDLE State
During IDLE there is no activity on the interface. The C28x must first setup a request. The T-Format API provides
functions to setup each type of request:
• PM_tformat_setupCommandReadEEPROM()
• PM_tformat_setupCommandWriteEEPROM()
• PM_tformat_setupCommandReadoutOrReset()
The _setupCommand function creates a request data packet, loads the data to the SPI TX FIFO, and configures
the CLB to generate the number of SPI clocks required to send the request and receive the response. Once
setup is complete, the C28x starts the transaction by calling the PM_startOperation() function.
Refer to: Figure 2-2, marker (1).
When the transaction begins, the START_OPERATION signal is pulled high through GPREG. GPREG is the
CLB's general purpose register allowing the C28x to directly control the tile's inputs. START_OPERATION
remains high for one CLB CLOCK because the CLB's rising edge filter is enabled for the input. At this point,
the main state machine (FSM_1) responds by moving the FRAME_STATE from IDLE to the TRANSMIT_DATA
state.
2.3.6.1.2 TRANSMIT_DATA State
During the TRANSMIT_DATA (or SEND_DATA) state, the encoder interface sends the request to the encoder.
The request is sent from the SPI TX FIFO on the falling edge of the SPICLK. During TRANSMIT_DATA, the
CLB:
• Enables transmission through the RS-485 driver by pulling the TxEN signal high.
• Starts generation of the CLOCK signal. CLOCK becomes the CLB_SPI_CLOCK.
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• CLB_SPI_CLOCK drives the SPI module clock.
• The CLOCK_COUNT (COUNTER_1) keeps track of the number of CLB_SPI_CLOCKs generated.
The number of CLB_SPI_CLOCKs required to send the transmission was loaded into both the match1 and
match2 of the CLOCK_COUNT by the C28x during command setup.
Refer to: Figure 2-2, marker (2).
When the required number of clocks has been reached, the CLOCK_COUNT_COMPLETE (match2) and
TRANSMIT_COMPLETE (match1) signals are pulled high. The effect is:
• The main state machine transitions to WAIT_FOR_START
• The CLOCK signal is disconnected from CLB_SPI_CLOCK
• TxEN is driven low to give control of the RS-485 to the sensor or encoder.
2.3.6.1.3 WAIT_FOR_START State
Refer to: Figure 2-2, marker (3).
During the WAIT_FOR_START state, the CLB is monitors the ENCODER_RESPONSE for a falling edge. The
falling-edge corresponds to the first start bit in the response from the encoder. The time required can be any
number of clock cycles and depends on the state of encoder and the cable length.
During WAIT_FOR_START, the CLOCK_COUNT match and CLOCK_COUNT_COMPLETE signals are ignored
and the generated CLOCK is disconnected from the CLB_SPI_CLOCK.
2.3.6.1.4 RECEIVE_DATA State
Refer to: Figure 2-2, marker (4).
On the falling edge of ENCODER_RESPONSE, the FRAME_STATE transitions from WAIT_FOR_START to
RECEIVE_DATA.
Refer to: Figure 2-2, marker (5).
During the RECEIVE_DATA, the SPI receives the response from the encoder. The size of the response (number
of clocks) depends on the specific request sent during TRANSMIT_DATA. The number of required clocks was
configured by the C28x during the command setup. To receive the response:
• The CLB aligns CLB_SPI_CLK to the response. The response is sampled on the rising edge of the clock.
Alignment is repeated on each edge of the response by resetting the counter which controls the clock edge
placement.
• The CLOCK signal is reconnected to the CLB_SPI_CLK.
• The clock count (COUNTER_1) match2 is adjusted by the HLC. The current count is read, increased by the
number of clocks needed to receive the response, and then written back.
• Once the RX FIFO is full, the SPI interrupts the C28x to indicate the response has been received. The C28x
calls the specific receiveData function to unpack the data.
Refer to: Figure 2-2, marker (6).
When the number of clocks required to receive the response is reached, the CLOCK_COUNT_COMPLETE
signal is pulled high. The CLB returns FRAME_STATE back to IDLE.
This pattern is repeated for each transaction with the encoder.
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2.3.6.2 Communication Tile Design
Frame State Generation
LUT_0
CLB_SPI_CLOCK
edge reset control
i0
i1
i2
i3
out
FSM_1
Primary state
machine. Detects the
frame transitions from
transmit, wait to
receive.
e0
e1
xe0
xe1
s0
s1
out
COUNTER_0
CLB_SPI_CLOCK
Edge Generation
reset
event
mode0
mode1
zero
match1
match2
LUT_1
Toggles high at the
start of the
TRANSMIT_DATA
and RECEIVE_DATA
states
i0
i1
i2
i3
out
FSM_0
CLOCK Generation
e0
e1
xe0
xe1
s0
s1
out
COUNTER_1
Increments on the
rising edge of the
generated CLOCK
reset
event
mode0
mode1
zero
match1
match2 FSM_2
TxEN Generation
e0
e1
xe0
xe1
s0
s1
out Tile4_out4 TxEN
FRAME_ACTIVE (not IDLE)
FRAME_STATE
FRAME_STATE
A
FRAME_STATE
LUT_2
Triggers an update of
COUNTER1.match2
(CLOCK Count) by
the HLC
i0
i1
i2
i3
out HLC.e0
Device Dependent
CLB_SPI_CLOCK
Qualification
i0
i1
i2
out
CLB_SPI_CLOCK
CLOCK
Route to device’s SPICLK input
TRANSMIT_DATA or RECEIVE_DATA
ENCODER_RESPONSE
(any edge)
FRAME_ACTIVE
TRANSMIT_COMPLETE
START_OPERATION
C
CLOCK_COUNT_COMPLETE
START_OPERATION
s1, s0
0,0 0,1
1,0
1,1
IDLE TRANSMIT_DATA
WAIT_FOR_START
RECEIVE_DATA
HLC updates COUNTER1.match2
START_OPERATION
GPREG.0 Rising Edge
COUNTER1.match2
Rising edge
ENCODER_RESPONSE
Falling Edge
COUNTER1.match2
Rising edge
TRANSMIT_OR_RECEIVE_STARTED
1
WAIT_FOR_DATA or RECEIVE_DATA
ENCODER_RESPONSE
(falling edge)
ENCODER_RESPONSE
(falling edge)
Resets the CLOCK edge genera

on when:
CLOCK width is reached or
ENCODER_RESPONSE falling or rising edge is
detected during the WAIT_FOR_DATA or
RECEIVE_DATA framestate
CLOCK_RISING_EDGE (SPI RX Sample)
CLOCK_WIDTH_REACHED
CLOCK_FALLING_EDGE
1
CLOCK_COUNT_COMPLETE
TRANSMIT_DATA or RECEIVE_DATA
s0
0
s0
1
NOT_TRANSMITTING TRANSMITTING
START_OPERATION
GPREG.0 Rising Edge
TRANSMIT_COMPLETE
OUT == s0
FRAME_ACTIVE
DFRAME_ACTIVE
B
A
FRAME_STATE
B
C
D
B
B
D
D
TRANSMIT_OR_RECEIVE_STARTED
CLOCK_ALIGNMENT
G
F
Figure 2-12. T-Format Communication Tile
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