Texas Instruments TMS320C6452 DSP User manual

TMS320C6452 DSPHost Port Interface (HPI)
User's Guide
Literature Number: SPRUF87AOctober 2007 – Revised May 2008

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Contents
Preface ........................................................................................................................................ 61 Introduction ......................................................................................................................... 91.1 Purpose of the Peripheral ................................................................................................ 91.2 Features .................................................................................................................... 91.3 Functional Block Diagram .............................................................................................. 101.4 Industry Standard(s) Compliance Statement ........................................................................ 111.5 Terminology Used in This Document ................................................................................. 112 Peripheral Architecture ....................................................................................................... 122.1 Clock Control ............................................................................................................. 122.2 Memory Map ............................................................................................................ 122.3 Signal Descriptions ...................................................................................................... 122.4 Pin Multiplexing .......................................................................................................... 122.5 Protocol Description ..................................................................................................... 122.6 Endianness Considerations ............................................................................................ 122.7 Architecture and Operation ............................................................................................. 142.8 Reset Considerations ................................................................................................... 312.9 Initialization ............................................................................................................... 322.10 Interrupt Support ......................................................................................................... 322.11 EDMA Event Support ................................................................................................... 342.12 Power Management ..................................................................................................... 342.13 Emulation Considerations .............................................................................................. 343 Registers ........................................................................................................................... 353.1 Peripheral Identification Register (PID) ............................................................................... 353.2 Power and Emulation Management Register (PWREMU_MGMT) ............................................... 363.3 Host Port Interface Control Register (HPIC) ......................................................................... 373.4 Host Port Interface Write Address Register (HPIAW) .............................................................. 393.5 Host Port Interface Read Address Register (HPIAR) ............................................................... 40
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List of Figures
1 HPI Block Diagram ......................................................................................................... 112 Example of Host-Processor Signal Connections ....................................................................... 153 HPI Strobe and Select Logic .............................................................................................. 164 16-bit Multiplexed-Mode Host Read Cycle .............................................................................. 195 16-bit Multiplexed-Mode Host Write Cycle .............................................................................. 206 Multiplexed-Mode Single-Halfword HPIC Cycle (Read or Write) .................................................... 217 HRDY Behavior During an HPIC or HPIA Read Cycle in the 16-bit Multiplexed Mode ........................... 228 HRDY Behavior During a Data Read Operation in the 16-bit Multiplexed Mode (Case 1: HPIA WriteCycle Followed by Nonauto-increment HPID Read Cycle) ........................................................... 229 HRDY Behavior During a Data Read Operation in the 16-bit Multiplexed Mode (Case 2: HPIA WriteCycle Followed by Auto-increment HPID Read Cycles) .............................................................. 2310 HRDY Behavior During an HPIC Write Cycle in the 16-bit Multiplexed Mode ..................................... 2311 HRDY Behavior During a Data Write Operation in the 16-bit Multiplexed Mode (Case 1:No Auto-incrementing) ..................................................................................................... 2412 HRDY Behavior During a Data Write Operation in the 16-bit Multiplexed Mode (Case 2:Auto-incrementing Selected, FIFO Empty Before Write) .............................................................. 2413 HRDY Behavior During a Data Write Operation in the 16-bit Multiplexed Mode (Case 3:Auto-incrementing Selected, FIFO Not Empty Before Write) ......................................................... 2414 HRDY Behavior During an HPIC or HPIA Read Cycle in the 32-Bit Multiplexed Mode .......................... 2515 HRDY Behavior During a Data Read Operation in the 16-Bit Multiplexed Mode (Case 1: HPIA WriteCycle Followed by Non-auto-increment HPID Read Cycle) .......................................................... 2516 HRDY Behavior During a Data Read Operation in the 32-Bit Multiplexed Mode (Case 2: HPIA WriteCycle Followed by Auto-increment HPID Read Cycles) .............................................................. 2617 HRDY Behavior During an HPIC Write Cycle in the 32-Bit Multiplexed Mode ..................................... 2618 HRDY Behavior During a Data Write Operation in the 32-Bit Multiplexed Mode (Case 1: NoAuto-incrementing) ......................................................................................................... 2719 HRDY Behavior During a Data Write Operation in the 32-Bit Multiplexed Mode (Case 2:Auto-incrementing Selected, FIFO Empty Before Write) .............................................................. 2720 HRDY Behavior During a Data Write Operation in the 32-Bit Multiplexed Mode (Case 3:Auto-incrementing Selected, FIFO Not Empty Before Write) ......................................................... 2821 FIFOs in the HPI ........................................................................................................... 2922 Host-to-CPU Interrupt State Diagram.................................................................................... 3223 CPU-to-Host Interrupt State Diagram.................................................................................... 3324 Peripheral Identification Register (PID) .................................................................................. 3525 Power and Emulation Management Register (PWREMU_MGMT) .................................................. 3626 Host Port Interface Control Register (HPIC) – Owner (Host) Access Permissions................................ 3727 Host Port Interface Control Register (HPIC)–Non-owner (DSP) Access Permissions ............................ 3728 Host Port Interface Write Address Register (HPIAW) ................................................................. 3929 Host Port Interface Read Address Register (HPIAR) ................................................................. 40
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List of Tables
1 HPI Pins ..................................................................................................................... 132 Options for Connecting Host and HPI Data Strobe Pins .............................................................. 173 Access Types Selectable With the HCNTL Signals ................................................................... 174 Cycle Types Selectable With the HCNTL and HR/ W Signals ........................................................ 185 HPI Registers Relative to Base Address 0200 0030h ................................................................. 356 Peripheral Identification Register (PID) Field Descriptions ........................................................... 357 Power and Emulation Management Register (PWREMU_MGMT) Field Descriptions ............................ 368 Host Port Interface Control Register (HPIC) Field Descriptions ..................................................... 389 Host Port Interface Write Address Register (HPIAW) Field Descriptions ........................................... 3910 Host Port Interface Read Address Register (HPIAR) Field Descriptions ........................................... 40
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PrefaceSPRUF87A – October 2007 – Revised May 2008
Read This First
About This Manual
This document describes the features and operation of the host port interface (HPI) in the TMS320C6452Digital Signal Processor (DSP).
Notational Conventions
This document uses the following conventions.•Hexadecimal numbers are shown with the suffix h. For example, the following number is 40hexadecimal (decimal 64): 40h.•Registers in this document are shown in figures and described in tables.– Each register figure shows a rectangle divided into fields that represent the fields of the register.Each field is labeled with its bit name, its beginning and ending bit numbers above, and itsread/write properties below. A legend explains the notation used for the properties.– Reserved bits in a register figure designate a bit that is used for future device expansion.
Note: Acronyms 3PSW, CPSW, CPSW_3G, and 3pGSw are interchangeable and all refer to the 3port gigabit switch.
TMS320C6452 DSP
Related Documents From Texas InstrumentsThe following documents describe the TMS320C6452 Digital Signal Processor (DSP). Copies of thesedocuments are available on the Internet at www.ti.com .Tip: Enter the literature number in the search boxprovided at www.ti.com .
Data Manual—
SPRS371 —TMS320C6452 Digital Signal Processor Data Manual describes the signals, specificationsand electrical characteristics of the device.
CPU—
SPRU732 —TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide describes the CPUarchitecture, pipeline, instruction set, and interrupts for the TMS320C64x and TMS320C64x+ digitalsignal processors (DSPs) of the TMS320C6000 DSP family. The C64x/C64x+ DSP generationcomprises fixed-point devices in the C6000 DSP platform. The C64x+ DSP is an enhancement ofthe C64x DSP with added functionality and an expanded instruction set.
Reference Guides—SPRUF85 —C6452 DSP DDR2 Memory Controller User's Guide describes the DDR2 memorycontroller in the TMS320C6452 Digital Signal Processor (DSP). The DDR2/mDDR memorycontroller is used to interface with JESD79D-2A standard compliant DDR2 SDRAM devices andstandard Mobile DDR SDRAM devices.
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www.ti.com TMS320C6452 DSP
SPRUF86 —C6452 Peripheral Component Interconnect (PCI) User's Guide describes the peripheralcomponent interconnect (PCI) port in the TMS320C6452 Digital Signal Processor (DSP). The PCIport supports connection of the C642x DSP to a PCI host via the integrated PCI master/slave businterface. The PCI port interfaces to the DSP via the enhanced DMA (EDMA) controller. Thisarchitecture allows for both PCI master and slave transactions, while keeping the EDMA channelresources available for other applications.
SPRUF87 —C6452 DSP Host Port Interface (UHPI) User's Guide describes the host port interface(HPI) in the TMS320C6452 Digital Signal Processor (DSP). The HPI is a parallel port through whicha host processor can directly access the CPU memory space. The host device functions as amaster to the interface, which increases ease of access. The host and CPU can exchangeinformation via internal or external memory. The host also has direct access to memory-mappedperipherals. Connectivity to the CPU memory space is provided through the enhanced directmemory access (EDMA) controller.
SPRUF89 —C6452 DSP VLYNQ Port User's Guide describes the VLYNQ port in the TMS320C6452Digital Signal Processor (DSP). The VLYNQ port is a high-speed point-to-point serial interface forconnecting to host processors and other VLYNQ compatible devices. It is a full-duplex serial buswhere transmit and receive operations occur separately and simultaneously without interference.
SPRUF90 —C6452 DSP 64-Bit Timer User's Guide describes the operation of the 64-bit timer in theC6452 Digital Signal Processor (DSP). The timer can be configured as a general-purpose 64-bittimer, dual general-purpose 32-bit timers, or a watchdog timer.
SPRUF91 —C6452 DSP Multichannel Audio Serial Port (McASP) User's Guide describes themultichannel audio serial port (McASP) in the C6452 Digital Signal Processor (DSP). The McASPfunctions as a general-purpose audio serial port optimized for the needs of multichannel audioapplications. The McASP is useful for time-division multiplexed (TDM) stream, Inter-IntegratedSound (I2S) protocols, and intercomponent digital audio interface transmission (DIT).
SPRUF92 —C6452 DSP Serial Port Interface (SPI) User's Guide discusses the Serial Port Interface(SPI) in the C6452 Digital Signal Processor (DSP). This reference guide provides the specificationsfor a 16-bit configurable, synchronous serial peripheral interface. The SPI is a programmable-lengthshift register, used for high speed communication between external peripherals or other DSPs.
SPRUF93 —C6452 DSP Universal Asynchronous Receiver/Transmitter (UART) User's Guidedescribes the universal asynchronous receiver/transmitter (UART) peripheral in the C6452 DigitalSignal Processor (DSP). The UART peripheral performs serial-to-parallel conversion on datareceived from a peripheral device, and parallel-to-serial conversion on data received from the CPU.
SPRUF94 —C6452 DSP Inter-Integrated Circuit (I2C) Module User's Guide describes theinter-integrated circuit (I2C) peripheral in the C6452 Digital Signal Processor (DSP). The I2Cperipheral provides an interface between the DSP and other devices compliant with the I2C-busspecification and connected by way of an I2C-bus. External components attached to this 2-wireserial bus can transmit and receive up to 8-bit wide data to and from the DSP through the I2Cperipheral. This document assumes the reader is familiar with the I2C-bus specification.
SPRUF95 —C6452 DSP General-Purpose Input/Output (GPIO) User's Guide describes thegeneral-purpose input/output (GPIO) peripheral in the C6452 Digital Signal Processor (DSP). TheGPIO peripheral provides dedicated general-purpose pins that can be configured as either inputs oroutputs. When configured as an input, you can detect the state of the input by reading the state ofan internal register. When configured as an output, you can write to an internal register to controlthe state driven on the output pin.
SPRUF96 —C6452 DSP Telecom Serial Interface Port (TSIP) User's Guide is a multi-link serialinterface consisting of a maximum of two transmit data signals (or links), two receive data signals(or links), two frame sync input signals, and two serial clock inputs. Internally the TSIP offers singlechannel of timeslot data management and single DMA capability that allow individual timeslots tobe selectively processed.
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SPRUF97 —TMS320C6452 DSP 3 Port Switch (3PSW) Ethernet Subsystem User's Guide describesthe operation of the 3 port switch (3PSW) ethernet subsystem in the TMS320C6452 Digital SignalProcessor (DSP). The 3 port switch gigabit ethernet subsystem provides ethernet packetcommunication and can be configured as an ethernet switch. It provides the serial gigabit mediaindependent interface (SGMII), the management data input output (MDIO) for physical layer device(PHY) management.
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1 Introduction
1.1 Purpose of the Peripheral
1.2 Features
User's GuideSPRUF87A – October 2007 – Revised May 2008
Host Port Interface (HPI)
The host port interface (HPI) provides a parallel port interface through which an external host processorcan directly access the TMS320C6452 processor's resources (configuration and program/data memories).The external host device is asynchronous to the CPU clock and functions as a master to the HPI interface.The HPI enables a host device and the C6452 processor to exchange information via internal or externalmemory. Dedicated address (HPIA) and data (HPID) registers within the HPI provide the data pathbetween the external host interface and the processor resources. An HPI control register (HPIC) isavailable to the host and the CPU for various configuration and interrupt functions.
The HPI enables an external host processor (host) to directly access program/data memory on theprocessor using a parallel interface. The primary purpose is to provide a mechanism to move data to andfrom the processor. In addition to data transfer, the host can also use the HPI to bootload the processorby downloading program and data information to the processor's memory after power-up.
The HPI supports the following features:•Multiplexed address/data•Dual 16-bit halfword cycle access (internal data word is 32-bits wide)•32-bit-wide host data bus interface•Internal data bursting using 8-word read and write, first-in first-out (FIFO) buffers•HPI control register (HPIC) accessible by both the DSP CPU and the external host•HPI address register (HPIA) accessible by both the DSP CPU and the external host•Separate HPI address registers for read (HPIAR) and write (HPIAW) with configurable option foroperating as a single HPI address register•HPI data register (HPID)/FIFOs providing data-path between external host interface and CPUresources
•Multiple strobes and control signals to allow flexible host connection•Asynchronous HRDY output to allow the HPI to insert wait states to the host•Software control of data prefetching to the HPID/FIFOs•Processor-to-Host interrupt output signal controlled by HPIC accesses•Host-to-Processor interrupt controlled by HPIC accesses•Memory-mapped peripheral identification register (PID)•Bus holders on host data and address buses (these are actually external to HPI module)
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1.3 Functional Block Diagram
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Figure 1 is a high-level block diagram showing how the HPI connects a host (left side of figure) and theprocessor internal memory (right side of figure). Host activity is asynchronous to the internal processorclock that drives the HPI. The host functions as a master to the HPI. When HPI resources are temporarilybusy or unavailable, the HPI communicates this to the host by de-asserting the HPI ready ( HRDY) outputsignal.
The HPI uses multiplexed operation, meaning the data bus carries both address and data. When the hostdrives an address on the bus, the address is stored in the address register (HPIA) in the HPI, so that thebus can then be used for data.
The HPI supports two interface modes: HPI16 and HPI32 mode. DSP selects either HPI16 or HPI32 modewith the help of HPI_WIDTH device configuration pin at reset.
-16-bit multiplexed mode (HPI16): The HPI is called HPI16 when operating as a 16-bit wide host port. Thismode is selected if the HPI_WIDTH configuration pin of the DSP is sampled low at reset. In this mode, a16-bit data bus (HD[15:0]) carries both addresses and data. HPI16 combines successive 16-bit transfersto provide 32-bit data to the CPU. The halfword identification line (HHWIL) input is used on the HPI16 toidentify the first or second half word of a word transfer.
-32-bit multiplexed mode (HPI32): HPI operates in this mode as a 32-bit wide host port. This mode isselected if the HPI_WIDTH configuration pin of the DSP is sampled high at reset. In this mode, a 32-bitdata bus (HD[31:0]) carries both addresses and data. HHWIL is not applicable for HPI32 mode.
The HPI contains two HPIAs (HPIAR and HPIAW), which can be used as separate address registers forread accesses and write accesses(for details, see Section 2.7.1 ).
A control register (HPIC) is accessible by the CPU and the host. The CPU uses HPIC to send an interruptrequest to the host, to clear an interrupt request from the host, and to configure and monitor the HPI.
Data flow between the host and the HPI uses a temporary storage register, the 32-bit data register (HPID).Data arriving from the host is held in HPID until the data can be stored elsewhere in the processor. Datato be sent to the host is held in HPID until the HPI is ready to perform the transfer. When addressauto-incrementing is used, read and write FIFOs are used to store burst data. If auto-incrementing is notused, the FIFO memory acts as a single register (only one location is used).
Note: To manage data transfers between HPID and the internal memory, the DSP contains dedicated HPIDMA logic. The HPI DMA logic is not programmable. It automatically stores or fetches data using theaddress provided by the host. The HPI DMA logic is independent of the EDMA3 controller included in theDSP.
In the DSP system, master and slave peripherals communicate with each other via the Switched CentralResource (SCR). By definition, master peripherals are capable of initiating read and write transfers in thesystem and may not solely rely on the EDMA3 controller for their data transfers. Slave peripherals rely onthe EDMA3 controller to perform transfers. The HPI is a master peripheral; it uses its DMA logic to directlycommunicate with the rest of the system via the SCR and does not rely on the EDMA3 controller for itsdata transfers. Note that the HPI cannot access all DSP resources or peripherals; see the device-specificdata manual for a list of resources accessible through the HPI.
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