Texas Instruments TMS320C6452 DSP User manual

TMS320C6452 DSPHost Port Interface (HPI)
User's Guide
Literature Number: SPRUF87AOctober 2007 – Revised May 2008

2 SPRUF87A – October 2007 – Revised May 2008Submit Documentation Feedback

Contents
Preface ........................................................................................................................................ 61 Introduction ......................................................................................................................... 91.1 Purpose of the Peripheral ................................................................................................ 91.2 Features .................................................................................................................... 91.3 Functional Block Diagram .............................................................................................. 101.4 Industry Standard(s) Compliance Statement ........................................................................ 111.5 Terminology Used in This Document ................................................................................. 112 Peripheral Architecture ....................................................................................................... 122.1 Clock Control ............................................................................................................. 122.2 Memory Map ............................................................................................................ 122.3 Signal Descriptions ...................................................................................................... 122.4 Pin Multiplexing .......................................................................................................... 122.5 Protocol Description ..................................................................................................... 122.6 Endianness Considerations ............................................................................................ 122.7 Architecture and Operation ............................................................................................. 142.8 Reset Considerations ................................................................................................... 312.9 Initialization ............................................................................................................... 322.10 Interrupt Support ......................................................................................................... 322.11 EDMA Event Support ................................................................................................... 342.12 Power Management ..................................................................................................... 342.13 Emulation Considerations .............................................................................................. 343 Registers ........................................................................................................................... 353.1 Peripheral Identification Register (PID) ............................................................................... 353.2 Power and Emulation Management Register (PWREMU_MGMT) ............................................... 363.3 Host Port Interface Control Register (HPIC) ......................................................................... 373.4 Host Port Interface Write Address Register (HPIAW) .............................................................. 393.5 Host Port Interface Read Address Register (HPIAR) ............................................................... 40
SPRUF87A – October 2007 – Revised May 2008 Table of Contents 3Submit Documentation Feedback

www.ti.com
List of Figures
1 HPI Block Diagram ......................................................................................................... 112 Example of Host-Processor Signal Connections ....................................................................... 153 HPI Strobe and Select Logic .............................................................................................. 164 16-bit Multiplexed-Mode Host Read Cycle .............................................................................. 195 16-bit Multiplexed-Mode Host Write Cycle .............................................................................. 206 Multiplexed-Mode Single-Halfword HPIC Cycle (Read or Write) .................................................... 217 HRDY Behavior During an HPIC or HPIA Read Cycle in the 16-bit Multiplexed Mode ........................... 228 HRDY Behavior During a Data Read Operation in the 16-bit Multiplexed Mode (Case 1: HPIA WriteCycle Followed by Nonauto-increment HPID Read Cycle) ........................................................... 229 HRDY Behavior During a Data Read Operation in the 16-bit Multiplexed Mode (Case 2: HPIA WriteCycle Followed by Auto-increment HPID Read Cycles) .............................................................. 2310 HRDY Behavior During an HPIC Write Cycle in the 16-bit Multiplexed Mode ..................................... 2311 HRDY Behavior During a Data Write Operation in the 16-bit Multiplexed Mode (Case 1:No Auto-incrementing) ..................................................................................................... 2412 HRDY Behavior During a Data Write Operation in the 16-bit Multiplexed Mode (Case 2:Auto-incrementing Selected, FIFO Empty Before Write) .............................................................. 2413 HRDY Behavior During a Data Write Operation in the 16-bit Multiplexed Mode (Case 3:Auto-incrementing Selected, FIFO Not Empty Before Write) ......................................................... 2414 HRDY Behavior During an HPIC or HPIA Read Cycle in the 32-Bit Multiplexed Mode .......................... 2515 HRDY Behavior During a Data Read Operation in the 16-Bit Multiplexed Mode (Case 1: HPIA WriteCycle Followed by Non-auto-increment HPID Read Cycle) .......................................................... 2516 HRDY Behavior During a Data Read Operation in the 32-Bit Multiplexed Mode (Case 2: HPIA WriteCycle Followed by Auto-increment HPID Read Cycles) .............................................................. 2617 HRDY Behavior During an HPIC Write Cycle in the 32-Bit Multiplexed Mode ..................................... 2618 HRDY Behavior During a Data Write Operation in the 32-Bit Multiplexed Mode (Case 1: NoAuto-incrementing) ......................................................................................................... 2719 HRDY Behavior During a Data Write Operation in the 32-Bit Multiplexed Mode (Case 2:Auto-incrementing Selected, FIFO Empty Before Write) .............................................................. 2720 HRDY Behavior During a Data Write Operation in the 32-Bit Multiplexed Mode (Case 3:Auto-incrementing Selected, FIFO Not Empty Before Write) ......................................................... 2821 FIFOs in the HPI ........................................................................................................... 2922 Host-to-CPU Interrupt State Diagram.................................................................................... 3223 CPU-to-Host Interrupt State Diagram.................................................................................... 3324 Peripheral Identification Register (PID) .................................................................................. 3525 Power and Emulation Management Register (PWREMU_MGMT) .................................................. 3626 Host Port Interface Control Register (HPIC) – Owner (Host) Access Permissions................................ 3727 Host Port Interface Control Register (HPIC)–Non-owner (DSP) Access Permissions ............................ 3728 Host Port Interface Write Address Register (HPIAW) ................................................................. 3929 Host Port Interface Read Address Register (HPIAR) ................................................................. 40
List of Figures4 SPRUF87A – October 2007 – Revised May 2008Submit Documentation Feedback

www.ti.com
List of Tables
1 HPI Pins ..................................................................................................................... 132 Options for Connecting Host and HPI Data Strobe Pins .............................................................. 173 Access Types Selectable With the HCNTL Signals ................................................................... 174 Cycle Types Selectable With the HCNTL and HR/ W Signals ........................................................ 185 HPI Registers Relative to Base Address 0200 0030h ................................................................. 356 Peripheral Identification Register (PID) Field Descriptions ........................................................... 357 Power and Emulation Management Register (PWREMU_MGMT) Field Descriptions ............................ 368 Host Port Interface Control Register (HPIC) Field Descriptions ..................................................... 389 Host Port Interface Write Address Register (HPIAW) Field Descriptions ........................................... 3910 Host Port Interface Read Address Register (HPIAR) Field Descriptions ........................................... 40
SPRUF87A – October 2007 – Revised May 2008 List of Tables 5Submit Documentation Feedback

PrefaceSPRUF87A – October 2007 – Revised May 2008
Read This First
About This Manual
This document describes the features and operation of the host port interface (HPI) in the TMS320C6452Digital Signal Processor (DSP).
Notational Conventions
This document uses the following conventions.•Hexadecimal numbers are shown with the suffix h. For example, the following number is 40hexadecimal (decimal 64): 40h.•Registers in this document are shown in figures and described in tables.– Each register figure shows a rectangle divided into fields that represent the fields of the register.Each field is labeled with its bit name, its beginning and ending bit numbers above, and itsread/write properties below. A legend explains the notation used for the properties.– Reserved bits in a register figure designate a bit that is used for future device expansion.
Note: Acronyms 3PSW, CPSW, CPSW_3G, and 3pGSw are interchangeable and all refer to the 3port gigabit switch.
TMS320C6452 DSP
Related Documents From Texas InstrumentsThe following documents describe the TMS320C6452 Digital Signal Processor (DSP). Copies of thesedocuments are available on the Internet at www.ti.com .Tip: Enter the literature number in the search boxprovided at www.ti.com .
Data Manual—
SPRS371 —TMS320C6452 Digital Signal Processor Data Manual describes the signals, specificationsand electrical characteristics of the device.
CPU—
SPRU732 —TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide describes the CPUarchitecture, pipeline, instruction set, and interrupts for the TMS320C64x and TMS320C64x+ digitalsignal processors (DSPs) of the TMS320C6000 DSP family. The C64x/C64x+ DSP generationcomprises fixed-point devices in the C6000 DSP platform. The C64x+ DSP is an enhancement ofthe C64x DSP with added functionality and an expanded instruction set.
Reference Guides—SPRUF85 —C6452 DSP DDR2 Memory Controller User's Guide describes the DDR2 memorycontroller in the TMS320C6452 Digital Signal Processor (DSP). The DDR2/mDDR memorycontroller is used to interface with JESD79D-2A standard compliant DDR2 SDRAM devices andstandard Mobile DDR SDRAM devices.
6Preface SPRUF87A – October 2007 – Revised May 2008Submit Documentation Feedback

www.ti.com TMS320C6452 DSP
SPRUF86 —C6452 Peripheral Component Interconnect (PCI) User's Guide describes the peripheralcomponent interconnect (PCI) port in the TMS320C6452 Digital Signal Processor (DSP). The PCIport supports connection of the C642x DSP to a PCI host via the integrated PCI master/slave businterface. The PCI port interfaces to the DSP via the enhanced DMA (EDMA) controller. Thisarchitecture allows for both PCI master and slave transactions, while keeping the EDMA channelresources available for other applications.
SPRUF87 —C6452 DSP Host Port Interface (UHPI) User's Guide describes the host port interface(HPI) in the TMS320C6452 Digital Signal Processor (DSP). The HPI is a parallel port through whicha host processor can directly access the CPU memory space. The host device functions as amaster to the interface, which increases ease of access. The host and CPU can exchangeinformation via internal or external memory. The host also has direct access to memory-mappedperipherals. Connectivity to the CPU memory space is provided through the enhanced directmemory access (EDMA) controller.
SPRUF89 —C6452 DSP VLYNQ Port User's Guide describes the VLYNQ port in the TMS320C6452Digital Signal Processor (DSP). The VLYNQ port is a high-speed point-to-point serial interface forconnecting to host processors and other VLYNQ compatible devices. It is a full-duplex serial buswhere transmit and receive operations occur separately and simultaneously without interference.
SPRUF90 —C6452 DSP 64-Bit Timer User's Guide describes the operation of the 64-bit timer in theC6452 Digital Signal Processor (DSP). The timer can be configured as a general-purpose 64-bittimer, dual general-purpose 32-bit timers, or a watchdog timer.
SPRUF91 —C6452 DSP Multichannel Audio Serial Port (McASP) User's Guide describes themultichannel audio serial port (McASP) in the C6452 Digital Signal Processor (DSP). The McASPfunctions as a general-purpose audio serial port optimized for the needs of multichannel audioapplications. The McASP is useful for time-division multiplexed (TDM) stream, Inter-IntegratedSound (I2S) protocols, and intercomponent digital audio interface transmission (DIT).
SPRUF92 —C6452 DSP Serial Port Interface (SPI) User's Guide discusses the Serial Port Interface(SPI) in the C6452 Digital Signal Processor (DSP). This reference guide provides the specificationsfor a 16-bit configurable, synchronous serial peripheral interface. The SPI is a programmable-lengthshift register, used for high speed communication between external peripherals or other DSPs.
SPRUF93 —C6452 DSP Universal Asynchronous Receiver/Transmitter (UART) User's Guidedescribes the universal asynchronous receiver/transmitter (UART) peripheral in the C6452 DigitalSignal Processor (DSP). The UART peripheral performs serial-to-parallel conversion on datareceived from a peripheral device, and parallel-to-serial conversion on data received from the CPU.
SPRUF94 —C6452 DSP Inter-Integrated Circuit (I2C) Module User's Guide describes theinter-integrated circuit (I2C) peripheral in the C6452 Digital Signal Processor (DSP). The I2Cperipheral provides an interface between the DSP and other devices compliant with the I2C-busspecification and connected by way of an I2C-bus. External components attached to this 2-wireserial bus can transmit and receive up to 8-bit wide data to and from the DSP through the I2Cperipheral. This document assumes the reader is familiar with the I2C-bus specification.
SPRUF95 —C6452 DSP General-Purpose Input/Output (GPIO) User's Guide describes thegeneral-purpose input/output (GPIO) peripheral in the C6452 Digital Signal Processor (DSP). TheGPIO peripheral provides dedicated general-purpose pins that can be configured as either inputs oroutputs. When configured as an input, you can detect the state of the input by reading the state ofan internal register. When configured as an output, you can write to an internal register to controlthe state driven on the output pin.
SPRUF96 —C6452 DSP Telecom Serial Interface Port (TSIP) User's Guide is a multi-link serialinterface consisting of a maximum of two transmit data signals (or links), two receive data signals(or links), two frame sync input signals, and two serial clock inputs. Internally the TSIP offers singlechannel of timeslot data management and single DMA capability that allow individual timeslots tobe selectively processed.
SPRUF87A – October 2007 – Revised May 2008 Read This First 7Submit Documentation Feedback

TMS320C6452 DSP www.ti.com
SPRUF97 —TMS320C6452 DSP 3 Port Switch (3PSW) Ethernet Subsystem User's Guide describesthe operation of the 3 port switch (3PSW) ethernet subsystem in the TMS320C6452 Digital SignalProcessor (DSP). The 3 port switch gigabit ethernet subsystem provides ethernet packetcommunication and can be configured as an ethernet switch. It provides the serial gigabit mediaindependent interface (SGMII), the management data input output (MDIO) for physical layer device(PHY) management.
Read This First8 SPRUF87A – October 2007 – Revised May 2008Submit Documentation Feedback

1 Introduction
1.1 Purpose of the Peripheral
1.2 Features
User's GuideSPRUF87A – October 2007 – Revised May 2008
Host Port Interface (HPI)
The host port interface (HPI) provides a parallel port interface through which an external host processorcan directly access the TMS320C6452 processor's resources (configuration and program/data memories).The external host device is asynchronous to the CPU clock and functions as a master to the HPI interface.The HPI enables a host device and the C6452 processor to exchange information via internal or externalmemory. Dedicated address (HPIA) and data (HPID) registers within the HPI provide the data pathbetween the external host interface and the processor resources. An HPI control register (HPIC) isavailable to the host and the CPU for various configuration and interrupt functions.
The HPI enables an external host processor (host) to directly access program/data memory on theprocessor using a parallel interface. The primary purpose is to provide a mechanism to move data to andfrom the processor. In addition to data transfer, the host can also use the HPI to bootload the processorby downloading program and data information to the processor's memory after power-up.
The HPI supports the following features:•Multiplexed address/data•Dual 16-bit halfword cycle access (internal data word is 32-bits wide)•32-bit-wide host data bus interface•Internal data bursting using 8-word read and write, first-in first-out (FIFO) buffers•HPI control register (HPIC) accessible by both the DSP CPU and the external host•HPI address register (HPIA) accessible by both the DSP CPU and the external host•Separate HPI address registers for read (HPIAR) and write (HPIAW) with configurable option foroperating as a single HPI address register•HPI data register (HPID)/FIFOs providing data-path between external host interface and CPUresources
•Multiple strobes and control signals to allow flexible host connection•Asynchronous HRDY output to allow the HPI to insert wait states to the host•Software control of data prefetching to the HPID/FIFOs•Processor-to-Host interrupt output signal controlled by HPIC accesses•Host-to-Processor interrupt controlled by HPIC accesses•Memory-mapped peripheral identification register (PID)•Bus holders on host data and address buses (these are actually external to HPI module)
SPRUF87A – October 2007 – Revised May 2008 Host Port Interface (HPI) 9Submit Documentation Feedback

1.3 Functional Block Diagram
Introduction www.ti.com
Figure 1 is a high-level block diagram showing how the HPI connects a host (left side of figure) and theprocessor internal memory (right side of figure). Host activity is asynchronous to the internal processorclock that drives the HPI. The host functions as a master to the HPI. When HPI resources are temporarilybusy or unavailable, the HPI communicates this to the host by de-asserting the HPI ready ( HRDY) outputsignal.
The HPI uses multiplexed operation, meaning the data bus carries both address and data. When the hostdrives an address on the bus, the address is stored in the address register (HPIA) in the HPI, so that thebus can then be used for data.
The HPI supports two interface modes: HPI16 and HPI32 mode. DSP selects either HPI16 or HPI32 modewith the help of HPI_WIDTH device configuration pin at reset.
-16-bit multiplexed mode (HPI16): The HPI is called HPI16 when operating as a 16-bit wide host port. Thismode is selected if the HPI_WIDTH configuration pin of the DSP is sampled low at reset. In this mode, a16-bit data bus (HD[15:0]) carries both addresses and data. HPI16 combines successive 16-bit transfersto provide 32-bit data to the CPU. The halfword identification line (HHWIL) input is used on the HPI16 toidentify the first or second half word of a word transfer.
-32-bit multiplexed mode (HPI32): HPI operates in this mode as a 32-bit wide host port. This mode isselected if the HPI_WIDTH configuration pin of the DSP is sampled high at reset. In this mode, a 32-bitdata bus (HD[31:0]) carries both addresses and data. HHWIL is not applicable for HPI32 mode.
The HPI contains two HPIAs (HPIAR and HPIAW), which can be used as separate address registers forread accesses and write accesses(for details, see Section 2.7.1 ).
A control register (HPIC) is accessible by the CPU and the host. The CPU uses HPIC to send an interruptrequest to the host, to clear an interrupt request from the host, and to configure and monitor the HPI.
Data flow between the host and the HPI uses a temporary storage register, the 32-bit data register (HPID).Data arriving from the host is held in HPID until the data can be stored elsewhere in the processor. Datato be sent to the host is held in HPID until the HPI is ready to perform the transfer. When addressauto-incrementing is used, read and write FIFOs are used to store burst data. If auto-incrementing is notused, the FIFO memory acts as a single register (only one location is used).
Note: To manage data transfers between HPID and the internal memory, the DSP contains dedicated HPIDMA logic. The HPI DMA logic is not programmable. It automatically stores or fetches data using theaddress provided by the host. The HPI DMA logic is independent of the EDMA3 controller included in theDSP.
In the DSP system, master and slave peripherals communicate with each other via the Switched CentralResource (SCR). By definition, master peripherals are capable of initiating read and write transfers in thesystem and may not solely rely on the EDMA3 controller for their data transfers. Slave peripherals rely onthe EDMA3 controller to perform transfers. The HPI is a master peripheral; it uses its DMA logic to directlycommunicate with the rest of the system via the SCR and does not rely on the EDMA3 controller for itsdata transfers. Note that the HPI cannot access all DSP resources or peripherals; see the device-specificdata manual for a list of resources accessible through the HPI.
Host Port Interface (HPI)10 SPRUF87A – October 2007 – Revised May 2008Submit Documentation Feedback

HPID
R/W FIFOs
HPIA
Increment
HPIC
Access
type
HD[15:0]
HDS1, HDS2
HR/W
HAS
HCNTL0
HCNTL1
HINT
HRDY
HPI
Host
Data
Address
or I/O
R/W
Data
strobes
IRQ
Ready
CPU
HCSChip select
Processor
memory
HPI DMA logic
Processor
HHWIL
high
Logic
1.4 Industry Standard(s) Compliance Statement
1.5 Terminology Used in This Document
www.ti.com Introduction
Figure 1. HPI Block Diagram
The HPI is not an industry standard interface that is developed and monitored by an internationalorganization. It is a generic parallel interface that can be configured to gluelessly interface, a variety ofparallel devices.
The following is a brief explanation of some terms used in this document:
Term MeaningCPU DSP CPUhost External host deviceHPI DMA logic Logic used to communicate between the HPI and the DMA system that moves data toand from memory. This is independent of the EDMA system on the processorprocessor the entire digital media system-on-chip
SPRUF87A – October 2007 – Revised May 2008 Host Port Interface (HPI) 11Submit Documentation Feedback

2 Peripheral Architecture
2.1 Clock Control
2.2 Memory Map
2.3 Signal Descriptions
2.4 Pin Multiplexing
2.5 Protocol Description
2.6 Endianness Considerations
Peripheral Architecture www.ti.com
The HPI clock is derived from SYSCLK2, which is the PLL1 clock divided by 6. For detailed information onthe PLLs and clock distribution on the processor, see the Subsystem User's Guide.
The HPI can be used by the host to access the following processor resources:•HPI configuration registers•Most on-chip device memory, peripherals, and memory-mapped registers (see Section 4, SystemInterconnect, in the device-specific data manual for more detailed information)•DDR2 Memory Controller configuration register file and memory address ranges•Power and Sleep Controller (PSC) registers•PLL1 and PLL2 registers
Consult the device-specific data manual for the memory address ranges of the above resources.
Table 1 shows the a description of the HPI signals.
On the C6452 extensive pin multiplexing is used to accommodate the largest number of peripheralfunctions in the smallest possible package. Pin multiplexing is controlled using a combination of hardwareconfiguration at device reset and software programmable register settings. UHPI pins are multiplexed withPCI pins' functionality. The configuration pin UHPIEN is to be set to 1 to enable UHPI. Refer to thedevice-specific data manual to determine how pin multiplexing affects the HPI.
The HPI does not conform to any industry standard protocol. Details on the nature of address, data andcontrol transactions are found in the following sections.
The HPI operation is independent of the C6452 endianness mode; therefore, there are no endiannessconsiderations for the HPI.
Host Port Interface (HPI)12 SPRUF87A – October 2007 – Revised May 2008Submit Documentation Feedback

www.ti.com Peripheral Architecture
Table 1. HPI Pins
Pin Type Host Connection Function
HCNTL[1:0] I Address or control pins HPI access control inputs. The HPI latches the logic levels of these pinson the falling edge of internal HSTRB (for details about internal HSTRB,see Section 2.7.4 ). The four binary states of these pins determine theaccess type of the current transfer (HPIC, HPIA, HPID with and withoutauto-incrementing).HCS I Chip select pin HPI chip select. HCS must be low for the HPI to be selected by the host.HCS can be kept low between accesses. HCS normally precedes anactive HDS (data strobe) signal, but can be connected to an HDS pin forsimultaneous select and strobe activity.HR/ W I R/W strobe pin HPI read/write. On the falling edge of internal HSTRB, HR/ W indicateswhether the current access is to be a read or write operation. DrivingHR/ W high indicates the transfer is a read from the HPI, while drivingHR/ W low indicates a write to the HPI.HHWIL I Address or control pins Halfword identification line. The host uses HHWIL to identify the firstand second halfwords of the host cycle. HHWIL must be driven low for thefirst halfword and high for the second halfword.HAS I None Address strobe. Connect to logic high.HINT O/Z Interrupt pin Host Interrupt. The CPU can interrupt the host processor by writing a 1to the HINT bit of HPIC. Before subsequent HINT interrupts can occur,the host must acknowledge interrupts by writing a 1 to the HINT bit. Thispin is active-low (that is, when an interrupt is asserted from the host, thestate of this signal is low) and inverted from the HINT bit value in HPIC.HDS1 and I Read strobe and write HPI data strobe pins. These pins are used for strobing data in and out ofHDS2 strobe pins or any data the HPI (for data strobing details, see Section 2.7.4 ). The direction of thestrobe pin data transfer depends on the logic level of the HR/ W signal. The HDSsignals are also used to latch control information on the falling edge.During an HPID write access, data is latched into the HPID register on therising edge of HDS. During read operations, these pins act asoutput-enable pins of the host data bus.HD[31:0] I/O/Z Data bus HPI data bus. The HPI data bus carries the address and data to/from theHD[15:0] HPI. HD[31:0] applies to HPI32 and HD[15:0] applies to HPI16.HRDY O/Z Asynchronous ready pin HPI-ready signal. When the HPI drives HRDY low, the host haspermission to complete the current host cycle. When the HPI drivesHRDY high, the HPI is not ready for the current host cycle to complete.HINT O/Z Interrupt pin The DSP can interrupt the host processor by writing a 1 to the HINT bit ofHPIC. Before subsequent HINT interrupts can occur, the host must clearprevious interrupts by writing a 1 to the HINT bit. This pin is active-lowand inverted from the HINT bit value in HPIC.
SPRUF87A – October 2007 – Revised May 2008 Host Port Interface (HPI) 13Submit Documentation Feedback

2.7 Architecture and Operation
2.7.1 Using the Address Registers
2.7.1.1 Single-HPIA Mode
2.7.1.2 Dual-HPIA Mode
Peripheral Architecture www.ti.com
The HPI contains two 32-bit address registers: one for read operations (HPIAR) and one for writeoperations (HPIAW). These roles are unchanging from the viewpoint of the HPI logic. The HPI DMA logicgets the address from HPIAR when reading from processor resources (see Section 2.2 ) and gets theaddress from HPIAW when writing to processor resources (see Section 2.2 ).
However, unlike the HPI logic, the host can choose how to interact with the two HPI address registers.Using the DUALHPIA bit in the HPI control register (HPIC), the host determines whether HPIAR andHPIAW act as a single 32-bit register (single-HPIA mode) or as two independent 32-bit registers(dual-HPIA mode).
Note: The addresses loaded into the HPI address registers must be word addresses, and must be32-bit word aligned (with the least-significant two bits equal to zero), for use in addressingmemory space within the C6452. For example, to access L2 SRAM at 0x00A0_0000, HPIAshould be loaded with 0x0028_0000 (0x00A0_0000 divided by 4).
When DUALHPIA = 0 in HPIC, HPIAR and HPIAW become a single HPI address register (HPIA) from theperspective of the host. In this mode:•A host HPIA write cycle (HCNTL[1:0] = 10b, HR/ W = 0) updates HPIAR and HPIAW with the samevalue.
•Both HPI address registers are incremented during auto-increment read/write cycles(HCNTL[1:0] = 01b).•An HPIA read cycle (HCNTL[1:0] = 10b, HR/ W = 1) returns the content of HPIAR, which should beidentical to the content of HPIAW.
To maintain consistency between the contents of HPIAR and HPIAW, the host should always reinitializethe HPI address registers after changing the state of the DUALHPIA bit. In addition, when DUALHPIA = 0,the host must always reinitialize the HPI address registers when it changes the data direction (from anHPID read cycle to an HPID write cycle, or conversely). Otherwise, the memory location accessed by theHPI DMA logic might not be the location intended by the host.
When DUALHPIA = 1 in HPIC, HPIAR and HPIAW are two independent HPI address registers from theperspective of the host. In this mode:•A host HPIA access (HCNTL[1:0] = 10b) reads/updates either HPIAR or HPIAW, depending on thevalue of the HPIA read/write select (HPIASEL) bit in HPIC. This bit is programmed by the host. WhileHPIASEL = 1, only HPIAR is read or updated by the host. While HPIASEL = 0, only HPIAW is read orupdated by the host. The HPIASEL bit is only meaningful in the dual-HPIA mode.
Note: The HPIASEL bit does not affect the HPI DMA logic. Regardless of the value of HPIASEL,the HPI DMA logic uses HPIAR when reading from memory and HPIAW when writing tomemory.
•A host HPID access with auto-incrementing (HCNTL[1:0] = 01b) causes only the relevant HPIA valueto be incremented to the next consecutive memory address. In an auto-increment read cycle, HPIAR isincremented after it has been used to perform the current read from memory. In an auto-incrementwrite cycle, HPIAW is incremented after it has been used for the write operation.
Host Port Interface (HPI)14 SPRUF87A – October 2007 – Revised May 2008Submit Documentation Feedback

2.7.2 Host-HPI Signal Connections
Host
Address
or I/O
Read/Write
Processor
HPI
Logic high
2
Chip select
Data strobe 1
Data strobe
HAS
HCNTL[1:0]
HHWIL
HR/W
HCS
HDS1
HDS2 (A)
32 HD[15:0]
Data
Ready HRDY
Interrupt HINT
2.7.3 HPI Configuration and Data Flow
www.ti.com Peripheral Architecture
Figure 2 shows an example of a signal connection between the HPI and a host.
Figure 2. Example of Host-Processor Signal Connections
A Data strobing options are given in Section 2.7.4
The host accomplishes a multiplexed access in the following manner:1. The host writes to the HPI control register (HPIC) to properly configure the HPI. Typically, this meansprogramming the halfword order bit (HWOB) and the HPIA-related bits (DUALHPIA and HPIASEL).This step is normally performed once before the initial data access.2. The host writes the desired internal processor memory address to an address register (HPIAR and/orHPIAW). For an introduction to the two HPI address registers and the two ways the host can interactwith them, see Section 2.7.1 .3. The host reads from or writes to the data register (HPID). Data transfers between HPID and theinternal memory of the processor are handled by the HPI DMA logic and are transparent to the CPU.
Each step of the access uses the same bus. Therefore, the host must drive the appropriate levels on theHCNTL1 and HCNTL0 signals to indicate which register is to be accessed. The host must also drive theappropriate level on the HR/ W signal to indicate the data direction (read or write) and must drive othercontrol signals as appropriate. When HPI resources are temporarily busy or unavailable, the HPI cancommunicate this to the host by de-asserting the HPI-ready ( HRDY) output signal.
When performing an access, the HPI first latches the levels on HCNTL[1:0], HR/ W, and other controlsignals. This latching can occur on the falling edge of the internal strobe signal (for details, seeSection 2.7.4 ). After the control information is latched, the HPI initiates an access based on the controlsignals.
SPRUF87A – October 2007 – Revised May 2008 Host Port Interface (HPI) 15Submit Documentation Feedback

2.7.4 HDS2, HDS1, and HCS: Data Strobing and Chip Selection
HDS1
HDS2
HCS
HRDY
Internal
HSTRB
Internal
HRDY
Peripheral Architecture www.ti.com
If the host wants to read data from processor resources (see Section 2.2 ), the HPI DMA logic reads theresource address from HPIAR and retrieves the data from the addressed memory location. When the datahas been placed in HPID, the HPI drives the data onto its HD bus. The HRDY signal informs the hostwhether the data on the HD bus is valid ( HRDY low) or not valid yet ( HRDY high). When the data is valid,the host should latch the data and drive the connected data strobe ( HDS1 or HDS2) inactive, which, inturn, will cause the internal strobe (internal HSTRB) signal to transition from low to high.
If the host wants to write data to processor resources (see Section 2.2 ), the operation is similar. After thehost determines that the HPI is ready to latch the data ( HRDY is low), it must cause internal HSTRB totransition from low to high, which causes the data to be latched into HPID. Once the data is in HPID, theHPI DMA logic reads the memory address from HPIAW and transfers the data from HPID to theaddressed memory location.
As shown in Figure 3 , the strobing logic is a function of three key inputs: the chip select pin ( HCS) and twodata strobe signals ( HDS1 and HDS2). The internal strobe signal, which is referred to as internal HSTRBthroughout this document, functions as the actual strobe signal inside the HPI. HCS must be low (HPIselected) during strobe activity on the HDS pins. If HCS remains high (HPI not selected), activity on theHDS pins is ignored.
Figure 3. HPI Strobe and Select Logic
Strobe connections between the host and the HPI depend in part on the number and types of strobe pinsavailable on the host. Table 2 describes some options for connecting to the HDS pins.
Notice in Figure 3 that HRDY is also gated by HCS. If HCS goes high (HPI not selected), HRDY goes low,regardless of whether the current internal transfer is completed in the processor.
Note: The HCS input and one HDS strobe input can be tied together and driven with a singlestrobe signal from the host. This technique selects the HPI and provides the strobe,simultaneously. When using this method, be aware that HRDY is gated by HCS aspreviously described.
It is not recommended to tie both HDS1 and HDS2 to static logic levels and use HCS as astrobe.
Host Port Interface (HPI)16 SPRUF87A – October 2007 – Revised May 2008Submit Documentation Feedback

2.7.5 HCNTL[1:0] and HR/ W: Indicating the Cycle Type
www.ti.com Peripheral Architecture
Table 2. Options for Connecting Host and HPI Data Strobe Pins
Available Host Data Strobe Pins Connections to HPI Data Strobe Pins
Host has separate read and write strobe Connect one strobe pin to HDS1 and the other to HDS2
(1)
. Since such a host might notpins, both active-low provide a R/ W line, take care to satisfy HR/ W timings as stated in the device datamanual. This could possibly be done using a host address line.Host has separate read and write strobe Connect one strobe pin to HDS1 and the other to HDS2
(1)
. Since such a host might notpins, both active-high provide a R/ W line, take care to satisfy HR/ W timings as stated in the device datamanual. This could possibly be done using a host address line.Host has one active-low strobe pin Connect the strobe pin to HDS1 or HDS2, and connect the other pin to logic-level 1.Host has one active-high strobe pin Connect the strobe pin to HDS1 or HDS2, and connect the other strobe pin tologic-level 0.(1)
The HR/ W signal could be driven by a host address line in this case.
The cycle type consists of:•The access type that the host selects by driving the appropriate levels on the HCNTL[1:0] pins of theHPI. Table 3 describes the four available access types.•The transfer direction that the host selects with the HR/ W pin. The host must drive the HR/ W signalhigh (read) or low (write).
A summary of cycle types is in Table 4 . The HPI samples the HCNTL levels at the falling edge of theinternal strobe signal HSTRB.
Table 3. Access Types Selectable With the HCNTL Signals
HCNTL1
(1)
HCNTL0
(1)
Access Type
0 0 HPIC access. The host requests to access the HPI control register (HPIC).0 1 HPID access with auto-incrementing. The host requests to access the HPI dataregister (HPID) and to have the appropriate HPI address register (HPIAR and/or HPIAW)automatically incremented by 1 after the access.1 0 HPIA access. The host requests to access the appropriate HPI address register (HPIARand/or HPIAW).1 1 HPID access without auto-incrementing. The host requests to access the HPI dataregister (HPID) but requests no automatic post-increment of the HPI address register.(1)
Note that the encoding of HCNTL0 and HCNTL1 for the different types of HPI accesses varies on many TI DSPs; therefore, youshould use caution to ensure that the correct encoding of these inputs is used for your device. The encoding of these signals asdescribed in this document applies only to the C6452.
SPRUF87A – October 2007 – Revised May 2008 Host Port Interface (HPI) 17Submit Documentation Feedback

2.7.6 HHWIL: Identifying the First and Second Halfwords in Multiplexed Mode Transfers
Peripheral Architecture www.ti.com
Table 4. Cycle Types Selectable With the HCNTL and HR/ W Signals
HCNTL1
(1)
HCNTL0
(1)
HR/ W Cycle Type
0 0 0 HPIC write cycle0 0 1 HPIC read cycle0 1 0 HPID write cycle with auto-incrementing0 1 1 HPID read cycle with auto-incrementing1 0 0 HPIA write cycle1 0 1 HPIA read cycle1 1 0 HPID write cycle without auto-incrementing1 1 1 HPID read cycle without auto-incrementing(1)
Note that the encoding of HCNTL0 and HCNTL1 for the different types of HPI accesses varies on many TI DSPs; therefore, youshould use caution to ensure that the correct encoding of these inputs is used for your device. The encoding of these signals asdescribed in this document applies only to the C6452.
Each host cycle consists of two consecutive halfword transfers. For each transfer, the host must specifythe cycle type with HCNTL[1:0] and HR/ W, and the host must use HHWIL to indicate whether the first orsecond halfword is being transferred. For HPID and HPIA accesses, HHWIL must always be driven low forthe first halfword transfer and high for the second halfword transfer. Results are undefined if the sequenceis broken. For examples of using HHWIL, see Section 2.7.7 .
When the host sends the two halfwords of a 32-bit word in this manner, the host can send themost-significant and the least-significant halfwords of the word in either order (most-significant halfwordfirst or most-significant halfword second). However, the host must inform the HPI of the selected orderbefore beginning the host cycle. This is done by programming the halfword order (HWOB) bit in HPIC.Although HWOB is written at bit 0 in HPIC, its current value is readable at both bit 0 and bit 8(HWOBSTAT). Thus, the host can determine the current halfword order configuration by checking theleast-significant bit of either half of HPIC.
There is one case when the HPI does not require a dual halfword access with HHWIL low for the firsthalfword and HHWIL high for the second halfword. This is the case when accessing the HPIC register.When accessing HPIC, the state of HHWIL is ignored and the same 16-bit HPIC register is accessedregardless of whether the host performs a single or dual access. For an example timing diagram of thiscase, see Section 2.7.8 .
18 Host Port Interface (HPI) SPRUF87A – October 2007 – Revised May 2008Submit Documentation Feedback

2.7.7 Performing a Multiplexed Access
Data 2Data 1
HCS
HSTRB
HR/W
HCNTL[1:0]
HD[15:0]
HRDY
HHWIL
Internal
HPI latches
control information Host latches data HPI latches control information Host latches data
www.ti.com Peripheral Architecture
Figure 2 shows an example of signal connections for multiplexed transfers. Figure 4 and Figure 5 showtypical HPI signal activity when performing a read and write transfer, respectively. In these cases, thefalling edge of internal HSTRB is used to latch the HCNTL[1:0], HR/ W, and HHWIL states into the HPI.Internal HSTRB is derived from HCS, HDS1, and HDS2 as described in Section 2.7.4 .
Figure 4. 16-bit Multiplexed-Mode Host Read Cycle
NOTE: Depending on the type of write operation (HPID without auto-incrementing, HPIA, HPIC, or HPID withauto-incrementing) and the state of the FIFO, transitions on HRDY may or may not occur. For more information, seeSection 2.7.9 .
SPRUF87A – October 2007 – Revised May 2008 Host Port Interface (HPI) 19Submit Documentation Feedback

HCS
HSTRB
HRDY
HR/W
HCNTL[1:0]
HHWIL
Data 1 Data 2
HD[15:0]
Internal
HPI latches
control information
HPI latches
data
HPI latches
control information
HPI latches
data
Peripheral Architecture www.ti.com
Figure 5. 16-bit Multiplexed-Mode Host Write Cycle
NOTE: Depending on the type of write operation (HPID without auto-incrementing, HPIA, HPIC, or HPID withauto-incrementing) and the state of the FIFO, transitions on HRDY may or may not occur. For more information, seeSection 2.7.9 .
20 Host Port Interface (HPI) SPRUF87A – October 2007 – Revised May 2008Submit Documentation Feedback