Texas Instruments LMK05028 Owner's manual

LMK05028
High-performance Network Synchronizer
Output
Dividers
Hitless Switching
with priority
Output
Buffers
68
4
Power
Conditioning
Device Control
I2C/SPI/Pin mode
EEPROM/ROM
TCXO/OCXO
(Optional)
PLL Core 1
PLL Core 2
XO
Copyright © 2018, Texas Instruments Incorporated
VDD,VDDO
Logic I/O
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to
change without notice.
LMK05028
SNAS724 –FEBRUARY 2018
LMK05028 Low-Jitter Dual Channel Clock Synchronizer With Eight Outputs and Integrated
EEPROM
1
1 Features
1• Two Independent PLL Cores, Each Featuring:
– Jitter: 150-fs RMS for Outputs ≥100 MHz
– Phase Noise: –102 dBc/Hz at 100-Hz Offset
for 122.88 MHz
– Hitless Switching: 50-ps Phase Transient With
Phase Cancellation
– Programmable Loop Bandwidth With Fastlock
– Standards-Compliant Synchronization and
Holdover Using a Low-Cost TCXO/OCXO
– Any Input to Any Output Frequency Translation
• Four Reference Clock Inputs
– Priority-Based Input Selection (Auto or
Manual)
– Digital Holdover on Loss of Reference
• Eight Clock Outputs With Programmable Drivers
– Up to Six Different Output Frequencies
– AC-LVDS, AC-CML, AC-LVPECL, HCSL, and
1.8-V or 2.5-V LVCMOS Output Formats
• EEPROM/ROM for Custom Startup Clock
Profiles(2)
• Flexible Configuration Options
– 1 Hz (1 PPS) to 750 MHz on Input and Output
– XO: 10 to 100 MHz, TCXO: 10 to 54 MHz
– DCO Mode: < 1 ppt/Step for Fine Frequency
and Phase Steering (IEEE 1588 Slave
Operation)
– Zero Delay for Deterministic Phase Offset
– Robust Clock Monitoring and Status
– I2C or SPI Interface
• Excellent Power Supply Noise Rejection
• Supply: 3.3-V Core With 1.8-V, 2.5-V, or 3.3-V
Output
• Industrial Temperature Range: –40°C to +85°C
2 Applications
• SyncE (G.8262), SONET/SDH (Stratum 3/3E,
G.813, GR-1244, GR-253), IEEE 1588 (PTP)
Slave Clock, or Optical Transport Network (G.709)
Synchronization
• Telecom and Enterprise Line Cards
• Wireless Base Station (BTS)
• Test and Measurement, Broadcast Video, and
Medical Ultrasound
• Jitter and Wander Attenuation, Precise Frequency
Translation, and Low-Jitter Clock Generation for
FPGA, DSP, ASIC, and CPU Devices.
3 Description
The LMK05028 device is a high-performance clock
generator, jitter cleaner, and clock synchronizer with
advanced reference clock selection and hitless
switching to meet the stringent requirements of
communications infrastructure applications. The ultra-
low jitter reduces bit error rates (BER) in high-speed
serial links.
The device has two independent PLL cores that can
each synchronize or lock to one of four reference
clock inputs, and the LMK05028 can generate up to
eight output clocks with up to six different
frequencies.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
LMK05028 VQFN (64) 9.00 mm × 9.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
(2) Contact TI Field Sales to inquire about custom factory pre-
programmed devices.
LMK05028 Simplified Block Diagram

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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description............................................................. 1
4 Revision History..................................................... 2
5 Description (continued)......................................... 3
6 Pin Configuration and Functions......................... 4
7 Specifications......................................................... 7
7.1 Absolute Maximum Ratings ...................................... 7
7.2 ESD Ratings.............................................................. 7
7.3 Recommended Operating Conditions....................... 8
7.4 Thermal Information.................................................. 8
7.5 Power Supply Characteristics................................... 8
7.6 Clock Input Characteristics (INx_P/N) ...................... 9
7.7 XO Input Characteristics (XO_P/N) .......................... 9
7.8 TCXO/OCXO Input Characteristics (TCXO_IN)...... 10
7.9 APLL/VCO Characteristics...................................... 10
7.10 2.5-V LVCMOS Output Characteristics
(OUTx_P/N) ............................................................. 10
7.11 1.8-V LVCMOS Output Characteristics
(OUTx_P/N) ............................................................. 10
7.12 AC-LVDS Output Characteristics (OUTx_P/N)..... 11
7.13 AC-CML Output Characteristics (OUTx_P/N)....... 11
7.14 AC-LVPECL Output Characteristics (OUTx_P/N). 12
7.15 HCSL Output Characteristics (OUTx_P/N)........... 12
7.16 2-Level Logic Input Characteristics (PDN,
GPIO[6:0], INSELx_[1:0])......................................... 12
7.17 3-Level Logic Input Characteristics
(HW_SW_CTRL, STATUS[1:0]) .............................. 12
7.18 Logic Output Characteristics (STATUS[1:0],
GPIO[6:5], GPIO2/SDO).......................................... 13
7.19 I2C Interface Characteristics (SDA, SCL)............. 13
7.20 SPI Timing Requirements (SDA, SCL, GPIO1/SCS,
GPIO2/SDO)............................................................ 13
7.21 Other Characteristics ............................................ 14
7.22 PLL Clock Output Performance Characteristics ... 14
7.23 Timing Diagrams................................................... 15
8 Parameter Measurement Information ................ 17
8.1 Test Configuration................................................... 17
9 Detailed Description............................................ 20
9.1 Overview................................................................. 20
9.2 Functional Block Diagrams ..................................... 21
9.3 Feature Description................................................. 21
9.4 Device Functional Modes........................................ 36
9.5 Programming .......................................................... 38
10 Application and Implementation........................ 44
10.1 Application Information.......................................... 44
10.2 Typical Application ............................................... 47
10.3 Do's and Don'ts..................................................... 51
11 Power Supply Recommendations ..................... 52
11.1 Power Supply Bypassing ...................................... 52
12 Layout................................................................... 52
12.1 Layout Guidelines ................................................. 52
12.2 Layout Example .................................................... 53
12.3 Thermal Reliability................................................. 53
13 Device and Documentation Support................. 54
13.1 Receiving Notification of Documentation Updates 54
13.2 Community Resources.......................................... 54
13.3 Trademarks........................................................... 54
13.4 Electrostatic Discharge Caution............................ 54
13.5 Glossary................................................................ 54
14 Mechanical, Packaging, and Orderable
Information........................................................... 54
4 Revision History
DATE REVISION NOTES
February 2018 * Initial release.

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Offset Frequency (Hz)
Phase Noise (dBc/Hz)
100 1000 10000 100000 1000000 10000000
-170
-160
-150
-140
-130
-120
-110
-100
-90
-80
D001
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5 Description (continued)
The flexible PLL cores provide programmable loop bandwidth for input jitter and wander attenuation and
fractional frequency translation to generate any output frequency from any input frequency. Each PLL core has
up to 3 feedback loops with two digital PLLs (DPLLs) and one analog PLL (APLL) with integrated VCO. Each
core supports 3 loop or 2 loop mode configurations to optimize clock performance and solution cost for different
use cases.
In three-loop mode, the TCXO/OCXO source determines the free-run and holdover frequency stability and
accuracy, and the XO source determines the output phase noise and jitter performance over the 12-kHz to 20-
MHz band. Three-loop mode allows the use of a cost-effective, low-frequency TCXO/OCXO (10 or 12.8 MHz) to
support standards-compliant frequency stability and low loop bandwidth (≤10 Hz) required in synchronization
applications like SyncE and SONET/SDH. Two-loop mode allows for either higher loop bandwidth, relaxed
holdover operation where the XO determines the free-run and holdover frequency stability and accuracy, or both.
The reference input muxes supports automatic input selection or manual input selection through software or pin
control. The reference switchover event will be hitless with superior phase transient performance (50 ps typical).
The reference clock input monitoring block monitors the clock inputs and will perform a switchover or holdover
when a loss of reference (LOR) is detected. A LOR can be detected upon any violation of the threshold limits set
for the input clock amplitude, frequency, missing pulse, and runt pulse monitors. The threshold limits for each
input monitor can be set and enabled independently per clock input. The holdover output frequency accuracy can
be determined by the historical average frequency to minimize frequency and phase disturbance during LOR.
The device has eight outputs with programmable drivers, allowing up to eight differential clocks, eight LVCMOS
pairs (two per pair), or a combination of both. The output clocks can be derived from either PLL/VCO domain
through the output channel muxes. A 1-PPS output can be supported on outputs 0 and 7. The output dividers
have a SYNC feature to allow multiple outputs to be phase-aligned. If needed, zero delay can be enabled to
achieve a deterministic phase offset between any specified PLL output clock and its selected input clock.
To support IEEE 1588 PTP slave clock or other clock steering applications, each PLL core also supports DCO
mode with <1-ppt (part per trillion) frequency resolution for precise frequency and phase adjustment through
external software or pin control.
The device is fully programmable through I2C or SPI interface and features custom start-up clock configuration
with the internal EEPROM, which is factory-set and in-system programmable. Internal LDO regulators provide
excellent power supply noise rejection (PSNR) to reduce the cost and complexity of the power delivery network.
The clock input and PLL monitors can be observed through the interrupt registers and status pins for full
diagnostic capability.
Table 1. Clock Output Phase Jitter for 156.25 MHz
INTEGRATION BANDWIDTH TYPICAL JITTER MAXIMUM JITTER
12 kHz – 20 MHz 150-fs RMS 225-fs RMS
AC-LVPECL output, IN = 19.44 MHz, XO = 48 MHz, TCXO = 10 MHz
Figure 1. Clock Output Phase Noise for 156.25 MHz

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64 HW_SW_CTRL17INSEL0_1
1IN0_P 48 CAP_APLL1
63 VDDO_718TCXO_IN
2IN0_N 47 LF1
62 OUT7_P19VDD_TCXO
3VDD_IN0 46 PDN
61 OUT7_N20INSEL0_0
4VDD_IN3 45 GPIO0/SYNCN
60 GPIO2/SDO21VDDO_0
5IN3_P 44 XO_N
59 VDDO_622OUT0_P
6IN3_N 43 XO_P
58 OUT6_N23OUT0_N
7CAP_DIG 42 VDD_XO
57 OUT6_P24GPIO1/SCS
8VDD_DIG 41 GPIO4/FDEC1
56 STATUS125VDDO_1
9VDD_IN2 40 GPIO3/FINC1
55 STATUS026OUT1_N
10IN2_P 39 LF2
54 OUT5_P27OUT1_P
11IN2_N 38 CAP_APLL2
53 OUT5_N28INSEL1_0
12GPIO5/FINC2 37 VDD_APLL2
52 OUT4_N29INSEL1_1
13GPIO6/FDEC2 36 SCL/SCK
51 OUT4_P30VDDO_23
14IN1_P 35 SDA/SDI
50 VDDO_4531OUT2_P
15IN1_N 34 OUT3_P
49 VDD_APLL132OUT2_N
16VDD_IN1 33 OUT3_N
Not to scale
GND
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(1) G = Ground, P = Power, I = Input, O = Output, I/O = Input or Output, A = Analog.
6 Pin Configuration and Functions
RGC Package
64-Pin VQFN
Top View
Pin Functions
PIN TYPE (1) DESCRIPTION
NAME NO.
POWER
GND PAD G Ground / Thermal Pad.
The exposed pad must be connected to PCB ground for proper electrical and thermal performance.
A 7x7 via pattern is recommended to connect the IC ground pad to the PCB ground layers.
VDD_IN0 3 P
Core Supply (3.3 V) for Reference Inputs 0 to 3.
Place a nearby 0.1-µF bypass capacitor on each pin.
VDD_IN1 16 P
VDD_IN2 9 P
VDD_IN3 4 P

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Pin Functions (continued)
PIN TYPE (1) DESCRIPTION
NAME NO.
VDD_XO 42 P Core Supply (3.3 V) for XO and TCXO Inputs.
Place a nearby 0.1-µF bypass capacitor on each pin.
VDD_TCXO 19 P
VDD_APLL1 49 P Core Supply (3.3 V) for PLL1, PLL2, and Digital Blocks.
Place a nearby 0.1-µF bypass capacitor on each pin.
VDD_APLL2 37 P
VDD_DIG 8 P
VDDO_0 21 P
Output Supply (1.8, 2.5, or 3.3 V) for Clock Outputs 0 to 7.
Place a nearby 0.1-µF bypass capacitor on each pin.
VDDO_1 25 P
VDDO_23 30 P
VDDO_45 50 P
VDDO_6 59 P
VDDO_7 63 P
CORE BLOCKS
LF1 47 A External Loop Filter Capacitor for APLL1 and APLL2.
Place a nearby 0.1-µF capacitor on each pin.
LF2 39 A
CAP_APLL1 48 A External Bypass Capacitors for APLL1, APLL2, and Digital Blocks.
Place a nearby 10-µF bypass capacitor on each pin.
CAP_APLL2 38 A
CAP_DIG 7 A
INPUT BLOCKS
IN0_P 1 I
DPLL Reference Clock Inputs 0 to 3.
Each input pair can accept a differential or single-ended clock signal for synchronizing the DPLLs.
Each pair has programmable input type with internal termination to support AC- or DC-coupled
clocks. A single-ended LVCMOS clock can applied to the P input with the N input pulled down to
ground. An unused input pair can be left floating. LVCMOS input mode is recommended for input
frequencies below 1 MHz.
IN0_N 2 I
IN1_P 14 I
IN1_N 15 I
IN2_P 10 I
IN2_N 11 I
IN3_P 5 I
IN3_N 6 I
XO_P 43 I XO Input.
This input pair can accept a differential or single-ended clock signal from a low-jitter local oscillator
to lock the APLLs. This input has programmable input type with internal termination to support AC-
or DC-coupled clocks. A single-ended LVCMOS clock can applied to the P input with the N input
pulled down to ground.
XO_N 44 I
TCXO_IN 18 I
TCXO Input.
This input can accept an AC-coupled sinewave, clipped-sinewave, or single-ended clock signal from
a stable oscillator (TCXO/OCXO) to lock the TCXO-DPLL if used by a DPLL configuration. The
input swing must be less than 1.2 Vpp before AC-coupling to the input pin, which a weak internal
biasing to about 0.6 V and no internal termination. Leave pin floating if unused.
OUTPUT BLOCKS
OUT0_P 22 O
Clock Outputs 0 to 3 Bank.
Each programmable output driver pair can support AC-LVDS, AC-CML, AC-LVPECL, HCSL, or
1.8/2.5-V LVCMOS clocks (one or two per pair). Unused differential outputs should be terminated if
active or left floating if disabled through registers.
The OUT[0:3] bank requires at least one clock from PLL2 domain if enabled. This bank is preferred
for PLL2 clocks to minimize output crosstalk.
OUT0_N 23 O
OUT1_P 27 O
OUT1_N 26 O
OUT2_P 31 O
OUT2_N 32 O
OUT3_P 34 O
OUT3_N 33 O

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Pin Functions (continued)
PIN TYPE (1) DESCRIPTION
NAME NO.
(2) Internal resistors: PDN pin has 200-kΩpullup to VDD. Each HW_SW_CTRL, GPIO, and STATUS pin has a 150-kΩbias to VIM (~0.9 V)
when PDN = 0 or 400-kΩpulldown when PDN = 1. Each INSEL pin has a 85-kΩpullup to 1.8 V when PDN = 0 or 400-kΩpulldown
when PDN = 1.
(3) Unless otherwise noted: Logic inputs are 2-level, 1.8-V compatible inputs. Logic outputs are 3.3-V LVCMOS levels.
OUT4_P 51 O
Clock Outputs 4 to 7 Bank.
Each programmable output driver pair can support AC-LVDS, AC-CML, AC-LVPECL, HCSL, or
1.8/2.5-V LVCMOS clocks (one or two per pair). Unused differential outputs should be terminated if
active or left floating if disabled through registers.
The OUT[4:7] bank requires at least one clock from PLL1 domain. This bank is preferred for PLL1
clocks to minimize output crosstalk.
OUT4_N 52 O
OUT5_P 54 O
OUT5_N 53 O
OUT6_P 57 O
OUT6_N 58 O
OUT7_P 62 O
OUT7_N 61 O
LOGIC CONTROL / STATUS (2)(3)
HW_SW_CTRL 64 I
Device Start-Up Mode Select (3-level, 1.8-V compatible).
This input selects the device start-up mode that determines the memory page used to initialize the
registers, serial interface, and logic pin functions. The input level is sampled only at device power-
on reset (POR).
See Table 2 for start-up mode descriptions and logic pin functions.
PDN 46 I
Device Power-Down (active low).
When PDN is pulled low, the device is in hard reset and all blocks including the serial interface are
powered-down. When PDN is pulled high, the device is started according to device mode selected
by HW_SW_CTRL and begins normal operation with all internal circuits reset to their initial state.
SDA/SDI 35 I/O
I2C Serial Data I/O (SDA) or SPI Serial Data Input (SDI). See Table 2.
The default 7-bit I2C address is 11000xxb, where the MSB bits (11000b) are initialized from on-chip
EEPROM and the LSB bits (xxb) are determined by the logic input pins. When HW_SW_CTRL is 0,
the LSBs are determined by the GPIO[2:1] input levels during POR. When HW_SW_CTRL is 1, the
LSBs are fixed to 00b.
SCL/SCK 36 I I2C Serial Clock Input (SCL) or SPI Serial Clock Input (SCK). See Table 2.
GPIO0/SYNCN 45 I
Multifunction Inputs or Outputs.
See Table 2.
GPIO1/SCS 24 I
GPIO2/SDO 60 I/O
GPIO3/FINC1 40 I
GPIO4/FDEC1 41 I
GPIO5/FINC2 12 I/O
GPIO6/FDEC2 13 I/O
STATUS1 56 I/O Status Outputs [1:0].
Each output has programmable status signal selection, driver type (3.3-V LVCMOS or open-drain),
and status polarity. Open-drain requires an external pullup resistor. Leave pin floating if unused.
STATUS0 55 I/O
INSEL0_1 17 I Manual Reference Input Selection for DPLL1.
INSEL0_[1:0] = 00b (IN0), 01b (IN1), 10b (IN2), or 11b (IN3). Leave pin floating if unused.
INSEL0_0 20 I
INSEL1_1 29 I Manual Reference Input Selection for DPLL2.
INSEL1_[1:0] = 00b (IN0), 01b (IN1), 10b (IN2), or 11b (IN3). Leave pin floating if unused.
INSEL1_0 28 I

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(1) The input levels on these pins are sampled only during POR.
(2) These GPIO pins are only functional when the DCO feature and FINC/FDEC pin controls are enabled by registers.
(3) As status outputs, the GPIO[6:5] pins have the same capabilities as the STATUS[1:0] pins described in .
(4) When HW_SW_CTRL = Float (VIM), the STATUS[1:0] pins momentarily function as 3-level inputs and both pins must be biased to VIM
(internally or externally) during device POR to ensure proper start-up. If either STATUS pin is connected to an external host device
(MCU, FPGA), the external device must be configured with high-impedance inputs (no pullup or pulldown) to avoid conflict with the
internal bias to VIM. If needed, external biasing resistors (10-kΩpullup to 3.3 V and 3.75-kΩpulldown) can be connected on each
STATUS pin to bias the inputs to VIM during POR.
Table 2. Device Start-Up Modes With Logic Pin Functions
HW_SW_CTRL
INPUT LEVEL(1) START-UP MODE MODE DESCRIPTION
0EEPROM + I2C
(Soft pin mode)
Registers are initialized from EEPROM, and I2C interface is enabled. Logic pins:
• SDA, SCL: I2C Data, I2C Clock (open-drain). Pins require external pullups > 1 kΩ.
• GPIO0: Output SYNC Input (active low). Tie pin high externally if not used.
• GPIO[2:1](1): I2C Address LSB Select Input (00, 01, 10, 11b)
• GPIO[4:3](2): DPLL1 DCO Frequency Decrement and Increment Inputs (active high)
• GPIO[6:5](2)(3): DPLL2 DCO Frequency Decrement and Increment Inputs (active high), or
Status Outputs
Float
(VIM)EEPROM + SPI
(4)
(Soft pin mode)
Registers are initialized from EEPROM, and SPI interface is enabled. Logic pins:
• SDA, SCL: SPI Data Input (SDI), SPI Clock (SCK)
• GPIO1: SPI Chip Select (SCS)
• GPIO2: SPI Data Output (SDO)
• GPIO[6:3, 0]: Same as for HW_SW_CTRL = 0
1ROM + I2C
(Hard pin mode)
Registers are initialized from the ROM page selected by GPIO pins, and I2C interface is enabled.
Logic pins:
• SDA, SCL: I2C Data, I2C Clock (open-drain). Pins require external pullups > 1 kΩ.
• GPIO[3:0](1): ROM Page Select Input (0000 to 1111b)
• GPIO[6:5](3): Status Outputs
• GPIO4: Not used during POR
After POR, GPIO[6:3] can function the same as for HW_SW_CTRL = 0 if enabled by registers.
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) VDD refers to all core supply pins or voltages. All VDD core supplies should be powered-on before internal power-on reset (POR).
(3) VDDO refers to all output supply pins or voltages. VDDO_x refers to the output supply for a specific output channel, where x denotes
the channel index.
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VDD (2) Core Supply Voltages –0.3 3.6 V
VDDO (3) Output Supply Voltages –0.3 3.6 V
Vin Input Voltage for Clock and Logic Inputs –0.3 VDD + 0.3 V
Vout Output Voltage for Clock and Logic Outputs –0.3 VDD + 0.3 V
TJJunction temperature 150 °C
Tstg Storage temperature –65 150 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.2 ESD Ratings VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±750

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(1) VDD refers to all core supply pins or voltages. All VDD core supplies should be powered-on before internal power-on reset (POR).
(2) The LVCMOS driver supports full rail-to-rail swing when VDDO_x is 1.8 V or 2.5 V ± 5%. When VDDO_x is 3.3 V, the LVCMOS driver
cannot swing fully to the positive rail due to the dropout voltage of the output channel's internal LDO regulator.
(3) Time for VDD to ramp monotonically above 2.7 V for proper internal POR. For slower or non-monotonic VDD ramp, hold PDN low until
after VDD voltages are valid.
7.3 Recommended Operating Conditions MIN NOM MAX UNIT
VDD (1) Core Supply Voltages 3.135 3.3 3.465 V
VDDO
(1) Output Supply Voltages AC-LVDS/CML/LVPECL, HCSL 1.71 1.8, 2.5, 3.3 3.465 V
1.8-V or 2.5-V LVCMOS (2) 1.71 1.8, 2.5 2.625 V
TAAmbient Temperature –40 25 85 °C
TJJunction Temperature 135 °C
tVDD Power Supply Ramp Time (3) 0.01 100 ms
nEEcyc EEPROM Programming Cycles 100 cycles
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) The thermal information is based on a 10-layer 200 mm x 250 mm board with 49 thermal vias (7 x 7 pattern, 0.3 mm holes)
(3) ψJB can allow the system designer to measure the board temperature (TPCB) with a fine-gauge thermocouple and back-calculate the
device junction temperature, TJ= TPCB + (ψJB x Power). Measurement of ψJB is defined by JESD51-6.
7.4 Thermal Information
THERMAL METRIC(1) (2) (3)
LMK05028
UNIT
RGC (VQFN)
64 PINS
0-LFM AIRFLOW
RθJA Junction-to-ambient thermal resistance 20.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 6.3 °C/W
RθJB Junction-to-board thermal resistance 4.9 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.3 °C/W
ψJT Junction-to-top characterization parameter 0.1 °C/W
ψJB Junction-to-board characterization parameter 4.8 °C/W
(1) Total device current can be estimated by summing the individual IDD_x and IDDO_x per pin for all blocks enabled in a given
configuration.
(2) Configuration A (All blocks on except TCXO_IN and both TCXO-DPLLs): IN[0:3] = 25 MHz, XO = 48.0048 MHz, TCXO_IN disabled.
Both DPLLs in 2 loop mode, DPLL[1:2] REF-TDC ~ 0.4 MHz, VCO1 = 5 GHz, PLL1_P1 = 8, VCO2 = 5.5296 GHz, PLL2_P1 = 9.
(3) Configuration B (All blocks on): IN[0:3] = 25 MHz, XO = 48.0048 MHz, TCXO_IN = 10 MHz. Both DPLLs in 3 loop mode, DPLL[1:2]
REF-TDC ~ 0.4 MHz, TCXO-TDC = 10 MHz, VCO1 = 5 GHz, PLL1_P1 = 8, VCO2 = 5.5296 GHz, PLL2_P1 = 9.
7.5 Power Supply Characteristics(1)
VDD = 3.3 V ± 5%, VDDO = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, TA= –40ºC to 85ºC. Specification applies to both
Configuration A (2) and Configuration B (3) unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IDD_IN[0,1,
3] Core Supply Current (VDD_INx) 3.5 mA
IDD_IN2 Core Supply Current
(VDD_INx) 6 mA
IDD_PLL1 Core Supply Current
(VDD_PLL1) Configuration A (2) 160 mA
Configuration B (3) 185 mA
IDD_PLL2 Core Supply Current
(VDD_PLL2) Configuration A 138 mA
Configuration B 160 mA
IDD_DIG Core Supply Current
(VDD_DIG) Configuration A 34 mA
Configuration B 42 mA
IDD_XO Core Supply Current
(VDD_XO) 25 mA

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Power Supply Characteristics(1) (continued)
VDD = 3.3 V ± 5%, VDDO = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, TA= –40ºC to 85ºC. Specification applies to both
Configuration A (2) and Configuration B (3) unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IDD_TCXO Core Supply Current
(VDD_TCXO) Configuration A 1 mA
Configuration B 6 mA
IDDO_x Output Supply Current
(VDDO_x = 3.3 V ± 5%)
AC-LVDS (one pair), 156.25 MHz 22 mA
AC-CML (one pair), 156.25 MHz 24 mA
AC-LVPECL (one pair), 156.25 MHz 27 mA
HCSL (one pair), 156.25 MHz 33 mA
2.5-V LVCMOS (two outputs), 156.25 MHz,
5-pF load 40 mA
1.8-V LVCMOS (two outputs), 156.25 MHz,
5-pF load 33 mA
IDD_PD Total Supply Current in Power-down (all VDD and
VDDO pins) Device powered-down (PDN pin = 0) 40 mA
(1) Parameter is specified by characterization and is not tested in production.
(2) For inputs less than 1 MHz, use LVCMOS input or else disable the amplitude monitor.
7.6 Clock Input Characteristics (INx_P/N)
VDD = 3.3 V ± 5%, VDDO = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, TA= –40ºC to 85ºC
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fCLK Input frequency(1) LVCMOS input 1E-6 250 MHz
Differential input (2) 1 750
VIH Input high voltage LVCMOS input 1.4 V
VIL Input low voltage 0 0.8 V
VIN_DIFF Differential input voltage
swing, peak-peak (VP– VN)Differential input 0.2 2 V
dV/dt Input slew rate (1) 0.2 V/ns
IIN Input leakage current –100 100 µA
CIN Input capacitance Single-ended, each pin 2 pF
(1) Parameter is specified by characterization and is not tested in production.
7.7 XO Input Characteristics (XO_P/N)
VDD = 3.3 V ± 5%, VDDO = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, TA= –40ºC to 85ºC
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fCLK Input frequency (1) 10 100 MHz
VIH Input high voltage LVCMOS input 1.4 2.6 V
VIL Input low voltage 0 0.8 V
VIN_DIFF Differential input voltage
swing, peak-peak (VP– VN)Differential input 0.2 2 V
dV/dt Input slew rate (1) 0.2 V/ns
IDC Input duty cycle 40 60 %
IIN Input leakage current –100 100 uA
CIN Input capacitance Single-ended, each pin 1 pF

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(1) Parameter is specified by characterization and is not tested in production.
7.8 TCXO/OCXO Input Characteristics (TCXO_IN)
VDD = 3.3 V ± 5%, VDDO = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, TA= –40ºC to 85ºC
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fCLK Input frequency (1) 10 54 MHz
VIN Input voltage swing 0.8 1.3 V
VBIAS Input bias voltage Biased internally TBD 0.6 TBD V
dV/dt Input slew rate (1) 0.2 V/ns
IDC Input duty cycle 40 60 %
CIN Input capacitance 10 pF
(1) Parameter is specified by characterization and is not tested in production.
7.9 APLL/VCO Characteristics
VDD = 3.3 V ± 5%, VDDO = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, TA= –40ºC to 85ºC
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fVCO1 VCO1 Frequency range (1) 4.8 5.4 GHz
fVCO2 VCO2 Frequency range (1) 5.5 6.2 GHz
(1) Parameter is specified by characterization and is not tested in production.
7.10 2.5-V LVCMOS Output Characteristics (OUTx_P/N)
VDD = 3.3 V ± 5%, VDDO = 2.5 V ± 5%, TA= –40ºC to 85ºC, Fast slew rate
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fOUT Output frequency (1) 1E-6 200 MHz
VOH Output high voltage IOH = 1 mA 1.9 V
VOL Output low voltage IOL = 1 mA 0.525 V
IOH Output high current -48 mA
IOL Output low current 55 mA
tR/tFOutput rise/fall time (1) 20% to 80% 250 TBD ps
tSKEW Output-to-output skew (1) Same post divider, output divide values, and
output type 100 ps
tSKEW Output-to-output skew (1) Same post divider and output divide values,
LVCMOS-to-DIFF 1.5 ns
PN-Floor Output phase noise floor
(fOFFSET = 10 MHz) (1) 66.66 MHz –155 dBc/Hz
ODC Output duty cycle (1) Not PLL bypass output 45 55 %
ROUT Output impedance 50 Ω
(1) Parameter is specified by characterization and is not tested in production.
7.11 1.8-V LVCMOS Output Characteristics (OUTx_P/N)
VDD = 3.3 V ± 5%, VDDO = 1.8 V ± 5%, TA= –40ºC to 85ºC, Fast slew rate
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fOUT Output frequency (1) 1E-6 200 MHz
VOH Output high voltage IOH = 1 mA 1.2 V
VOL Output low voltage IOL = 1 mA 0.4 V
IOH Output high current -23 mA
IOL Output low current 24
tR/tFOutput rise/fall time (1) 20% to 80% 250 TBD ps
tSKEW Output-to-output skew (1) Same post divider, output divide values, and
output type 100 ps
tSKEW Output-to-output skew (1) Same post divider and output divide values,
LVCMOS-to-DIFF 1.5 ns

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1.8-V LVCMOS Output Characteristics (OUTx_P/N) (continued)
VDD = 3.3 V ± 5%, VDDO = 1.8 V ± 5%, TA= –40ºC to 85ºC, Fast slew rate
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PN-Floor Output phase noise floor
(fOFFSET = 10 MHz) (1) 66.66 MHz –155 dBc/Hz
ODC Output duty cycle (1) Not PLL bypass output 45 55 %
ROUT Output impedance 50 Ω
(1) Parameter is specified by characterization and is not tested in production.
(2) An output frequency over the fOUT max spec is possible, but the output swing may be less than the VOD min spec.
7.12 AC-LVDS Output Characteristics (OUTx_P/N)
VDD = 3.3 V ± 5%, VDDO = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, TA= –40ºC to 85ºC, Output pair AC-coupled to 100-Ω
differential load, Fast slew rate
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fOUT Output frequency(1) (2) 750 MHz
VOD Output voltage swing (VOH-
VOL)fOUT ≥25 MHz 250 400 450 mV
VODpp Differential output voltage
swing, peak-to-peak 2 × |VOD| V
VOS Output common mode 100 430 mV
tSKEW Output-to-output skew (1) Same post divider, output divide values, and
output type 100 ps
tR/tFOutput rise/fall time (1) 20% to 80%, < 300 MHz 150 300 ps
±100 mV around center point, > 300 MHz 200
PN-Floor Output phase noise floor
(fOFFSET = 10 MHz) 156.25 MHz –160 dBc/Hz
ODC Output duty cycle (1) Not PLL bypass output 45 55 %
(1) Parameter is specified by characterization and is not tested in production.
(2) An output frequency over the fOUT max spec is possible, but the output swing may be less than the VOD min spec.
7.13 AC-CML Output Characteristics (OUTx_P/N)
VDD = 3.3 V ± 5%, VDDO = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, TA= –40ºC to 85ºC, Output pair AC-coupled to 100-Ω
differential load, Fast slew rate
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fOUT Output frequency(1) (2) 750 MHz
VOD Output voltage swing (VOH-
VOL)fOUT ≥25 MHz 400 600 800 mV
VODpp Differential output voltage
swing, peak-to-peak 2 x |VOD| V
VOS Output common mode 150 550 mV
tSKEW Output-to-output skew (1) Same post divider, output divide values, and
output type 100 ps
tR/tFOutput rise/fall time (1) 20% to 80%, < 300 MHz 150 300 ps
±100 mV around center point, > 300 MHz 200
PN-Floor Output phase noise floor
(fOFFSET = 10 MHz) 156.25 MHz –160 dBc/Hz
ODC Output duty cycle (1) Not PLL bypass output 45 55 %

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(1) Parameter is specified by characterization and is not tested in production.
(2) An output frequency over the fOUT max spec is possible, but the output swing may be less than the VOD min spec.
7.14 AC-LVPECL Output Characteristics (OUTx_P/N)
VDD = 3.3 V ± 5%, VDDO = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, TA= –40ºC to 85ºC, Output pair AC-coupled to 100-Ω
differential load, Fast slew rate
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fOUT Output frequency(1) (2) 750 MHz
VOD Output voltage swing (VOH-
VOL)fOUT ≥25 MHz 500 800 1000 mV
VODpp Differential output voltage
swing, peak-to-peak 2 × |VOD| V
VOS Output common mode 300 700 mV
tSKEW Output-to-output skew (1) Same post divider, output divide values, and
output type 100 ps
tR/tFOutput rise/fall time (1) 20% to 80%, < 300 MHz 150 300 ps
±100 mV around center point, > 300 MHz 200
PN-Floor Output phase noise floor
(fOFFSET = 10 MHz) 156.25 MHz –162 dBc/Hz
ODC Output duty cycle (1) Not PLL bypass output 45 55 %
(1) Parameter is specified by characterization and is not tested in production.
7.15 HCSL Output Characteristics (OUTx_P/N)
VDD = 3.3 V ± 5%, VDDO = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, TA= –40ºC to 85ºC, Output pair terminated with 50 Ωto
GND, Fast slew rate
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fOUT Output frequency 400 MHz
VOH Output high voltage 600 880 mV
VOL Output low voltage –150 150 mV
tSKEW Output-to-output skew (1) Same post divider, output divide values, and
output type 100 ps
dV/dt Output slew rate(1) Measured from -150 mV to +150 mV on the
differential waveform 2.5 8 V/ns
PN-Floor Output phase noise floor
(fOFFSET = 10 MHz) 100 MHz –158 dBc/Hz
ODC Output duty cycle (1) Not PLL bypass output 45 55 %
7.16 2-Level Logic Input Characteristics (PDN, GPIO[6:0], INSELx_[1:0])
VDD = 3.3 V ± 5%, VDDO = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, TA= –40ºC to 85ºC
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH Input high voltage 1.2 V
VIL Input low voltage 0.6 V
IIH Input high current VIH = VDD –40 40 uA
IIL Input low current VIL = GND –40 40 uA
tWIDTH Input pulse width Monotonic edges 10 ns
CIN Input capacitance 2 pF
7.17 3-Level Logic Input Characteristics (HW_SW_CTRL, STATUS[1:0])
VDD = 3.3 V ± 5%, VDDO = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, TA= –40ºC to 85ºC
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH Input high voltage 1.4 V
VIM Input mid voltage Input floating with internal bias 0.9 V
VIL Input low voltage 0.4 V

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3-Level Logic Input Characteristics (HW_SW_CTRL, STATUS[1:0]) (continued)
VDD = 3.3 V ± 5%, VDDO = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, TA= –40ºC to 85ºC
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IIH Input high current VIH = VDD –40 40 uA
IIL Input low current VIL = GND –40 40 uA
CIN Input capacitance 2 pF
7.18 Logic Output Characteristics (STATUS[1:0], GPIO[6:5], GPIO2/SDO)
VDD = 3.3 V ± 5%, VDDO = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, TA= –40ºC to 85ºC
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH Output high voltage IOH = 3 mA, LVCMOS mode TBD V
VOL Output low voltage IOL = 3 mA 0.6 V
tR/tFOutput rise/fall time 20% to 80%, LVCMOS mode, 1 kΩto GND 500 ps
7.19 I2C Interface Characteristics (SDA, SCL)
VDD = 3.3 V ± 5%, VDDO = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, TA= –40ºC to 85ºC
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
VIH Input high voltage 1.2 V
VIL Input low voltage 0.5 V
IIH Input leakage –15 15 uA
CIN Input capacitance 1 pF
VOL Output low voltage IOL = 3 mA 0.3 V
fSCL SCL clock rate Standard 100 kHz
fSCL SCL clock rate Fast mode 400 kHz
tSU_STA START condition setup
time SCL high before SDA low 0.6 us
tH_STA START condition hold time SCL low after SDA low 0.6 us
tPH_STA SCL pulse width high 0.6 us
tPL_STA SCL pulse width low 1.3 us
tSU_SDA SDA hold time SDA valid after SCL low 0 0.9 us
tH_SDA SDA setup time 100 ns
tR_IN SCL/SDA input rise time 300 ns
tF_IN SCL/SDA input fall time 300 ns
tF_OUT SDA output fall time CBUS ≤400 pF 300 ns
tSU_STOP STOP condition setup time 0.6 us
tBUS Bus free time between
STOP and START 1.3 us
tVD-DAT Data valid time 0.9 us
tVD-ACK Data valid acknowledge
time 0.9 us
7.20 SPI Timing Requirements (SDA, SCL, GPIO1/SCS, GPIO2/SDO)
VDD = 3.3 V ± 5%, VDDO = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, TA= –40ºC to 85ºC
PARAMETER MIN NOM MAX UNIT
fClock SCL clock rate 20 MHz
t1SCS to SCL setup time 10 ns
t2SDI to SCL setup time 10 ns
t3SDI to SCL hold time 10 ns
t4SCL high time 25 ns
t5SCL low time 25 ns

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SPI Timing Requirements (SDA, SCL, GPIO1/SCS, GPIO2/SDO) (continued)
VDD = 3.3 V ± 5%, VDDO = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, TA= –40ºC to 85ºC
PARAMETER MIN NOM MAX UNIT
t6SCL to SDO valid read-back data 10 TBD ns
t7SCS pulse width 20 ns
t8SCS to CLK hold time 10 ns
(1) Parameter is specified by characterization and is not tested in production.
7.21 Other Characteristics
VDD = 3.3 V ± 5%, VDDO = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, TA= –40ºC to 85ºC, OUTx = 156.25 MHz, Differential
output pair AC-coupled to 100-Ωdifferential load, HCSL output pair terminated with 50 Ωto GND, LVCMOS output terminated
with 50 Ωto VDDO / 2.
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
tPHO,CMO
SIN-to-OUT Phase Offset,
LVCMOS outputs(1) Zero delay enabled TBD ns
tPHO,DIFF IN-to-OUT Phase Offset, DIFF
outputs(1) Zero delay enabled TBD ns
PSNR Spur level induced by power
supply noise (VN= 50 mVpp)
VDDO_x = 2.5 V or 3.3 V, AC-Diff or
HCSL output –70 dBc
VDDO_x = 2.5 V, LVCMOS output –55 dBc
PSNR Spur level induced by power
supply noise (VN= 25 mVpp) VDDO_x = 1.8 V, AC-Diff or HCSL output –70 dBc
VDDO_x = 1.8 V, LVCMOS output –45 dBc
SPUR Spur level due to isolation/cross
coupling (adjacent outputs) OUTx = 156.25 MHz, OUTy = 155.52
MHz, AC-Diff or HCSL (same output type
for both channels) –75 dBc
(1) Parameter is specified by characterization and is not tested in production.
(2) Actual loop bandwidth may be lower. Applies to REF-DPLL and TCXO-DPLL. The valid loop bandwidth range may be constrained by
the DPLL loop mode and REF and/or TCXO input frequencies used in a given configuration.
(3) First PLL domain to start-up is selected by PLLSTRTMODE bit. Assumes XO input clock is stable before rising edge of PDN, PLL/VCO
wait timers set to 3 ms/0.4 ms, and output channels auto-muted during APLL lock only.
7.22 PLL Clock Output Performance Characteristics
VDD = 3.3 V ± 5%, VDDO = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5%, TA= –40ºC to 85ºC, OUTx = 156.25 MHz, Differential
output pair AC-coupled to 100-Ωdifferential load, HCSL output pair terminated with 50 Ωto GND, LVCMOS output terminated
with 50 Ωto VDDO / 2.
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
RJ RMS Phase Jitter(1) (12
kHz – 20 MHz) OUT = 156.25 MHz AC-Diff or HCSL, XO = 48.0048 MHz 150 225 fs RMS
PN-TDC Output Close-in Phase
Noise (fOFFSET = 100 Hz) OUT = 122.88 MHz AC-Diff or HCSL, IN = 10 MHz, XO = 48.0048 MHz, LBW = 100 Hz –102 dBc/Hz
LBW DPLL Loop Bandwidth
Range(1)(2) Programmed bandwidth setting 0.01 to 4000 Hz
JPK Jitter Peaking(1) IN = 25 MHz, OUT = 25 MHz, DPLL BW = TBD
Hz 0.1 dB
JTOL Jitter tolerance(1) Jitter Modulation = 10 Hz, 10.3125 Gbps 2488 UI p-p
PHTR Maximum phase transient
during Hitless Switch(1) Valid for a single switchover event between two clock inputs at the same frequency ±100 ps
fERROR Maximum additive
frequency error (1) Valid for a single switchover event between two clock inputs at the same frequency 100 ppb
tSTART-XO Initial Clock Start-up Time
(3) From rising edge of PDN to free-running output
clocks from first PLL domain 20 ms
STD Standards Compliance
G.813 Opt. 1
G.8262 Opt. 1 and 2
G.709
GR-253-CORE
GR-1244 CORE

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VOUT,SE
tRtF
OUT_REFx/2
20%
80%
VOD
OUTx_P
OUTx_N
VOUT,DIFF,PP = 2 x VOD
0 V
20%
80%
tRtF
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7.23 Timing Diagrams
Figure 2. Differential Output Voltage and Rise/Fall Time
Figure 3. Single-Ended Output Voltage and Rise/Fall Time

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INx_P
INx_N
OUTx_P
OUTx_N
OUTx_P
OUTx_N
OUTx_P/N
Differential
Differential, PLL
Differential, PLL
Single Ended, PLL
tPHO, SE
tPHO,DIFF
tSK,DIFF,INT
OUTx_P/N
tSK,SE,INT
INx_P Single Ended
tSK,SE-DIFF,INT
Single Ended, PLL
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Timing Diagrams (continued)
Figure 4. Differential and Single-Ended Output Skew and Phase Offset

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LMK05028
HCSL
HCSL
50 
50 
Oscilloscope
High impedance differential probe
Opt ±33 
Opt ±33 
Copyright © 2018, Texas Instruments Incorporated
LMK05028 Oscilloscope
High impedance differential probe
AC-LVPECL,
AC-LVDS,
AC-CML
Copyright © 2018, Texas Instruments Incorporated
LMK05028 LVCMOS Phase Noise/
Spectrum
Analyzer
Copyright © 2018, Texas Instruments Incorporated
LMK05028 LVCMOS
2pF
Oscilloscope
High impedance probe
Copyright © 2018, Texas Instruments Incorporated
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8 Parameter Measurement Information
8.1 Test Configuration
This section describes the test configuration for several electrical characteristics.
Figure 5. LVCMOS Output DC Configuration During Device Test
Figure 6. LVCMOS Output AC Configuration During Device Test
Figure 7. AC-LVPECL, AC-LVDS, AC-CML Output DC Configuration During Device Test
Figure 8. HCSL Output Driving 100-ΩDifferential Trace Impedance DC Configuration During Device Test

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Signal Generator LVDS LMK05028
100 
Copyright © 2018, Texas Instruments Incorporated
LMK05028
375 
125 
Signal Generator
Copyright © 2018, Texas Instruments Incorporated
Signal Generator LVCMOS
Offset = VDD_IN/2
LMK05028
Copyright © 2018, Texas Instruments Incorporated
HCSL
HCSL
50 50 
Balun Phase Noise/
Spectrum
Analyzer
Opt ±33 
Opt ±33 
LMK05028
Copyright © 2018, Texas Instruments Incorporated
AC-LVPECL, AC-LVDS, AC-CML
Phase Noise/
Spectrum
Analyzer
AC-LVPECL, AC-LVDS, AC-CML
Balun
LMK05028
Copyright © 2018, Texas Instruments Incorporated
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Test Configuration (continued)
Figure 9. AC-LVPECL, AC-LVDS, AC-CML Output AC Configuration During Device Test
Figure 10. HCSL Output Driving 100-ΩDifferential Trance Impedance AC Configuration During Device
Test
Figure 11. LVCMOS Reference Input DC Configuration During Device Test
Figure 12. LVCMOS XO Input DC Configuration During Device Test
Figure 13. LVDS Input DC Configuration During Device Test

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Signal Generator
Sine wave
Modulator
Reference
Input
Device Output
Power Supply
Balun Phase Noise/
Spectrum
Analyzer
LMK05028
Copyright © 2018, Texas Instruments Incorporated
Signal Generator LMK05028
Differential
Copyright © 2018, Texas Instruments Incorporated
LMK05028
Signal Generator HCSL
50 
50 
Copyright © 2018, Texas Instruments Incorporated
Signal Generator LVPECL
50 50 
LMK05028
VDD_IN - 2
Copyright © 2018, Texas Instruments Incorporated
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Test Configuration (continued)
Figure 14. LVPECL Input DC Configuration During Device Test
Figure 15. HCSL Input DC Configuration During Device Test
100-Ωdifferential input termination with AC biasing enabled internally (not shown)
Figure 16. Differential Input AC Configuration During Device Test
Figure 17. PSNR Test Setup

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9 Detailed Description
9.1 Overview
The LMK05028 is a high-performance clock generator and jitter cleaner with advanced clock synchronization
capabilities to meet the stringent timing requirements of communications infrastructure and other industrial
applications. The device features four reference inputs, two independent PLL domains, and eight output clocks
with RMS phase jitter of 150 fs typical. Each PLL core supports programmable loop bandwidth for jitter or wander
attenuation, and fractional frequency translation for flexible frequency planning. The advanced synchronization
options in each PLL core include superior hitless switching, digital holdover, DCO mode with <1 ppt/step for
precise clock steering (IEEE 1588 PTP slave operation), and zero delay for deterministic input-to-output phase
offset. The device can use a low-frequency TCXO/OCXO to determine the free-run or holdover frequency
stability for standards-compliant operation, or a standard XO when long-term stability and wander are non-critical.
The device is programmable through I2C or SPI registers and supports custom start-up clock configuration with
internal EEPROM, which can be programmed in-system or factory pre-programmed.