Transcend CompactFlash TS16GCF100I-P User manual

T
T
Tr
r
ra
a
an
n
ns
s
sc
c
ce
e
en
n
nd
d
d I
I
In
n
nd
d
du
u
us
s
st
t
tr
r
ri
i
ia
a
al
l
l C
C
CF
F
F C
C
Ca
a
ar
r
rd
d
d
(
(
(T
T
TS
S
S1
1
12
2
28
8
8M
M
M ~
~
~ 1
1
16
6
6G
G
GC
C
CF
F
F1
1
10
0
00
0
0I
I
I)
)
)
Transcend Information Inc.
V1.1
1
Description
The Transcend CF100I is a High Speed industrial
Compact Flash Card with high quality Flash Memory
assembled on a printed circuit board.
Placement
Dimensions
Features
•CompactFlash Specification Version 4.1 Complaint
•RoHS compliant products
•Single Power Supply: 3.3V
± 5% or 5V ± 10%
•Operating Temperature: -40
o
C to 85
o
C
•Storage Temperature: -55
o
C to 100
o
C
•Operation Modes:

PC Card Memory Mode

PC Card IO Mode

True IDE Mode
•True IDE Mode supports:

Ultra DMA Mode 0 to Ultra DMA Mode 4

Multi-Word DMA Mode 0 to Multi-Word DMA Mode 4

PIO Mode 0 to PIO Mode 6

(Series of –P Only support PIO Mode 0 to PIO Mode
4, please see Order Information)
•True IDE Mode: Fixed Disk (Standard)
•PC Card Mode: Fixed Disk (Standard)
•Durability of Connector: 10,000 times
•Endurance: 2,000,000 Program/Erase cycles
•MTBF: 1,000,000 hours
• Support Wear-Leveling to extend product life
• Support S.M.A.R.T (Self-defined)
• Support Security Command
•Compliant to CompactFlash, PCMCIA, and ATA
standards
•Mechanical Shock Test: 1500G
•Vibration Test: 20G (Peak-to-Peak)
20Hz to 2000Hz (Frequency)

T
T
Tr
r
ra
a
an
n
ns
s
sc
c
ce
e
en
n
nd
d
d I
I
In
n
nd
d
du
u
us
s
st
t
tr
r
ri
i
ia
a
al
l
l C
C
CF
F
F C
C
Ca
a
ar
r
rd
d
d
(
(
(T
T
TS
S
S1
1
12
2
28
8
8M
M
M ~
~
~ 1
1
16
6
6G
G
GC
C
CF
F
F1
1
10
0
00
0
0I
I
I)
)
)
Transcend Information Inc.
V1.1
2
Order information
Part Number Interface Transfer Mode
True IDE mode
Ultra DMA mode 0~4
Multi-Word DMA Mode 0~4
PIO Mode 0 ~ 6
Fixed Disk (Standard)
TS128M~16GCF100I
PC Card mode (PCMCIA)
80ns, 100ns, 120ns, 250ns Fixed Disk (Standard)
True IDE mode PIO Mode 0 ~ 4 Fixed Disk (Standard)
TS128M~16GCF100I-P
PC Card mode (PCMCIA)
250ns Fixed Disk (Standard)
C.H.S. Table
Capacity C H S
128MB 246 16 63
256MB 493 16 63
512MB 987 16 63
1GB 1974 16 63
2GB 3949 16 63
4GB 7899 16 63
8GB 15798 16 63
16GB 33149 15 63

T
T
Tr
r
ra
a
an
n
ns
s
sc
c
ce
e
en
n
nd
d
d I
I
In
n
nd
d
du
u
us
s
st
t
tr
r
ri
i
ia
a
al
l
l C
C
CF
F
F C
C
Ca
a
ar
r
rd
d
d
(
(
(T
T
TS
S
S1
1
12
2
28
8
8M
M
M ~
~
~ 1
1
16
6
6G
G
GC
C
CF
F
F1
1
10
0
00
0
0I
I
I)
)
)
Transcend Information Inc.
V1.1
3
Transcend

T
T
Tr
r
ra
a
an
n
ns
s
sc
c
ce
e
en
n
nd
d
d I
I
In
n
nd
d
du
u
us
s
st
t
tr
r
ri
i
ia
a
al
l
l C
C
CF
F
F C
C
Ca
a
ar
r
rd
d
d
(
(
(T
T
TS
S
S1
1
12
2
28
8
8M
M
M ~
~
~ 1
1
16
6
6G
G
GC
C
CF
F
F1
1
10
0
00
0
0I
I
I)
)
)
Transcend Information Inc.
V1.1
4
Block Diagram

T
T
Tr
r
ra
a
an
n
ns
s
sc
c
ce
e
en
n
nd
d
d I
I
In
n
nd
d
du
u
us
s
st
t
tr
r
ri
i
ia
a
al
l
l C
C
CF
F
F C
C
Ca
a
ar
r
rd
d
d
(
(
(T
T
TS
S
S1
1
12
2
28
8
8M
M
M ~
~
~ 1
1
16
6
6G
G
GC
C
CF
F
F1
1
10
0
00
0
0I
I
I)
)
)
Transcend Information Inc.
V1.1
5
Pin Assignments and Pin Type

T
T
Tr
r
ra
a
an
n
ns
s
sc
c
ce
e
en
n
nd
d
d I
I
In
n
nd
d
du
u
us
s
st
t
tr
r
ri
i
ia
a
al
l
l C
C
CF
F
F C
C
Ca
a
ar
r
rd
d
d
(
(
(T
T
TS
S
S1
1
12
2
28
8
8M
M
M ~
~
~ 1
1
16
6
6G
G
GC
C
CF
F
F1
1
10
0
00
0
0I
I
I)
)
)
Transcend Information Inc.
V1.1
6
Note: 1) These signals are required only for 16 bit accesses and not required when installed in 8 bit
systems. Devices should allow for 3-state signals not to consume current.
2) The signal should be grounded by the host.
3) The signal should be tied to VCC by the host.
4) The mode is required for CompactFlash Storage Cards.
5) The -CSEL signal is ignored by the card in PC Card modes. However, because it is not
pulled upon the card in these modes, it should not be left floating by the host in PC Card
modes. In these modes, the pin should be connected by the host to PC Card A25 or
grounded by the host.
6) If DMA operations are not used, the signal should be held high or tied to VCC by the host. For
proper operation in older hosts: while DMA operations are not active, the card shall ignore
this signal,including a floating condition
7) Signal usage in True IDE Mode except when Ultra DMA mode protocol is active.
8) Signal usage in True IDE Mode when Ultra DMA mode protocol DMA Write is active.
9) Signal usage in True IDE Mode when Ultra DMA mode protocol DMA Read is active.
10) Signal usage in PC Card I/O and Memory Mode when Ultra DMA mode protocol DMA Write is active.
11) Signal usage in PC Card I/O and Memory Mode when Ultra DMA mode protocol DMA Read is active.
12) Signal usage in PC Card I/O and Memory Mode when Ultra DMA protocol is active.

T
T
Tr
r
ra
a
an
n
ns
s
sc
c
ce
e
en
n
nd
d
d I
I
In
n
nd
d
du
u
us
s
st
t
tr
r
ri
i
ia
a
al
l
l C
C
CF
F
F C
C
Ca
a
ar
r
rd
d
d
(
(
(T
T
TS
S
S1
1
12
2
28
8
8M
M
M ~
~
~ 1
1
16
6
6G
G
GC
C
CF
F
F1
1
10
0
00
0
0I
I
I)
)
)
Transcend Information Inc.
V1.1
7
Signal Description
Signal Name Dir.
Pin Description
A10 – A00
(PC Card Memory Mode)
A10 – A00
(PC Card I/O Mode)
A02 - A00
(True IDE Mode)
I
I
8,10,11,12,
14,15,16,17,
18,19,20
18,19,20
These address lines along with the -REG signal are used to
select the following:
The I/O port address registers within the CompactFlash Storage Card , the
memory mapped
port address registers within the CompactFlash Storage Card,
a byte in the card's information structure and its
configuration control and status
registers.
This signal is the same as the PC Card Memory Mode signal.
In True IDE Mode, only A[02:00] are used to select the one of eight registers
in the Task File, the remaining address lines should be grounded by the
host.
BVD1
(PC Card Memory Mode)
-STSCHG
(PC Card I/O Mode)
Status Changed
-PDIAG
(True IDE Mode)
I/O
46 This signal is asserted high, as BVD1 is not supported.
This signal is asserted low to alert the host to changes in the
READY and Write
Protect states, while the I/O interface is configured. Its use is controlled by the
Card Config and Status Register.
In the True IDE Mode, this input / output is the Pass Diagnostic signal in the
Master / Slave handshake protocol.
BVD2
(PC Card Memory Mode)
-SPKR
(PC Card I/O Mode)
-DASP
(True IDE Mode)
I/O
45 This signal is asserted high, as BVD2 is not supported.
This line is the Binary Audio output from the card. If the Card does not support
the Binary Audio function, this line should be held negated.
In the True IDE Mode, this input/output is the Disk Active/Slave
Present signal in
the Master/Slave handshake protocol.
-CD1, -CD2
(PC Card Memory Mode)
-CD1, -CD2
(PC Card I/O Mode)
-CD1, -CD2
(True IDE Mode)
O 26,25 These Card Detect pins are connected to ground on the
CompactFlash Storage
Card. They are used by the host to determine that the CompactFlash Storage
Card is fully inserted into its socket.
This signal is the same for all modes.
This signal is the same for all modes.

T
T
Tr
r
ra
a
an
n
ns
s
sc
c
ce
e
en
n
nd
d
d I
I
In
n
nd
d
du
u
us
s
st
t
tr
r
ri
i
ia
a
al
l
l C
C
CF
F
F C
C
Ca
a
ar
r
rd
d
d
(
(
(T
T
TS
S
S1
1
12
2
28
8
8M
M
M ~
~
~ 1
1
16
6
6G
G
GC
C
CF
F
F1
1
10
0
00
0
0I
I
I)
)
)
Transcend Information Inc.
V1.1
8
Signal Name
Dir.
Pin Description
-CE1, -CE2
(PC Card Memory Mode)
Card Enable
-CE1, -CE2
(PC Card I/O Mode)
Card Enable
-CS0, -CS1
(True IDE Mode)
I 7,32 These input signals are used both to select the card and to indicate to the card
whether a byte or a word operation is being performed. -CE2 always accesses
the odd byte of the word.-CE1 accesses the even byte or the Odd byte of the
word depending on A0 and -CE2. A multiplexing scheme based on A0,-CE1,
-CE2 allows 8 bit hosts to access all data on D0-D7. See Table 27, Table 29,
Table 31, Table 35, Table 36 and Table 37.
This signal is the same as the PC Card Memory Mode signal.
In the True IDE Mode, -CS0 is the address range select for the task file
registers while -CS1 is used to select the Alternate Status Register and the
Device Control Register.
While –DMACK is asserted, -CS0 and –CS1 shall be held negated and the
width of the transfers shall be 16 bits.
-CSEL
(PC Card Memory Mode)
-CSEL
(PC Card I/O Mode)
-CSEL
(True IDE Mode)
I 39 This signal is not used for this mode, but should be connected by
the host to PC
Card A25 or grounded by the host.
This signal is not used for this mode, but should be connected by
the host to PC
Card A25 or grounded by the host.
This internally pulled up signal is used to configure this device as
a Master or a
Slave when configured in the True IDE Mode.
When this pin is grounded, this device is configured as a Master.
When the pin is open, this device is configured as a Slave.
D15 - D00
(PC Card Memory Mode)
D15 - D00
(PC Card I/O Mode)
D15 - D00
(True IDE Mode)
I/O
31,30,29,28,
27,49,48,47,
6,5,4,3,2,
23, 22, 21
These lines carry the Data, Commands and Status information
between the host
and the controller. D00 is the LSB of the Even
Byte of the Word. D08 is the LSB
of the Odd Byte of the Word.
This signal is the same as the PC Card Memory Mode signal.
In True IDE Mode, all Task File operations occur in byte mode
on the low order
bus D[7:0] while all data transfers are 16 bit using D[15:0].
GND
(PC Card Memory Mode)
GND
(PC Card I/O Mode)
GND
(True IDE Mode)
-- 1,50 Ground.
This signal is the same for all modes.
This signal is the same for all modes.

T
T
Tr
r
ra
a
an
n
ns
s
sc
c
ce
e
en
n
nd
d
d I
I
In
n
nd
d
du
u
us
s
st
t
tr
r
ri
i
ia
a
al
l
l C
C
CF
F
F C
C
Ca
a
ar
r
rd
d
d
(
(
(T
T
TS
S
S1
1
12
2
28
8
8M
M
M ~
~
~ 1
1
16
6
6G
G
GC
C
CF
F
F1
1
10
0
00
0
0I
I
I)
)
)
Transcend Information Inc.
V1.1
9
Signal Name
Dir.
Pin Description
-INPACK
(PC Card Memory Mode)
-INPACK
(PC Card I/O Mode)
Input Acknowledge
DMARQ
(True IDE Mode)
O 43 This signal is not used in this mode.
The Input Acknowledge signal is asserted by the CompactFlash Storage Card
when the card is selected and responding to an I/O read cycle at the address
that is on the address bus. This signal is used by the host to control the enable
of
any input data buffers between the CompactFlash Storage Card and the CPU.
This signal is a DMA Request that is used for DMA data
transfers between host
and device. It shall be asserted by the
device when it is ready to transfer data to
or from the host. For Multiword DMA transfers, the direction of data transfer is
controlled by -IORD and -IOWR. This signal is used in a
handshake manner with
-DMACK, i.e., the device shall wait until the host asserts -DMACK before
negating DMARQ, and reasserting DMARQ if there is more data to transfer.
DMARQ shall not be driven when the device is not selected.
While a DMA operation is in progress, -CS0 and –CS1 shall be
held negated and
the width of the transfers shall be 16 bits.
If there is no hardware support for DMA mode in the host, this
output signal is not
used and should not be connected at the
host. In this case, the BIOS must report
that DMA mode is not supported by the host so that device drivers will not
attempt DMA mode.
A host that does not support DMA mode and implements both PCMCIA and
True-IDE modes of operation need not alter the PCMCIA mode connections
while in True-IDE mode as long as this does not prevent proper operation
in any
mode.
-IORD
(PC Card Memory Mode)
-IORD
(PC Card I/O Mode)
-IORD
(True IDE Mode – Except
Ultra DMA Protocol Active)
-HDMARDY
(True IDE Mode – In Ultra
DMA Protocol DMA Read)
HSTROBE
(True IDE Mode – In Ultra
DMA Protocol DMA Write)
I 34 This signal is not used in this mode.
This is an I/O Read strobe generated by the host. This signal
gates I/O data onto
the bus from the CompactFlash Storage
Card when the card is configured to use
the I/O interface.
In True IDE Mode, while Ultra DMA mode is not active, this
signal has the same
function as in PC Card I/O Mode.
In True IDE Mode when Ultra DMA mode DMA Read is active, this signal is
asserted by the host to indicate that the host is read to receive Ultra DMA data-
in
bursts. The host may negate -HDMARDY to pause an Ultra DMA transfer.
In True IDE Mode when Ultra DMA mode DMA Write is active,
this signal is the
data out strobe generated by the host. Both the rising and falling edge of
HSTROBE cause data to be latched by the device. The host may stop
generating HSTROBE edges to pause an Ultra DMA data-out burst.

T
T
Tr
r
ra
a
an
n
ns
s
sc
c
ce
e
en
n
nd
d
d I
I
In
n
nd
d
du
u
us
s
st
t
tr
r
ri
i
ia
a
al
l
l C
C
CF
F
F C
C
Ca
a
ar
r
rd
d
d
(
(
(T
T
TS
S
S1
1
12
2
28
8
8M
M
M ~
~
~ 1
1
16
6
6G
G
GC
C
CF
F
F1
1
10
0
00
0
0I
I
I)
)
)
Transcend Information Inc.
V1.1
10
Signal Name
Dir.
Pin Description
-IOWR
(PC Card Memory Mode)
-IOWR
(PC Card I/O Mode)
-IOWR
(True IDE Mode – Except
Ultra DMA Protocol Active)
STOP
(True IDE Mode – Ultra DMA
Protocol Active)
I 35 This signal is not used in this mode.
The I/O Write strobe pulse is used to clock I/O data on the Card Data bus into
the CompactFlash Storage Card controller registers when the CompactFlash
Storage Card is configured to use the I/O interface.
The clocking shall occur on the negative to positive edge of the signal (trailing
edge).
In True IDE Mode, while Ultra DMA mode protocol is not active, this signal has
the same function as in PC Card I/O Mode. When Ultra DMA mode protocol is
supported, this signal must be negated before entering Ultra DMA mode
protocol.
In True IDE Mode, while Ultra DMA mode protocol is active, the
assertion of this
signal causes the termination of the Ultra DMA burst.
-OE
(PC Card Memory Mode)
-OE
(PC Card I/O Mode)
-ATA SEL
(True IDE Mode)
I 9 This is an Output Enable strobe generated by the host interface. It is used to
read data from the CompactFlash Storage Card in Memory Mode and to read
the CIS and configuration registers.
In PC Card I/O Mode, this signal is used to read the CIS and configuration
registers.
To enable True IDE Mode this input should be grounded by the host.
READY
(PC Card Memory Mode)
-IREQ
(PC Card I/O Mode)
INTRQ
(True IDE Mode)
O
37 In Memory Mode, this signal is set high when the CompactFlash Storage Card
is
ready to accept a new data transfer operation and is held low when the card is
busy.
At power up and at Reset, the READY signal is held low (busy) until the
CompactFlash Storage Card has completed its power up or reset function. No
access of any type should be made to the CompactFlash Storage Card during
this time.
Note, however, that when a card is powered up and used with RESET
continuously disconnected or asserted, the Reset function of the RESET pin is
disabled. Consequently, the
continuous assertion of RESET from the application
of power shall not cause the READY signal to remain continuously in the busy
state.
I/O Operation – After the CompactFlash Storage Card Card has been
configured for I/O operation, this signal is used as -
Interrupt Request. This line is
strobed low to generate a pulse mode interrupt or held low for a level mode
interrupt.
In True IDE Mode signal is the active high Interrupt Request to the host.