Transcend Secure Digital Card TS2GSD133 User manual

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Description
Secure Digital Card of high capacity but economic
cost. It is specifically designed to meet the security,
capacity and small form factor requirements in newly
emerging audio and video consumer electronic
devices.Transcend Secure Digital Card can lead you
to a colorful digital world.
Placement
Front Back
Features
•ROHS compliant product
•Operating Voltage: 2.7 ~ 3.6V
•Operating Temperature: -25 ~ 85°C
•Insertion/removal durability: 10,000 cycles
•Fully compatible with SD card spec. v1.1
•Mechanical Write Protection Switch
•Forward compatibility to MultiMediaCard Version 2.11
•Supports Copy Protection for Recorded Media(CPRM) for
music and other commercial media
•Form Factor: 24mm x 32mm x 2.1mm
Pin Definition
SD Mode SPI Mode
Pin No. Name Type Description Name Type Description
1 CD/DAT I/O/PP3Card Detect/Data Line [Bit3] CS I
Chip Select (neg true)
2 CMD PP Command/Response DI I
Data In
3 VSS1 S Supply voltage ground VSS S
Supply voltage ground
4 VDD S Supply voltage VDD S
Supply voltage
5 CLK I Clock SCLK I Clock
6 VSS2 S Supply voltage ground VSS2 S Supply voltage ground
7 DAT0 I/O/PP Data Line [Bit0] DO O/PP
Data Out
8 DAT1 I/O/PP Data Line [Bit1] RSV
9 DAT2 I/O/PP Data Line [Bit2] RSV

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Architecture

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Bus Operating Conditions
• General
Parameter Symbol Min. Max. Unit Remark
Peak voltage on all lines -0.3 VDD+0.3 V
All Inputs
Input Leakage Current -10 10 µA
All Outputs
Output Leakage Current -10 10 µA
• Power Supply Voltage
Parameter Symbol Min. Max. Unit Remark
Supply voltage VDD 2.0 3.6 V CMD0, 15,55,ACMD41
commands
Supply voltage specified in OCR register 2.7 3.6 V Except CMD0, 15,55,
ACMD41 commands
Supply voltage differentials (VSS1, VSS2) -0.3 0.3 V
Power up time 250 ms From 0v to VDD Min.
Note. The current consumption of any card during the power-up procedure must not exceed 10 mA.
• Bus Signal Line Load
The total capacitance CLthe CLK line of the SD Memory Card bus is the sum of the bus master capacitance CHOST, the bus
capacitance CBUS itself and the capacitance CCARD of each card connected to this line:
CL= CHOST + CBUS + Ν*CCARD
Where N is the number of connected cards. Requiring the sum of the host and bus capacitances not to exceed 30 pF for
up to 10 cards, and 40 pF for up to 30 cards, the following values must not be exceeded:
Parameter Symbol Min. Max. Unit Remark
Bus signal line capacitance CL100 pF fPP ≤ 20 MHz, 7 cards
Single card capacitance CCARD 10 pF
Maximum signal line inductance 16 nH fPP ≤ 20 MHz
Pull-up resistance inside card (pin1) RDAT3 10 90 kΩMay be used for card
detection
Note that the total capacitance of CMD and DAT lines will be consist of CHOST, CBUS and one CCARD only since they are
connected separately to the SD Memory Card host.
Parameter Symbol Min. Max. Unit Remark
Pull-up resistance RCMD, RDAT 10 100 kΩTo prevent bus floating
Bus signal line capacitance CL250 pF fPP ≤ 5 MHz, 21 cards

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• Bus Signal Levels
As the bus can be supplied with a variable supply voltage, all signal levels are related to the supply voltage.
To meet the requirements of the JEDEC specification JESD8-1A, the card input and output voltages shall be within the
following specified ranges for any VDD of the allowed voltage range:
Parameter Symbol Min. Max. Unit Remark
Output HIGH voltage VOH 0.75*VDD V IOH = -100 μA @VDD min
Output LOW voltage VOL 0.125*VDD V IOL = -100 μA @VDD min
Input HIGH voltage VIH 0.625*VDD VDD + 0.3 V
Input LOW voltage VIL VSS – 0.3 0.25*VDD V

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• Bus Timing
Parameter Symbol Min Max. Unit Remark
Clock CLK (All values are referred to min (VIH) and max (VIL)
Clock frequency Data Transfer Mode fPP 0 25 MHz CL≤ 100 pF, (7 cards)
Clock frequency Identification Mode
(The low freq. is required for MultiMediaCard
compatibility.)
fOD 0 400 KHz CL≤ 250 pF, (21 cards)
tWL 10 ns CL≤ 100 pF, (7 cards)Clock low time
50 ns CL≤ 250 pF, (21 cards)
tWH 10 ns CL≤ 100 pF, (7 cards)Clock high time
50 ns CL≤ 250 pF, (21 cards)
tTLH 10 ns CL≤ 100 pF, (7 cards)Clock rise time
50 ns CL≤ 250 pF, (21 cards)

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tTHL 10 ns CL≤ 100 pF, (7 cards)Clock fall time
50 ns CL≤ 250 pF, (21 cards)
Inputs CMD, DAT (referenced to CLK)
Input set-up time tISU 5 ns CL≤ 25 pF, (1 cards)
Input hold time tIH 5 ns CL≤ 25 pF, (1 cards)
Outputs CMD, DAT (referenced to CLK)
Output Delay time tODLY 0 14 ns CL≤ 25 pF, (1 cards)

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Reliability and Durability
Temperature Operation: -25°C / 85°C (Target spec)
Storage: -40°C (168h) / 85°C (500h)
Junction temperature: max. 95°C
Moisture and corrosion Operation: 25°C / 95% rel. humidity
Storage: 40°C / 93% rel. hum./500h
Salt Water Spray: 3% NaCl/35C; 24h acc. MIL STD Method 1009
Durability 10.000 mating cycles; test procedure: tbd.
Bending 10N
Torque 0.15N.m or +/-2.5 deg
Drop test 1.5m free fall
UV light exposure UV: 254nm, 15Ws/cm² according to ISO 7816-1
Visual inspection
Shape and form
No warp page; no mold skin; complete form; no cavities surface smoothness <=
-0.1 mm/cm² within contour; no cracks; no pollution (fat, oil dust, etc.)
Minimum moving force of WP witch 40gf (Ensures that the WP switch will not slide while it is inserted to the connector.)
WP Switch cycles minimum 1000 Cycles(@Slide force 0.4N to 5N)
Above technical information is based on industry standard data and tested to be reliable. However, Transcend makes no
warranty, either expressed or implied, as to its accuracy and assumes no liability in connection with the use of this product.
Transcend reserves the right to make changes in specifications at any time without prior notice.

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Mechanical Dimension

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