Ublox JODY-W2 Quick setup guide

UBX-18068879 - R14
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JODY-W2
Host-based multiradio modules with Wi-Fi 5 and
Bluetooth 5.2
System integration manual
Abstract
This document describes the system integration of JODY-W2 series modules. These host-based
modules support Wi-Fi 802.11n/ac and Bluetooth®5.2 and are designed for both simultaneous and
independent operations. The JODY-W2 modules include an integrated MAC/baseband processor
and RF front-end components and are offered in both professional and automotive grades.

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Document information
Title
JODY-W2
Subtitle
Host-based multiradio modules with Wi-Fi 5 and Bluetooth 5.2
Document type
System integration manual
Document number
UBX-18068879
Revision and date
R14
5-Jun-2023
Disclosure restriction
C1 - Public
Document status description
Functional sample
Draft
For functional testing. Revised and supplementary data will be published later.
In development /
Prototype
Objective specification
Target values. Revised and supplementary data will be published later.
Engineering sample
Advance information
Data based on early testing. Revised and supplementary data will be published later.
Initial production
Early production information
Data from product verification. Revised and supplementary data may be published later.
Mass production /
End of life
Production information
Document contains the final product specification.
This document applies to the following products:
Product name
Document status
JODY-W263-A
Production information
JODY-W263
Production information
☞For information about the related hardware, software, and status of listed product types, refer to
the respective data sheet [2].
u -blox or third parties may hold intellectual property rights in the products, names, logos and designs included in this
document. Copying, reproduction, or modification of this document or any part thereof is only permitted with the express
written permission of u-blox. Disclosure to third parties is permitted for clearly public documents only.
The information contained herein is provided “as is”. No warranty of any kind, either express or implied, is made in relation to
the accuracy, reliability, fitness for a particular purpose or content of this document. This document may be revised by u-blox
at any time. For most recent documents, please visit www.u-blox.com.
Copyright © u-blox AG.

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Contents
Document information .............................................................................................................................2
Contents .......................................................................................................................................................3
1System description ............................................................................................................................7
1.1 Overview and applications ........................................................................................................................7
Product features.................................................................................................................................7
Module architecture...........................................................................................................................8
Power management ...........................................................................................................................9
1.2 Pin configuration and function.................................................................................................................9
Pin attributes.......................................................................................................................................9
Pin list..................................................................................................................................................10
Main supply inputs ...........................................................................................................................12
1.3 System function interfaces....................................................................................................................13
Power-up sequence ..........................................................................................................................13
Reset ...................................................................................................................................................14
Power-off sequence..........................................................................................................................14
Wake-up signals................................................................................................................................15
Configuration pins............................................................................................................................15
1.4 Data communication interfaces ............................................................................................................16
SDIO 3.0 interface.............................................................................................................................16
High Speed UART interface............................................................................................................17
PCM - Audio interface......................................................................................................................17
Low power oscillator.........................................................................................................................17
JTAG –Test Interface......................................................................................................................18
1.5 Antenna interfaces...................................................................................................................................18
Wi-Fi and Bluetooth antennas .......................................................................................................18
Approved antenna designs.............................................................................................................19
1.6 Other remarks............................................................................................................................................19
Unused pins .......................................................................................................................................19
GPIO usage.........................................................................................................................................19
2Design-in............................................................................................................................................. 20
2.1 Overview......................................................................................................................................................20
2.2 Antenna interfaces...................................................................................................................................20
RF transmission line design ...........................................................................................................21
Antenna design .................................................................................................................................23
2.3 Supply interfaces ......................................................................................................................................26
Module supply design ......................................................................................................................26
2.4 Data communication interfaces ............................................................................................................28
SDIO 3.0 ..............................................................................................................................................28
High-speed UART interface............................................................................................................29
2.5 Other interfaces and notes.....................................................................................................................29

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2.6 General high-speed layout guidelines...................................................................................................29
General considerations for schematic design and PCB floor-planning.................................30
Component placement....................................................................................................................30
Layout and manufacturing.............................................................................................................30
2.7 Module footprint and paste mask.........................................................................................................31
2.8 Thermal guidelines ...................................................................................................................................32
2.9 ESD guidelines...........................................................................................................................................33
2.10Design checklist ........................................................................................................................................34
Schematic checklist.........................................................................................................................34
Layout checklist................................................................................................................................34
3Software ............................................................................................................................................. 35
3.1 Available software packages..................................................................................................................35
Open-source Linux/Android drivers ..............................................................................................35
MCUXpresso SDK .............................................................................................................................36
Proprietary drivers............................................................................................................................36
3.2 Supported kernel versions ......................................................................................................................36
3.3 Driver package structure.........................................................................................................................37
3.4 Software architecture..............................................................................................................................37
Wi-Fi driver architecture .................................................................................................................38
Bluetooth driver architecture.........................................................................................................38
3.5 Compiling the drivers ...............................................................................................................................39
Prerequisites......................................................................................................................................40
3.6 Deploying the drivers................................................................................................................................40
Firmware.............................................................................................................................................41
Configuration utilities......................................................................................................................41
Additional software requirements................................................................................................41
3.7 Configuration of Wi-Fi transmit power limits .....................................................................................42
Wi-Fi power table..............................................................................................................................42
Applying the transmit power limit configuration.......................................................................45
Reading the transmit power limit configuration........................................................................46
3.8 Configuration of Bluetooth power levels ..............................................................................................46
3.9 Adaptivity configuration (energy detection) .......................................................................................46
3.10Yocto recipes..............................................................................................................................................47
3.11Runtime usage...........................................................................................................................................47
Using reserved MAC addresses.....................................................................................................48
Device detection................................................................................................................................48
Using SDIO-UART driver package.................................................................................................48
Using SDIO-SDIO driver package...................................................................................................51
Verifying the firmware version.......................................................................................................51
Verifying the interfaces...................................................................................................................51
Access point ......................................................................................................................................52
Station mode .....................................................................................................................................54
Bluetooth usage................................................................................................................................55

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Sleep mode configuration .........................................................................................................56
3.12Driver debugging .......................................................................................................................................57
Compile-time debug options ..........................................................................................................57
Runtime debug options...................................................................................................................57
4Handling and soldering................................................................................................................... 58
4.1 ESD handling precautions.......................................................................................................................58
4.2 Packaging, shipping, storage, and moisture preconditioning .........................................................58
4.3 Soldering.....................................................................................................................................................58
Reflow soldering process ................................................................................................................59
Cleaning ..............................................................................................................................................60
Other notes ........................................................................................................................................60
5Regulatory compliance................................................................................................................... 61
5.1 General requirements ..............................................................................................................................61
5.2 European Union regulatory compliance ...............................................................................................61
CE End-product regulatory compliance .......................................................................................61
Compliance with the RoHS directive ............................................................................................62
5.3 Great Britain regulatory compliance .....................................................................................................62
UK Conformity Assessed (UKCA)..................................................................................................62
5.4 United States/Canada end-product regulatory compliance............................................................62
United States compliance statement (FCC)...............................................................................63
Canada compliance statement (ISED) .........................................................................................64
Referring to the u-blox FCC/ISED certification ID......................................................................65
Obtaining own FCC/ISED certification ID ....................................................................................65
Antenna requirements ....................................................................................................................66
Configuration control and software security of end-products ...............................................66
Operating frequencies.....................................................................................................................67
End product labeling requirements ..............................................................................................68
5.5 NCC Taiwan compliance..........................................................................................................................69
Taiwan NCC Warning Statement..................................................................................................69
Labeling requirements for end products .....................................................................................70
5.6 Japan radio equipment compliance......................................................................................................71
Compliance statement....................................................................................................................71
End product labelling requirement................................................................................................71
5.7 KCC South Korea compliance.................................................................................................................71
5.8 Australia and New Zealand regulatory compliance ...........................................................................72
5.9 Approved antennas ..................................................................................................................................72
6Product testing................................................................................................................................. 73
6.1 u-blox in-line production testing............................................................................................................73
6.2 OEM manufacturer production test .....................................................................................................74
“Go/No go” tests for integrated devices ......................................................................................74
Appendix .................................................................................................................................................... 75
B.1. FCC/ISED regulatory domain..................................................................................................................76

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B.1.1. Wi-Fi output power for 2.4 GHz band ...........................................................................................76
B.1.2. Wi-Fi output power for 5 GHz band...............................................................................................76
B.2. ETSI regulatory domain ...........................................................................................................................77
B.2.1. Wi-Fi output power for 2.4 GHz band ...........................................................................................77
B.2.2. Wi-Fi output power for 5 GHz band...............................................................................................77
B.3. Japan regulatory domain (Giteki) ..........................................................................................................78
B.3.1. Wi-Fi output power for 2.4 GHz band ...........................................................................................78
B.3.2. Wi-Fi output power for 5 GHz band...............................................................................................78
B.4. Korea regulatory domain (KCC)..............................................................................................................79
B.4.1. Wi-Fi output power for 2.4 GHz band ...........................................................................................79
B.4.2. Wi-Fi output power for 5 GHz band...............................................................................................79
B.5. Taiwan regulatory domain (NCC)...........................................................................................................79
B.5.1. Wi-Fi output power for 2.4 GHz band ...........................................................................................79
B.5.2. Wi-Fi output power for 5 GHz band...............................................................................................80
Related documents ................................................................................................................................ 83
Revision history ....................................................................................................................................... 84
Contact....................................................................................................................................................... 84

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1System description
1.1 Overview and applications
The JODY-W2 series provides a complete short range transceiver solution that can be easily
integrated into automotive and industrial applications. The modules are designed for both
simultaneous and independent operation of the following technologies:
•Wi-Fi interface supporting IEEE 802.11a/b/g/n/ac data rates up to 433 Mbit/s
•Bluetooth 5.2
JODY-W2 series modules are surface-mount device (SMD) components and can be used as a Wi-Fi
micro-access point for up to eight clients. A coexistence feature on chip level improves parallel use of
Bluetooth and Wi-Fi communication. For highest throughput and performance, Wi-Fi and Bluetooth
have separate antenna pins.
Product features
Item
JODY-W263-A
JODY-W263
Grade
Automotive
Professional
Chipset
NXP 88W8987A/S
NXP 88W8987
Antenna type
Two antenna pins for Wi-Fi and
Bluetooth
Two antenna pins for Wi-Fi and
Bluetooth
Supported Wi-Fi radio modes
IEEE 802.11 a/b/g/n/ac
IEEE 802.11 a/b/g/n/ac
Supported Wi-Fi bands
2.5 / 5 GHz
2.5 / 5 GHz
Max. Wi-Fi output power
19 dBm (at antenna pin)
19 dBm (at antenna pin)
Bluetooth version
5.2
5.2
Bluetooth profiles
HCI
HCI
Supported Bluetooth radio modes
Bluetooth BR/EDR
Bluetooth Low Energy
Bluetooth BR/EDR
Bluetooth Low Energy
Supported Bluetooth LE data rates
1 Mbps
2 Mbps
1 Mbps
2 Mbps
LTE coexistence filter
-
-
OS support
Linux / Android
Linux / Android
Interfaces
SDIO 3.0 (Wi-Fi/Bluetooth)
UART (Bluetooth)
PCM (Bluetooth digital audio)
SDIO 3.0 (Wi-Fi/Bluetooth)
UART (Bluetooth)
PCM (Bluetooth digital audio)
Features
Micro access point with max. 8
connected clients
Micro access point with max. 8
connected clients
Simultaneous client and access point
mode
Simultaneous client and access point
mode
WPA3
WPA3
RF parameters/MAC addresses in OTP
RF parameters/MAC addresses in OTP
Max. ambient operating temperature
85 °C (JODY-W263-00A)
105 °C (JODY-W263-01A)
85 °C
Module size
19.8 x 13.8 mm
19.8 x 13.8 mm
Table 1: JODY-W2 series product features

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Module architecture
Table 2 shows the available antenna (ANT0 and ANT1) and host interface configurations for the
different JODY-W2 series module variants.
Product type
ANT0 configuration
ANT1 configuration
Host interface
JODY-W263
JODY-W263-A
2.4 GHz Bluetooth
2.4 GHz and 5 GHz Wi-Fi
SDIO Wi-Fi (optional Bluetooth)
UART Bluetooth
Table 2: Supported configurations of the JODY-W2 module series
JODY-W2 series module has two antenna pins with one dedicated for dual band Wi-Fi (2.4 GHz and
5 GHz) and the other for Bluetooth. The block diagram shown in Figure 1 is applicable for both
professional and automotive-grade variants.
Figure 1: Block diagram of JODY-W2
☞JODY-W2 variants with a dedicated LTE Coexistence Filter (2.4 GHz BPF) are available on
request. Coexistence filters are only needed if LTE bands 7, 38, 40, and 41 are used.

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Power management
JODY-W2 series modules have several operation modes. The operation modes and general guidelines
for Wi-Fi and Bluetooth operation are defined in Table 3.
General
Status
Power State
Description
Power-down
Not Powered
VBAT, VIO, and 1V8 supply not present or below the operating range: module is
switched off.
Power Down
This is done by asserting PDn and CORE_PDn low. This is the lowest power condition
with active voltage rails. All internal clocks are shut down; register and memory
states are not maintained. Upon exiting power down mode, a reset is automatically
performed, and a firmware re-download is required to re-enter any of the normal
operation modes.
General
operation
Deep Sleep
This is a low-power state used in the sleep state of many power save modes. It is a
low-power state where the internal reference clock and many blocks in the chip are
switched off. Only a slow sleep clock is used to maintain register and memory states.
Wake-up does not require a firmware re-download.
Active
TX/RX data connection enabled, with the system running at the specified power
consumption.
Wi-Fi
operation
IEEE Power Save
(Station mode)
The device automatically wakes up for beacon reception. This is dependent on the
DTIM value of the AP it is connected to. If it is a DTIM value of 1 along with a beacon
interval of 100 ms, the device wakes up every 100 ms. Similarly, with DTIM =2, the
device wakes up at every 200 ms, and so on.
Bluetooth
operation
Page scan
The device accepts connection and waits for a connection.
Page & Inquiry Scan
The device is actively searching for connection.
LE advertisement
Bluetooth LE advertisement, transmits advertisement data periodically.
Table 3: Power states
1.2 Pin configuration and function
Pin attributes
•FUNCTION: Pin function
•PIN NAME: The name of the package pin or terminal
•PIN NUMBER: Package pin numbers associated with each signal.
•POWER: The voltage domain that powers the pin
•TYPE: Signal type description:
oI = Input
oO = Output
oI/O = Input and Output
oD = Open drain
oDS = Differential
oPWR = Power
oGND = Ground
oPU = Internal pull-up
oPD = Internal pull-down
oH = High-Impedance pin
oRF = Radio interface
•SIGNAL NAME: The signal name for that pin in the mode being used.
•REMARKS: Pin description and notes.

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Pin list
Figure 2 and Table 4 show the pin-out of the JODY-W2 module, with pins grouped by function.
Figure 2: JODY-W2 pin assignment (top view)
1
I/O notations: I=Input, O=Output, I/O=Input or Output, OD=Open Drain, NC=Not Connected, PWR=Power, GND=Ground,
RF=Radio i/f
No.
Name
Chip pin
I/O1
Description
Domain
1
GND
GND
Ground
GND
2
VBAT
PWR
Module supply input
(2.8 V –5.5 V)
VBAT
3
VIO
PWR
VIO supply (1.8 V or 3.3 V)
VIO
4
1V8
PWR
VIO supply for SDIO,
Supply for analog part (1.8 V)
1V8
5
GND
GND
Ground
GND
6
CONFIG[2]
NC
Reserved for future use.
A “DNI” pull-up resistor should be added at this pin to
respond to future chipset changes.
1V8
7
CONFIG[0]
CONFIG_HOST[0]
I
Configuration pin, see also Table 7: Host interface
configuration options
1V8
8
CONFIG[1]
CONFIG_HOST[1]
I
Configuration pin, see also Table 7: Host interface
configuration options
1V8

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No.
Name
Chip pin
I/O1
Description
Domain
9
GPIO_13
GPIO[13]
I/O
Optional host to Wi-Fi out-of-band wake-up signal
(input)
VIO
10
HOST_WAKE
GPIO[1]
I/O
Wi-Fi to host out-of-band wake-up signal (output)
VIO
11
GPIO_12
GPIO[12]
I/O
Optional host to Bluetooth out-of-band wake-up signal
(input)
VIO
12
GPIO_20
GPIO[20]
I/O
Bluetooth to host out-of-band wake-up signal (output)
GPIO_1 or GPIO_4 can be used as alternative signals.
VIO
13
LTE_COEX_TX
GPIO[17] /
JTAG_TDO
I/O
Configuration pin, see also Table 8: Additional
configuration pins
VIO
14
LTE_COEX_RX
GPIO[16] /
JTAG_TDI
I/O
VIO
15
PCM_SYNC
PCM_SYNC /
GPIO[7]
I/O
PCM frame sync, can be output (master) or input (slave)
VIO
16
PCM_CLK
PCM_CLK /
GPIO[6]
I/O
PCM clock, can be output (master) or input (slave)
VIO
17
PCM_OUT
PCM_DOUT /
GPIO[5]
O
PCM data output
Configuration pin, see also Table 8: Additional
configuration pins
VIO
18
PCM_IN
PCM_DIN /
GPIO[4]
I
PCM data input
VIO
19
GND
GND
Ground
GND
20
GND
GND
Ground
GND
21
ANT2
NC
Reserved (Do not connect)
-
22
GND
GND
Ground
GND
23
GND
GND
Ground
GND
24
ANT0
RF
Bluetooth antenna signal. Do not connect to DC
VBAT
25
GND
GND
Ground
GND
26
ANT3
NC
Reserved (Do not connect)
-
27
GND
GND
Ground
GND
28
GND
GND
Ground
GND
29
ANT1
RF
Wi-Fi dual-band antenna signal. Do not connect to DC
VBAT
30
GND
GND
Ground
GND
31
GND
GND
Ground
GND
32
GPIO_14
GPIO[14] /
JTAG_TCK
I/O
Can be used as Wi-Fi independent reset signal (input)
VIO
33
GPIO_15
GPIO[15] /
JTAG_TMS
I/O
Can be used as Bluetooth independent reset signal
(input)
VIO
34
GPIO_2
GPIO[2]
I/O
VIO
35
GPIO_3
GPIO[3]
I/O
VIO
36
BT_UART_TX
UART_SOUT /
GPIO[8]
O
Bluetooth UART serial data output
Configuration pin, see also Table 8: Additional
configuration pins
VIO
37
BT_UART_RX
UART_SIN /
GPIO[9]
I
Bluetooth UART serial data input
VIO
38
BT_UART_RTS
UART_RTSn /
GPIO[11]
O
Bluetooth UART active-low request-to-send signal
(output)
Configuration pin, see also Table 8: Additional
configuration pins
VIO
39
BT_UART_CTS
UART_CTSn /
GPIO[10]
I
Bluetooth UART active-low clear-to-send signal (input)
VIO
40
GPIO_18
GPIO[18]
I/O
VIO
41
GPIO_19
GPIO[19]
I/O
VIO

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Table 4: JODY-W2 pin description
Main supply inputs
JODY-W2 series modules are supplied through the VBAT/VIO/1V8 pins. VBAT supplies power to the
internal power management circuitry that includes a SMPS converter and a LDO that source the
system ASIC.
The current drawn by the JODY-W2 series through the VBAT pin can vary by several orders of
magnitude depending on the operation mode and state. It changes from high current consumption
during Wi-Fi transmission at maximum RF power level in connected-mode to low current consumption
during low power idle-mode with the power saving configuration enabled.
The electrical requirements for supply voltages are described in the JODY-W2 series data sheet [2].
No.
Name
Chip pin
I/O1
Description
Domain
42
GPIO_0
GPIO[0]
I/O
VIO
43-48
NC
NC
Reserved (Do not connect)
-
49
GND
GND
Ground
GND
50
SD_D2
SD_DAT[2]
I/O
SDIO data line bit [2]
1V8
51
SD_D3
SD_DAT[3]
I/O
SDIO data line bit [3]
1V8
52
SD_CMD
SD_CMD
I/O
SDIO Command line
1V8
53
SD_CLK
SD_CLK
I
SDIO Clock input
1V8
54
SD_D0
SD_DAT[0]
I/O
SDIO data line bit [0]
1V8
55
SD_D1
SD_DAT[1]
I/O
SDIO data line bit [1]
1V8
56
NC
NC
Reserved (Do not connect)
-
57
PG
OD
Open-drain output from the internal DC/DC converter,
which indicates the power quality of the 2.2 V rail. High
impedance indicates power good. Low level indicates
2.2 V is not in power good.
A (100 kΩ) pull-up resistor must be connected to this pin
to detect the power good state.
-
58
PDn
PDn
I
Power-down interface of the chipset:
0 = power-down mode
1 = normal mode
Can accept an input of 1.8 V to 4.5 V.
No Internal pull-up on this pin.
1V8
59
CORE_PDn
I
Enable pin of the core voltage regulator:
0 = power supply off
Connect with PDn
1V8
60
LPO_IN
SPL_CLK_IN
I
Sleep clock input (optional)
32.768 kHz clock input used for lower power operation in
sleep mode.
Only supported on professional grade variants:JODY-
W263-xxB
VIO
-
Exposed Pins
GND
15 Ground/Thermal exposed pins
Connect to ground, see also Thermal guidelines
GND

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Rail
Allowable Ripple (peak to peak)2over DC supply
Current consumption, peak
10-100 kHz
100 kHz-1 MHz
>1 MHz
VBAT (3.3 V)
65 mVpk-pk
25 mVpk-pk
10 mVpk-pk
0.8 A
VIO + 1V8
65 mVpk-pk
25 mVpk-pk
10 mVpk-pk
300 mA + sink current to other devices
Table 5: Summary of voltage supply requirements
JODY-W2 series modules are powered by one of the following DC supplies:
•Switching Mode Power Supply (SMPS)
•Low Drop Out (LDO) regulator
The SMPS is the ideal choice when the available primary supply source has significantly higher value
than the operating supply voltage of the JODY-W2 series modules. The use of SMPS provides the
best power efficiency for the overall application and minimizes current drawn from the main supply
source.
⚠When choosing the SMPS, ensure that the AC voltage ripple at switching frequency does not
exceed the requirements as specified in Table 5. The use of an LDO linear regulator is convenient
for a primary supply with a relatively small difference to the supply voltage where the typical
85-90% efficiency of the switching regulator leads to minimal current saving. Linear regulators
are not recommended for high voltage step-down as they dissipate a considerable amount of
energy.
Independent of the selected DC power supply, it is crucial that it can handle the high peak current
generated by the module. A margin of at least 20% over the specified peak current is recommended
when designing the power supply for the module.
1.3 System function interfaces
Power-up sequence
The module power-up sequence can be initiated by applying the respective voltage to the
VBAT/VIO/1V8 supply pins and deasserting PDn (logic level 1) and CORE_PDn (logic level 1). Firmware
download is required every time PDn and CORE_PDn signals are asserted. It is advisable to tie PDn
and CORE_PDn together.
JODY-W2 includes an internal SMPS voltage generator followed by an internal LDO which generates
the supply voltage to the supply nodes of the internal ASIC.
Figure 4 shows the recommended power-up sequence of the module. With VIO set to 3.3V, VIO must
be applied before VBAT. With VIO set to 1.8 V, the order of VIO and VBAT does not matter. Once the
internal Switched Mode Power Supply (SMPS) has stabilized to 90% (taking up to 1.15 ms), 1V8 can
be applied followed by the de-assertion of PDn and CORE_PDn.
PG is an open-drain output used to sense when the internal DC/DC has stabilized. The output is set in
a high-impedance state when the internal voltage is "good". An external 100 kΩ pull-up resistor must
be connected to PG to ensure that the signal is in an affirmative logic-high level. A low-level state
indicates that the power is “not good”. External power-up logic can monitor the transition of PG to
high or wait at least 1.15 ms before applying 18V and continuing the power-up sequence.
2
Ripple measured on the power connectors of u-blox EVK.

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Figure 3: Power-up sequences for VIO=3.3 V or 1.8 V
Figure 4: Optional power-up sequences for VIO=1.8 V
Reset
The internal power-up reset logic means that an external reset is not necessary for proper operation,
although it can be used by the host controller through PDn and CORE_PDn in case of abnormal module
behavior.
JODY-W2 is reset to its default operating state by any of the following events:
•Module is powered on and internal voltages are good
•Software or firmware reset
•Asserting PDn and CORE_PDn
Power-off sequence
It is advisable to ramp down VBAT followed by 1V8. PDn must be asserted when powering down the
module.
One of the following conditions must be met before Power-on Reset is triggered again:
•PDn and CORE_PDn asserted
•PDn asserted and 1V8 discharged to less than 0.2 V

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Figure 5: Power-down sequence of JODY-W2 module
Wake-up signals
JODY-W2 provides module-to-host, wake-up signals that are used to exit the host from any sleep
mode over Wi-Fi or Bluetooth. The wake-up signals are powered by the VIO voltage domain.
Name
Module pin
Chipset GPIO
Description
HOST_WAKE
10
GPIO_1
Wi-Fi to host out-of-band wake-up signal (output)
GPIO_20
12
GPIO_20
Bluetooth to host out-of-band wake-up signal (output)
PCM_IN
18
GPIO_4
Alternative Bluetooth to out-of-band wake-up signal if PCM is not
used (output)
Table 6: Wake-up signal definition
Configuration pins
Two dedicated boot-strap configuration pins (CONFIG[0], CONFIG[1]) determine the configuration of
the host interface after system reset. Additional multiplexed pins (PCM_OUT,LTE_COEX_TX,
BT_UART_TX, BT_UART_RTS) are used as configuration inputs following a reset and revert to their
normal function immediately after system reset.
By default, the configuration pins are high at logic level 1, unless otherwise noted. A 100 kΩpull down
resistor to ground is required to set the pins low. No external circuitry is required to set a configuration
pin to a high level.
Table 7 describes the boot-strap configuration options that are set by CONFIG[0] and CONFIG[1] pins
and used to configure the host communication interfaces:
•SDIO-UART: Wi-Fi commands and data are transferred through the SDIO bus to the module. The
high-speed UART interface is used for Bluetooth communication.
•SDIO-SDIO: Wi-Fi and Bluetooth communication are transferred through the SDIO interface.
CONFIG[1]
CONFIG[0]
Wi-Fi
Bluetooth
Firmware download
Number of SDIO functions
1
0
SDIO
UART
SDIO+UART (parallel/Serial)
1 (Wi-Fi)
1
1
SDIO
SDIO
SDIO+SDIO (parallel/Serial)
2 (Wi-Fi, Bluetooth)
Table 7: Host interface configuration options
Additional configuration pins must be set to their pre-requisite states following a reset as shown in
Table 8. The Internal PU/PD sets the default logic level if the pin is not connected to any external
component.
Name
Pin
Description
Internal PU/PD
PCM_OUT
17
Shall be set high during reset
Weak PU
BT_UART_RTS
38
Shall be set high during reset
Weak PU

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Name
Pin
Description
Internal PU/PD
LTE_COEX_TX
13
Shall be set high during reset
Weak PU
BT_UART_TX
36
Shall be set low during reset
A 51 kΩpull-down resistor is implemented on the module.
Table 8: Additional configuration pins
1.4 Data communication interfaces
JODY-W2 series modules use SDIO 3.0 and high-speed UART as host interface. The Wi-Fi traffic is
always communicated through the SDIO host interface. Depending on the configuration, the
high-speed UART interface can be configured for the Bluetooth/Bluetooth LE traffic between the host
and the JODY-W2 module series.
⚠Use of the high-speed UART interface is only possible with the SDIO-UART software package. The
SDIO-SDIO software package supports only the SDIO host interface.
SDIO 3.0 interface
JODY-W2 series modules include a SDIO device interface compatible with the industry standard SDIO
3.0 specification (UHS-I, up to 104 Mbyte/s) and allows a host controller using the SDIO bus protocol
to access Wi-Fi and Bluetooth functions. The modules also support legacy modes, such as default
speed and High-Speed modes.
☞The SDIO signal voltage is fixed to 1.8 V for Default Speed and High-Speed modes.
A module acts as a device on the SDIO bus. Table 9 summarizes the bus speed modes supported by
the module.
Bus Speed Mode
Max. Bus Speed [MB/s]
Max. Clock Frequency [MHz]
Signal Voltage (1V8) [V]
SDR104
104
208
1.8
SDR50
50
100
1.8
DDR50
50
50
1.8
SDR25
25
50
1.8
SDR12
12.5
25
1.8
High Speed
25
50
Only supported at 1.8 V
Default Speed
12.5
25
Only supported at 1.8 V
Table 9: SDIO supported rates for JODY-W2
Pull-up resistors are required for all SDIO data and command lines. These pull-up resistors can be
provided either externally on the host PCB or internally in the host application processor. JODY-W2
includes programmable internal PU/PD. Depending on the routing of the SDIO lines on the host,
termination resistors in series to the traces might also be needed. This to improve signal integrity or
reduce EMC radiation. See also Data communication interfaces.
Name
I/O
Description
Remarks
SD_CLK
I
SDIO Clock input
SD_CMD
I/O
SDIO Command line
Pull-up resistors are required
SD_D0
I/O
SDIO Data line bit [0]
Pull-up resistors are required
SD_D1
I/O
SDIO Data line bit [1]
Pull-up resistors are required
SD_D2
I/O
SDIO Data line bit [2]
Pull-up resistors are required
SD_D3
I/O
SDIO Data line bit [3]
Pull-up resistors are required
Table 10: SDIO signal definition
The SDIO host interface pins of the module are powered by the 1V8 voltage domain.

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High Speed UART interface
The JODY-W2 series modules support a high-speed Universal Asynchronous Receiver/Transmitter
(UART) interface in compliance with the industry standard 16550 specification. The main features of
the UART interface are:
•FIFO mode permanently selected for transmit and receive operations
•Two pins for transmit and receive operations
•Two flow control pins (RTS/CTS)
•Interrupt triggers for low-power, high throughput operation
•Supports standard baud rates and high throughput up to 4 Mbit/s. The default baud rate after
reset is 3000000 baud.
The UART interface operation includes:
•Uploading the firmware to the module
•Bluetooth data
Name
I/O
Description
Remarks
BT_UART_TX
O
UART TX signal
Connect to Host RX. Used as configuration pin. See also
Configuration pins.
BT_UART_RX
I
UART RX signal
Connect to Host TX
BT_UART_RTS
O
UART RTS signal
Connect to Host CTS. Used as configuration pin. See also
Configuration pins.
BT_UART_CTS
I
UART CTS signal
Connect to Host RTS
Table 11: UART signal description
High Speed UART signals are powered by the VIO voltage domain.
PCM - Audio interface
JODY-W2 series modules provide one bi-directional 4-wire PCM digital audio interface that can be
used for digital audio communication with external digital audio devices as an audio codec. The PCM
interface supports:
•Master or slave mode
•PCM bit width size of 8 bit or 16 bit
•Up to 4 slots with configurable bit width and start positions
•Short frame and long frame synchronization
Name
I/O
Description
Remarks
PCM_CLK
I/O
PCM clock
Output if Master, Input if Slave
PCM_SYNC
I/O
PCM frame sync
Output if Master, Input if Slave
PCM_IN
I
PCM data in
PCM_OUT
O
PCM data out
Used as configuration pin. See also Configuration pins.
Table 12: PCM digital audio signal description
The PCM signals are powered by the VIO voltage domain.
Low power oscillator
For professional grade modules, an optional external low-frequency clock for low-power mode timing
can be connected to the LPO_IN pin. The external LPO must meet the requirements listed in Table 14.
If no external sleep clock is used, leave this pin unconnected.

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Name
I/O
Description
Remarks
LPO_IN
I
32.768 kHz clock input
Failsafe pin.
Table 13: External 32.768 kHz sleep clock signal description
LPO_IN is a failsafe input, clock signal that can be applied to the pin when the module is not powered
and the requirements in Table 14 are fulfilled.
☞Not applicable for automotive grade module variants.
Parameter
LPO clock
Unit
Nominal input frequency
32.768
kHz
Frequency accuracy
±250
ppm
Duty cycle
30 –70
%
Input signal accuracy
200 –3300
mV, pkpk
Signal type
Square-wave or Sine-wave
-
Input impedance3
> 100
kΩ
< 5
pF
Clock jitter (during startup)
< 10,000
ppm
Table 14: External 32.768 kHz sleep clock specification
JTAG –Test Interface
A JTAG test interface is supported on chipset pins GPIO14–17. Table 15 shows the mapping between
chipset and module pins.
Chip pin name
Module pin name
Supply domain
Description
GPIO_14
GPIO_14
VIO
JTAG_TCK test clock (Input)
GPIO_15
GPIO_15
VIO
JTAG_TMS controller select (Input)
GPIO_16
LTE_COEX_RX
VIO
UART_LTE_SIN / JTAG_TDI test data input (Input)
GPIO_17
LTE_COEX_TX
VIO
UART_LTE_SOUT / JTAG_TDO test data output (Output)
Table 15: JTAG signal mapping
1.5 Antenna interfaces
Wi-Fi and Bluetooth antennas
JODY-W2 provides two antenna pins, one for dual-band Wi-Fi connectivity (ANT1) and another for
Bluetooth (ANT0). The following recommendations apply to developing an antenna interface for the
JODY-W2 module:
•Where possible, consider integrating in the end product the u-blox reference design to minimize
the effort on the certification process. For the full list of available reference designs, see the
JODY-W2 antenna reference design, application note [15].
•The ANT0 and ANT1 pins of JODY-W2 have a nominal characteristic impedance of 50 and must
be connected to the external antennas through a 50 transmission line to allow proper RF
transmission and reception.
•Good isolation must be provided between the various antennas in the system. Special care shall be
taken to maximize isolation between the antennas operating in the same or nearby bands.
For information describing how to properly design circuits compliant with these requirements, see
Antenna interfaces.
3
When power is applied or switched off.

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Approved antenna designs
JODY-W2 modules come with a pre-certified design that can be used to save costs and time during
the certification process. To minimize this effort, the customer is required to implement antenna
layout according to u-blox reference designs. Reference design source files can be provided on request
by u-blox.
4
For Bluetooth and Wi-Fi operation, the module has been tested and approved for use with the
antennas listed in the JODY-W2 series data sheet [2]. The module may be integrated with other
antennas. In this case, the OEM installer must certify his design with respective regulatory agencies.
1.6 Other remarks
Unused pins
☞JODY-W2 modules have pins that are reserved for future use (NC). These pins must be left
unconnected on the application board.
GPIO usage
☞The reconfiguration of signals marked as GPIOs on the JODY-W2 module for applications not
listed in this document depends on the respective firmware release.
4
Reference design will be available after certification.

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2Design-in
2.1 Overview
For an optimal integration of JODY-W2 series modules in the final application board, it is advisable to
follow the design guidelines described in this chapter. Every application circuit must be properly
designed to ensure that the related interface functions correctly, but several specific points require
special attention during the design of the application device.
The following list provides a rank of importance in the application design, starting from the highest
relevance:
•Module antenna connection: ANT0 and ANT1 pins.
Antenna circuit affects the RF compliance of the device integrating JODY-W2 modules with
applicable certification schemes. For schematic and layout design recommendations, see also
Antenna interfaces.
•Module supply: VBAT, VIO/1V8, and GND pins.
The supply circuit affects the RF compliance of the device integrating JODY-W2 modules with
applicable certification schemes. Follow the General high-speed layout guidelines.
•High speed interfaces: SDIO pins.
High speed interfaces can be a source of radiated noise and can affect the compliance with
regulatory standards for radiated emissions. Follow the General high-speed layout guidelines and
recommendations for the SDIO 3.0 interface.
•System functions: PDn and pins described as Configuration pins.
Accurate design is required to ensure that the voltage level is well defined during module boot.
Follow the General high-speed layout guidelines.
•Other pins: High speed UART, PCM, specific signals and NC pins.
Accurate design is required to ensure proper functionality. Follow the General high-speed layout
guidelines and recommendations for the High-speed UART interface.
2.2 Antenna interfaces
JODY-W2 modules provide the following two RF interfaces for connecting the external antennas:
•The ANT0 port for Bluetooth connectivity.
•The ANT1 port for Wi-Fi connectivity.
Both the ANT0 and the ANT1 ports have a nominal characteristic impedance of 50 and must be
connected to the related antenna through a 50 transmission line to allow proper impedance
matching along the RF path. A bad termination of the ANT0 pin (Bluetooth) or the ANT1 pin (Wi-Fi)
may result in poor performance of the module.
For the dual antenna modules, the isolation between the two antennas should be maximized, the
requirements specified in Table 16 and Table 17 should be followed to ensure good performance.
⚠According to FCC regulations, the transmission line from the antenna pin in the module to the
antenna or antenna connector on the host PCB is considered part of the approved antenna design.
Consequently, module integrators must either follow exactly one of the antenna reference design
used in the module’s FCC type approval or certify their own designs. See also the JODY-W2
antenna reference design [15].