VersaLogic Blackbird VL-EPU4562 User manual

Programmer’s
Reference
Manual
REV. May 2018
Blackbird
(VL-EPU-4562)
Intel®Core™-based Embedded
Processing Unit with SATA,
Dual Ethernet, USB, Digital I/O,
Serial, Video, Mini PCIe
Sockets, SPX, Trusted Platform
Module.

EPU-4562 Programmer’s Reference Manual ii
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PC/104, PC/104-Plus, and the PC/104 logo are trademarks of the PC/104 Consortium.
* Other names and brands may be claimed as the property of others.

EPU-4562 Programmer’s Reference Manual iii
Product Release Notes
Release 1.1
Updated Uartmode1 – Uart Mode Register #1 section
Release 1.0
Initial Release.
Support
The EPU-4562 support page contains additional information and resources for this product
including:
Reference Manual (PDF format)
Operating system information and software drivers
Data sheets and manufacturers’ links for chips used in this product
BIOS information and upgrades
Utility routines and benchmark software
The VersaTech KnowledgeBase is an invaluable resource for resolving technical issues with
your VersaLogic product.
VersaTech KnowledgeBase

EPU-4562 Programmer’s Reference Manual iv
Contents
Introduction ...................................................................................................................1
Related Documents.............................................................................................................1
System Resources ........................................................................................................2
Interrupts.............................................................................................................................2
FPGA I/O Space .................................................................................................................2
FPGA Registers.............................................................................................................4
Register Access Key...........................................................................................................4
Reset Status Key.................................................................................................................4
FPGA Register Map ...........................................................................................................5
FPGA Register Descriptions...............................................................................................8
Product Information Registers...............................................................................8
BIOS and Jumper Status Register.......................................................................... 9
Timer Registers....................................................................................................10
Miscellaneous FPGA Registers...........................................................................13
SPI Control Registers ..........................................................................................18
SPI Data Registers...............................................................................................20
SPI Debug Control Register and mSATA/PCIe Select Control Register............21
ADM – ADC Control/Status Register.................................................................21
This register is used as the interrupt control/status register for the TI ADS8668A
and is primarily related to the ALARM signal output from the A/D. .................21
FANCON – Fan Control Register .......................................................................31
FANTACHLS, FANTACHMS – FANTACH Status Registers..........................32
Programming Information for Hardware Interfaces..................................................41
Watchdog Timer...............................................................................................................41
Programmable LED.......................................................................................................... 41
Processor WAKE# Capabilities........................................................................................42
Tables
Table 1: FPGA I/O Map...................................................................................................... 3
Table 2: FPGA Register Map.............................................................................................. 5
Table 3: PCR – Product Code and LED Register............................................................... 8
Table 4: PSR – Product Status Register.............................................................................. 8
Table 5: SCR –Status/Control Register .............................................................................. 9
Table 6: TICR – 8254 Timer Interrupt Control Register.................................................. 10
Table 7: TISR – 8254 Timer Interrupt Status Register..................................................... 11
Table 8: TCR – 8254 Timer Control Register.................................................................. 12
Table 9: MISCSR1 – Misc. Control Register #1.............................................................. 13

Contents
EPU-4562 Programmer’s Reference Manual v
Table 10: MISCSR2 – Misc. Control Register #2............................................................ 15
Table 11: MISCSR3 – Misc. Control Register #3............................................................ 16
Table 11: MISCSR4 – Misc. Control Register #4............................................................ 17
Table 12: SPI Interface Control Register.......................................................................... 18
Table 13: SPI Interface Status Register ............................................................................ 19
Table 14: SPI – SPI Debug Control Register.................................................................... 21
Table 18: DIODIR1 – Digital I/O 8-1 Direction Control Register ................................... 22
Table 19: DIODIR2 – Digital I/O 16-9 Direction Control Register ................................. 22
Table 20: DIOPOL1 – Digital I/O 8-1 Polarity Control Register..................................... 23
Table 21: DIOPOL2 – Digital I/O 16-9 Polarity Control Register................................... 23
Table 22: DIOOUT1 – Digital I/O 8-1 Output Control Register...................................... 23
Table 23: DIOOUT2 – Digital I/O 16-9 Output Control Register.................................... 23
Table 24: DIOIN1 – Digital I/O 8-1 Input Status Register............................................... 24
Table 25: DIOIN2 – Digital I/O 16-9 Input Status Register............................................. 24
Table 26: DIOIMASK1 – Digital I/O 8-1 Interrupt Mask Register.................................. 24
Table 27: DIOIMASK2 – Digital I/O 16-9 Interrupt Mask Register................................ 24
Table 28: DIOISTAT1 – Digital I/O 8-1 Interrupt Mask Register ................................... 24
Table 29: DIOISTAT2 – Digital I/O 16-9 Interrupt Mask Register ................................. 25
Table 30: DIOCR – Digital I/O Control Register............................................................. 25
Table 31: AUXDIR – AUX GPIO Direction Control Register ........................................ 26
Table 32: AUXPOL – AUX GPIO Polarity Control Register.......................................... 26
Table 33: AUXOUT – AUX GPIO Output Control Register........................................... 27
Table 34: AUXIN – AUX GPIO Input Status Register .................................................... 27
Table 35: AUXICR – AUX GPIO Interrupt Mask Register............................................. 27
Table 36: AUXISTAT – AUX GPIO Interrupt Status Register........................................ 27
Table 37: AUXMODE1 – AUX I/O Mode Register ........................................................ 28
Table 38: WDT_CTL – Watchdog Control Register........................................................ 29
Table 39: WDT_VAL – Watchdog Control Register....................................................... 30
Table 40: XCVRMODE – COM Transceiver Mode Register.......................................... 30
Table 41: AUXMODE2 - AUX I/O Mode Register #2.................................................... 31
Table 41: FANCON – Fan Control Register .................................................................... 32
Table 41: FANTACHLS – FANTACH Status Register LS Bits...................................... 33
Table 41: FANTACHMS – FANTACH Status Register MS Bits.................................... 33
Table 42: UART1CR – UART1 Control Register (COM1)............................................. 34
Table 43: UART2CR – UART2 Control Register (COM2)............................................. 35
Table 43: UART3CR – UART3 Control Register (COM3)............................................. 36
Table 43: UART4CR – UART4 Control Register (COM4)............................................. 37
Table 44: UARTMODE1 – UART MODE Register #1................................................... 39
Table 45: UARTMODE2 – UART MODE Register #2................................................... 40

EPU-4562 Programmer’s Reference Manual 1
Introduction
This document provides information for users requiring register-level information for developing
applications with the VL-EPU-4562.
Related Documents
The following documents are available on the EPU-4562 Product Support Web Page:
VL-EPU-4562 Hardware Reference Manual – provides information on the board’s hardware
features including connectors and all interfaces.
Operating System compatibility and software package downloads are available at the VersaLogic
Software Support page.
1

EPU-4562 Programmer’s Reference Manual 2
System Resources
Interrupts
The LPC SERIRQ is used for interrupt interface to the Skylake SoC.
Each of the following devices can have an IRQ interrupt assigned to it and each with an interrupt
enable control for IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, IRQ9, IRQ10, and IRQ11:
8254 timers (with three interrupt status bits)
8x GPIOs (with one interrupt status bit per GPIO)16x Digital I/Os (with 1 interrupt status bit
per GPIO)
COM 1 UART (with 16550 interrupt status bits)
COM 2 UART (with 16550 interrupt status bits)
COM 3 UART (with the usual 16550 interrupt status bits).
COM 4 UART (with the usual 16550 interrupt status bits).
Watchdog timer (one status bit)
Common interrupts can be assigned to multiple devices if software can deal with it (this is
common on UARTs being handled by a common ISR).
Interrupt status bits for everything except the UARTs will “stick” and are cleared by a “write-
one” to a status register bit. The 16550 UART interrupts behave as defined for the 16550
registers and are a pass-through to the LPC SERIRQ.
Per the VersaAPI standard, anytime an interrupt on the SERIRQ is enabled, the slot becomes
active. All interrupts in the SERIRQ are high-true so when the slot becomes active, the slot will
be low when there is no interrupt and high when there is an interrupt.
FPGA I/O Space
The FPGA is mapped into I/O space on the LPC bus. The address range is mapped into a 64 byte
I/O window.
FPGA access: LPC I/O space
FPGA access size: All 8-bit byte accesses (16-bit like registers are aligned on 16-bit word
boundaries to make word access possible in software but the LPC bus still splits the accesses
into two 8-bit accesses)
FPGA address range: 0x1C80 to 0x1CBF (a 64-byte window)
The three 8254 timers only require four bytes of addressing and are located at the end of the
64-byte I/O block. The only requirement is that the base address must be aligned on a 4-byte
block. The table below lists the FPGA’s I/O map.
2

System Resources and Maps
EPU-4562 Programmer’s Reference Manual 3
Table 1: FPGA I/O Map
Address Range Device Size
0x1C80 – 0x1CBB
FPGA registers
60 bytes
0x1CBC – 0x1CBF
8254 timer address registers
4 bytes

EPU-4562 Programmer’s Reference Manual 4
FPGA Registers
This chapter describes the FPGA registers.
Table 2 (beginning on the following page) lists all 64 FPGA registers
Table 3 (refer to page 8) through Table 48 provide bit-level information on the individual
FPGA registers
Register Access Key
Key:
R/W
Read/Write
RO
Read-Only
R/WC
Read-Status/Write-1-to-Clear
WO
Write-Only
ROC
Read-Only and clear-to-0 after reading
RSVD
Not implemented. Returns 0 when read. Writes are
ignored
Reset Status Key
Reset Status Key
POR Power-on reset (only resets one time when input power comes on)
Platform Resets prior to the processor entering the S0 power state (that is, at power-on and in sleep states)
resetSX
•If AUX_PSEN is a '0' in MISCSR1 (default setting), then this is the same as the Platform reset.
•
If AUX_PSEN is programmed to a '1', then it is the same as the Power-On Reset (POR).
n/a Reset doesn't apply to status or reserved registers
3

EPU-4562 Programmer’s Reference Manual 5
FPGA Register Map
Table 2: FPGA Register Map
I/O
Address
Offset
Reset
D7
D6
D5
D4
D3
D2
D1
D0
C80
0
Platform
PLED
PRODUCT_CODE
C81
1
n/a
REV_LEVEL
EXTEMP
CUSTOM
BETA
C82
2
Platform
BIOS_JMP
BIOS_OR
BIOS_SEL
LED_DEBUG
WORKVER
0
WP_JMP
WP_EN
C83
3
Platform
IRQEN
IRQSEL2
IRQSEL1
IRQSEL0
0
IMASK_TC5
IMASK_TC4
IMASK_TC3
C84
4
Platform
INTRTEST
TMRTEST
TMRIN4
TMRIN3
0
ISTAT_TC5
ISTAT_TC4
ISTAT_TC3
C85
5
Platform
TIM5GATE
TIM4GATE
TIM3GATE
TM45MODE
TM4CLKSEL
TM3CLKSEL
TMROCTST
TMRFULL
C86
6
n/a
0
0
0
0
0
0
0
0
C87
7
n/a
0
0
0
0
0
0
0
0
C88
8
Platform
CPOL
CPHA
SPILEN1
SPILEN0
MAN_SS
SS2
SS1
SS0
C89
9
Platform
IRQSEL1
IRQSEL0
SPICLK1
SPICLK0
HW_IRQ_EN
LSBIT_1ST
HW_INT
BUSY
C8A
A
Platform
msb
<============>
lsb
C8B
B
Platform
msb
<============>
lsb
C8C
C
Platform
msb
<============>
lsb
C8D
D
Platform
msb
<============>
lsb
C8E
E
Platform
0
MUXSEL2
MUXSEL1
MUXSEL0
0
SERIRQEN
SPILB
DACLDA
C8F
F
Platform
IRQEN
IRQSEL2
IRQSEL1
IRQSEL0
ADC_RESET
IN_ALARM
ISTAT_ALARM
IMASK_ALAR
M
C90
10
POR
0
0
0
0
MINI3_PSDIS
MINI2_PSDIS
AUX_PSEN
MINI1_PSDIS
C91
11
POR
USB_HUBMOD
E
W_DISABLE
USB_HUBDIS
ETH0_OFF
USB2_OC2
USB2_OC1
USB2_DIS2
USB2_DIS1
C92
12
Platform
PROCHOT
LVDS_OC
0
0
0
PBRESET
0
TPM_PP
C93
13
POR
0
0
USB3_OC2
USB3_OC1
0
0
USB3_DIS2
USB3_DIS1
C94
14
resetSX
DIR_DIO8
DIR_DIO7
DIR_DIO6
DIR_DIO5
DIR_DIO4
DIR_DIO3
DIR_DIO2
DIR_DIO1
C95
15
resetSX
DIR_DIO16
DIR_DIO15
DIR_DIO14
DIR_DIO13
DIR_DIO12
DIR_DIO11
DIR_DIO10
DIR_DIO9
C96
16
resetSX
POL_DIO8
POL_DIO7
POL_DIO6
POL_DIO5
POL_DIO4
POL_DIO3
POL_DIO2
POL_DIO1
C97
17
resetSX
POL_DIO16
POL_DIO15
POL_DIO14
POL_DIO13
POL_DIO12
POL_DIO11
POL_DIO10
POL_DIO9
C98
18
resetSX
OUT_DIO8
OUT_DIO7
OUT_DIO6
OUT_DIO5
OUT_DIO4
OUT_DIO3
OUT_DIO2
OUT_DIO1
C99
19
resetSX
OUT_DIO16
OUT_DIO15
OUT_DIO14
OUT_DIO13
OUT_DIO12
OUT_DIO11
OUT_DIO10
OUT_DIO9
C9A
1A
n/a
IN_DIO8
IN_DIO7
IN_DIO6
IN_DIO5
IN_DIO4
IN_DIO3
IN_DIO2
IN_DIO1
C9B
1B
n/a
IN_DIO16
IN_DIO15
IN_DIO14
IN_DIO13
IN_DIO12
IN_DIO11
IN_DIO10
IN_DIO9

FPGA Registers
EPU-4562 Programmer’s Reference Manual 6
I/O
Address
Offset
Reset
D7
D6
D5
D4
D3
D2
D1
D0
C9C
1C
Platform
IMASK_DIO8
IMASK_DIO7
IMASK_DIO6
IMASK_DIO5
IMASK_DIO4
IMASK_DIO3
IMASK_DIO2
IMASK_DIO1
C9D
1D
Platform
IMASK_DIO16
IMASK_DIO15
IMASK_DIO14
IMASK_DIO13
IMASK_DIO12
IMASK_DIO11
IMASK_DIO10
IMASK_DIO9
C9E
1E
Platform
ISTAT_DIO8
ISTAT_DIO7
ISTAT_DIO6
ISTAT_DIO5
ISTAT_DIO4
ISTAT_DIO3
ISTAT_DIO2
ISTAT_DIO1
C9F
1F
Platform
ISTAT_DIO16
ISTAT_DIO15
ISTAT_DIO14
ISTAT_DIO13
ISTAT_DIO12
ISTAT_DIO11
ISTAT_DIO10
ISTAT_DIO9
CA0
20
Platform
IRQEN
IRQSEL2
IRQSEL1
IRQSEL0
0
0
0
TMREN
CA1
21
resetSX
DIR_GPIO8
DIR_GPIO7
DIR_GPIO6
DIR_GPIO5
DIR_GPIO4
DIR_GPIO3
DIR_GPIO2
DIR_GPIO1
CA2
22
resetSX
POL_GPIO8
POL_GPIO7
POL_GPIO6
POL_GPIO5
POL_GPIO4
POL_GPIO3
POL_GPIO2
POL_GPIO1
CA3
23
resetSX
OUT_GPIO8
OUT_GPIO7
OUT_GPIO6
OUT_GPIO5
OUT_GPIO4
OUT_GPIO3
OUT_GPIO2
OUT_GPIO1
CA4
24
n/a
IN_GPIO8
IN_GPIO7
IN_GPIO6
IN_GPIO5
IN_GPIO4
IN_GPIO3
IN_GPIO2
IN_GPIO1
CA5
25
Platform
IMASK_GPIO8
IMASK_GPIO7
IMASK_GPIO6
IMASK_GPIO5
IMASK_GPIO4
IMASK_GPIO3
IMASK_GPIO2
IMASK_GPIO1
CA6
26
Platform
ISTAT_GPIO8
ISTAT_GPIO7
ISTAT_GPIO6
ISTAT_GPIO5
ISTAT_GPIO4
ISTAT_GPIO3
ISTAT_GPIO2
ISTAT_GPIO1
CA7
27
resetSX
MODE_GPIO8
MODE_GPIO7
MODE_GPIO6
MODE_GPIO5
MODE_GPIO4
MODE_GPIO3
MODE_GPIO2
MODE_GPIO1
CA8
28
Platform
IRQEN
IRQSEL2
IRQSEL1
IRQSEL0
0
RESET_EN
WDT_EN
WDT_STAT
CA9
29
Platform
msb
<============>
lsb
CAA
2A
Platform
0
0
0
0
COM4_MODE
COM3_MODE
COM2_MODE
COM1_MODE
CAB
2B
Platform
IRQEN
IRQSEL2
IRQSEL1
IRQSEL0
0
0
0
0
CAC
2C
Platform
COM_MODE
0
0
0
0
0
0
FAN_OFF
CAD
2D
n/a
0
0
0
0
0
0
0
0
CAE
2E
Platform
msb
<============>
lsb
CAF
2F
Platform
msb
<============>
lsb
CB0
30
n/a
0
0
0
0
0
0
0
0
CB1
31
n/a
0
0
0
0
0
0
0
0
CB2
32
Platform
IRQEN
IRQSEL2
IRQSEL1
IRQSEL0
UART1_BASE
3
UART1_BASE
2
UART1_BASE
1
UART1_BASE0
CB3
33
Platform
IRQEN
IRQSEL2
IRQSEL1
IRQSEL0
UART2_BASE
3
UART2_BASE
2
UART2_BASE
1
UART2_BASE0
CB4
34
Platform
IRQEN
IRQSEL2
IRQSEL1
IRQSEL0
UART3_BASE
3
UART3_BASE
2
UART3_BASE
1
UART3_BASE0
CB5
35
Platform
IRQEN
IRQSEL2
IRQSEL1
IRQSEL0
UART4_BASE
3
UART4_BASE
2
UART4_BASE
1
UART4_BASE0
CB6
36
Platform
UART4_485ADC
UART3_485ADC
UART2_485ADC
UART1_485ADC
UART4_EN
UART3_EN
UART2_EN
UART1_EN
CB7
37
Platform
0
0
0
0
0
0
0
FAST_MODE
CB8
38
n/a
0
0
0
0
0
0
0
0
CB9
39
n/a
0
0
0
0
0
0
0
0
CBA
3A
n/a
0
0
0
0
0
0
0
0

FPGA Registers
EPU-4562 Programmer’s Reference Manual 7
I/O
Address
Offset
Reset
D7
D6
D5
D4
D3
D2
D1
D0
CBB
3B
n/a
0
0
0
0
0
0
0
0
CBC
3C
Platform
msb
<============>
lsb
CBD
3D
Platform
msb
<============>
lsb
CBE
3E
Platform
msb
<============>
lsb
CBF
3F
Platform
msb
<============>
lsb

EPU-4562 Programmer’s Reference Manual 8
FPGA Register Descriptions
Key:
R/W
Read/Write
RO
Read-Only
R/WC
Read-Status/Write-1-to-Clear
WO
Write-Only
ROC
Read-Only and clear-to-0 after reading
RSVD
Not implemented. Returns 0 when read. Writes are
ignored
PRODUCT INFORMATION REGISTERS
This register drives the PLED on the paddleboard. It also provides read access to the product
code.
Table 3: PCR – Product Code and LED Register
Bit Identifier Access Default Description
7 PLED R/W 0 Drives the programmable LED on the paddleboard. 0 – LED is off (default)
1 – LED is on
6-0
PRODUCT_CODE
RO
0010011
Product Code for the EPU-4562 (0x13)
Table 4: PSR – Product Status Register
Bit Identifier Access Default Description
7:3 REV_LEVEL[4:0] RO N/A
Revision level of the PLD (incremented every FPGA release)
0 – Indicates production release revision level when BETA
status bit (bit 0) is set to ‘0’
1 – Indicates development release revision level when BETA
status bit (bit 0) is set to ‘1’
2 EXTEMP RO N/A Extended or Standard Temp Status (set via external resistor): 0 – Standard Temp
1 – Extended Temp (always set)
1 CUSTOM RO N/A Custom or Standard Product Status (set in FPGA): 0 – Standard Product
1 – Custom Product or PLD/FPGA
0 BETA RO N/A Beta or Production Status (set in FPGA): 1 – Beta (or Debug)
0 – Production

FPGA Registers
EPU-4562 Programmer’s Reference Manual 9
BIOS AND JUMPER STATUS REGISTER
Table 5: SCR –Status/Control Register
Bit Identifier Access Default Description
7 BIOS_JMP RO N/A Status of the external BIOS switch (jumper):
1 – Primary BIOS selected (the one on the COM Module)
0 – Backup BIOS selected (the one on the base board)
Note: For this implementation this reads the status of the jumper
all the time is essentially the “AND” of the jumper setting and (if
the BIOS_OR is set to a ‘1’) the BIOS_SEL setting. Note that if
BIOS_SEL sets a ‘1’ but a ‘0’ is read here then that means the
external jumper is installed.
6 BIOS_OR R/W 0 BIOS Switch (jumper) Override
0 – BIOS Select will follow the BIOS_JMP switch setting (FPGA
BIOS_SEL setting has no affect)
1 – BIOS Select will follow the BIOS_SEL register setting
5 BIOS_SEL R/W 0 BIOS Select (see BIOS_OR):
0 – Primary BIOS selected (the one on the COM Module)
1 – Backup BIOS selected (the one on the base board)
Note: If the external BIOS configuration jumper is set to Backup
then setting this will not have any affect. The jumper must not be
installed to use this selection mode. Must have BIOS_OR set to a
‘1’ for this to have any affect.
4 LED_DEBUG R/W 0 Debug LED (controls the yellow LED): 0 – LED is off and follows its primary function (MSATA_DAS)
1 – LED is on
3 WORKVER RO N/A
Status used to indicate that the FPGA is not officially released
and is still in a working state.
0 – FPGA is released
1 – FPGA is in a working state (not released)
2
RESERVED RO
N/A
Reserved. Writes are ignored; reads always return 0.
1 WP_JMP RO N/A Back-up BIOS Write protect jumper status. WP_EN has to be set
to a ‘0’ to read the actual jumper.
0 – Jumper is installed (write-protect is enabled)
1 – Jumper is removed (not write protected)
0 WP_EN R/W 0 Back-up BIOS Write protect control. It drives an open-drain
output.
0 – not write protected (open-drain output is Hi-Z so WP jumper
can be read)
1 – write protected (drives output low)

FPGA Registers
EPU-4562 Programmer’s Reference Manual 10
TIMER REGISTERS
The FPGA implements an 8254-compatible timer/counter that includes three 16-bit timers.
Table 6: TICR – 8254 Timer Interrupt Control Register
Bit Identifier Access Default Description
7 IRQEN R/W 0 8254 Timer interrupt enable/disable: 0 – Interrupts disabled
1 – Interrupts enabled
6-4 IRQSEL(2:0) R/W 000
8254 Timer interrupt IRQ select in LPC SERIRQ:
000 – IRQ3
001 – IRQ4
010 – IRQ5
011 – IRQ10
100 – IRQ6
101 – IRQ7
110 – IRQ9
111 – IRQ11
3 RESERVED RO 0 Reserved. Writes are ignored; reads always return 0.
2 IMASK_TC5 R/W 0 8254 timer #5 interrupt mask: 0 – Interrupt disabled
1 – Interrupt enabled
1 IMASK_TC4 R/W 0 8254 timer #4 interrupt mask: 0 – Interrupt disabled
1 – Interrupt enabled
0 IMASK_TC3 R/W 0 8254 timer #3 interrupt mask: 0 – Interrupt disabled
1 – Interrupt enabled

FPGA Registers
EPU-4562 Programmer’s Reference Manual 11
Table 7: TISR – 8254 Timer Interrupt Status Register
Bit Identifier Access Default Description
7
RESERVED
RO
0
Reserved. Writes are ignored; reads always return 0.
6
RESERVED
RO
0
Reserved. Writes are ignored; reads always return 0.
5
RESERVED
RO
0
Reserved. Writes are ignored; reads always return 0.
4
RESERVED
RO
0
Reserved. Writes are ignored; reads always return 0.
3
RESERVED
RO
0
Reserved. Writes are ignored; reads always return 0.
2 ISTAT_TC5 RW/C N/A
Status for the 8254 Timer #5 output (terminal count) interrupt
when read. This bit is read-status and a write-1-to-clear.
0 – Timer output (terminal count) has not transitioned from 0 to
a 1 level
1 – Timer output (terminal count) has transitioned from a 0 to a
1 level
1 ISTAT_TC4 RW/C N/A
Status for the 8254 Timer #4 output (terminal count) interrupt
when read. This bit is read-status and a write-1-to-clear.
0 – Timer output (terminal count) has not transitioned from 0 to
a 1 level
1 – Timer output (terminal count) has transitioned from a 0 to a
1 level
0 ISTAT_TC3 RW/C N/A
Status for the 8254 Timer #3 output (terminal count) interrupt
when read. This bit is read-status and a write-1-to-clear.
0 – Timer output (terminal count) has not transitioned from 0 to
a 1 level
1 – Timer output (terminal count) has transitioned from a 0 to a
1 level

FPGA Registers
EPU-4562 Programmer’s Reference Manual 12
Table 8: TCR – 8254 Timer Control Register
Bit Identifier Access Default Description
7 TMR5GATE R/W 0
Debug/Test Only: Controls the “gate” signal on 8254 timer #5 when not
using an external gate signal:
0 – Gate on signal GCTC5 is disabled
1 – Gate on signal GCTC5 is enabled
Always set to 0 when configuring timer modes except when TMRFULL
is ‘0’ and then it should be set to ‘1’ and not changed unless using
internal clocking.
6 TMR4GATE R/W 0
Debug/Test Only: Controls the “gate” signal on 8254 timer #4 when not
using an external gate signal:
0 – Gate on signal GCTC4 is disabled
1 – Gate on signal GCTC4 is enabled
Always set to 0 when configuring timer modes except when TMRFULL
is ‘0’ and then it should be set to ‘1’ and not changed unless using
internal clocking
5 TMR3GATE R/W 0
Debug/Test Only: Controls the “gate” signal on 8254 timer #3 when not
using an external gate signal:
0 – Gate on signal GCTC3 is disabled
1 – Gate on signal GCTC3 is enabled
Always set to 0 when configuring timer modes except when TMRFULL
is ‘0’ and then it should be set to ‘1’ and not changed unless using
internal clocking
4 TM45MODE R/W 0
Mode to set timers #4 and #5 in:
0 – Timer #4 and #5 form one 32-bit timer controlled by timer #1 signals
1 – Timer #4 and Timer #5 are separate 16-bit timers with their own
control signals.
Almost always used in 32-bit mode especially when TMRFULL is a ‘0’
(the 16-bit timer #5 if of limited use)
3 TM4CLKSEL R/W 0
Timer #4 Clock Select:
0 – Use internal 4.125 MHz clock (derived from LPC clock)
1 – Use external ICTC4 assigned to digital I/O
Timer #5 is always on internal clock if configured as a 16-bit clock
2 TM3CLKSEL R/W 0 Timer #3 Clock Select:
0 – Use internal 4.125 MHz clock (derived from LPC clock)
1 – Use external ICTC3 assigned to digital I/O
1 TMROCTST R/W 0
Debug/Test Only: Used to derive OCTCx outputs with TIMxGATE
signals for continuity testing only:
0 – Normal operation
1 – Drive OCTCx outputs with corresponding TMRxGATE control
registers (for example, OCTC4 with TMR4GATE) for continuity testing.
0
TMRFULL
R/W
0
This bit can be read or written to, but it has no function.

FPGA Registers
EPU-4562 Programmer’s Reference Manual 13
MISCELLANEOUS FPGAREGISTERS
MISCSR1 – Miscellaneous Control Register #1
This is a register in the always-on power well of the FPGA. It holds its state during sleep modes
and can only be reset by a power cycle. This is a placeholder register for features like pushing the
power-button and also for software initiated resets should those be needed.
Reset: This register is only reset by the main power-on reset since it must maintain its state in
Sleep modes (for example, S3).
Table 9: MISCSR1 – Misc. Control Register #1
Bits Identifier Access Default Description
7-4 Reserved RO 00000 Reserved. Writes are ignored; reads always return 0.
2 MINI2_PSDIS R/W 0
Minicard #2 3.3 V power disable
0 – Minicard 3.3 V power stays on always (this is normally how
minicards operate if they support any Wake events)
1 – Minicard 3.3 V power will be turned off when not in S0 (in sleep
modes).
The Minicard 3.3 V power switch is controlled by the “OR” of the S0
power control signal and the inverse of MINI2_PSDIS.
1 AUX_PSEN R/W 0
CBR-4005B 8xGPIO (sometimes called “AUX” GPIOs) I/O Power
Enable
0 – The GPIO pullups will be powered down in sleep modes (only
power in S0)
1 – The GPIO pullups will not be powered down in sleep modes
and the configuration will remain.
This power is used for both the GPIO pullup voltage and for the
3.3V power on Pin 37 of the User Interface connector J2.
Note: Some register resets are conditional on the state of
AUX_PSEN
0 MINI1_PSDIS R/W 0
Minicard #1 3.3 V power disable
0 – Minicard 3.3 V power stays on always (this is normally how
minicards operate if they support any Wake events)
1 – Minicard 3.3 V power will be turned off when not in S0 (in sleep
modes).
The Minicard 3.3 V power switch is controlled by the “OR” of the S0
power control signal and the inverse of MINI1_PSDIS.

FPGA Registers
EPU-4562 Programmer’s Reference Manual 14
MISCSR2 – Miscellaneous Control Register #2
This is a register in the always-on power well of the FPGA. It holds its state during sleep modes
and can only be reset by a power cycle. It is primarily used for control signals for the always-
powered Ethernet controllers and the USB hubs. This register is only reset by the main power-on
reset since it must maintain its state in sleep modes (for example, S3).

FPGA Registers
EPU-4562 Programmer’s Reference Manual 15
Table 10: MISCSR2 – Misc. Control Register #2
Bit Identifier Access Default Description
7
USB_HUBMODE
R/W 0
Determines whether the hub resets only once (to support wake-up from
sleep modes on USB ports) or resets every time it enters sleep modes
using the platform reset:
0 – USB Hub will be reset once at power on. Use USB_HUBDIS to
manually control the reset if necessary. This supports USB Wake-up
modes
1 – USB Hub will be reset by platform reset every time (will be reset
when entering all sleep modes). USB ports cannot be used to wake-up
6 W_DISABLE R/W 0
Controls the W_DISABLE (Wireless Disable) signal going to the PCIe
Minicards (disables both minicards if asserted):
0 – W_DISABLE signal is not asserted (Enabled)
1 – W_DISABLE signal is asserted (Disabled)
Note: There are other control sources that can be configured to control
this signal and if enabled the control becomes the “OR” of all sources
5 USB_HUBDIS R/W 0
Control the reset on the USB2513B Hub (used for 3x Minicard USB
ports).
0 – USB2513 Hub is Enabled (reset released)
1 – USB2513 Hub is in Reset
Note: FPGA was changed so that Platform reset drives this reset once
at power on.
4 ETHOFF0 R/W 0
Disables Ethernet controller #0 (controls the ETH_OFF# input to the
I210-IT):
0 – Ethernet controller is enabled (On)
1 – Ethernet controller is disabled (Off)
3 USB2_OC2 RO N/A
Overcurrent Status from the USB 2.0 port 2,3 VBUS power switches.
This signal also passed to the fourth USB_6_7_OC# input on the COM
Express connector.
0 – VBUS power switch is not in overcurrent (either OK or disabled)
1 – VBUS power switch is in overcurrent and is now off.
Note: The power switches latch-off in overcurrent and can only be re-
enabled by a power-cycle or by setting this bit to a ‘1’, wait >1msec and
then a ‘0’
2 USB2_OC1 RO N/A
Overcurrent Status from the USB 2.0 port 0,1 VBUS power switches.
This signal also passed to the third USB_4_5_OC# input on the COM
Express connector.
0 – VBUS power switch is not in overcurrent (either OK or disabled)
1 – VBUS power switch is in overcurrent and is now off.
Note: The power switches latch-off in overcurrent and can only be re-
enabled by a power-cycle or by setting this bit to a ‘1’, wait >1msec and
then a ‘0’
1 USB2_DIS2 R/W 0
Disable control for the paddleboard USB 2.0 ports 2,3 VBUS power
switches (there are two power-switches but they have a common power
enable and overcurrent status)
0 – VBUS power switches are enabled
1 – VBUS power switched are disabled.
Note: The power switches latch-off in overcurrent and can only be re-
enabled by a power-cycle or by setting this bit to a ‘1’, wait >1msec and
then a ‘0’