VersaLogic Viper User manual

Programmer’s
Reference
Manual
REV. November 2017
Viper
(VL-EBX-38)
Intel®Atom™-based Single
Board Computer with Dual
Ethernet, Video, USB, SATA,
Serial I/O, Digital I/O, Analog
I/O, Trusted Platform Module
security, Counter/Timers, Mini
PCIe, mSATA, PC/104-Plus
Interface, and SPX.

ii VL-EBX-38 Programmer’s Reference Manual
WWW.VERSALOGIC.COM
12100 SW Tualatin Road
Tualatin, OR 97062-7341
[phone]
Fax [phone]
Copyright © 2017 VersaLogic Corp. All rights reserved.
Notice:
Although every effort has been made to ensure this document is error-free, VersaLogic makes no
representations or warranties with respect to this product and specifically disclaims any implied warranties
of merchantability or fitness for any particular purpose.
VersaLogic reserves the right to revise this product and associated documentation at any time without
obligation to notify anyone of such changes.
PC/104, PC/104-Plus, and the PC/104 logo are trademarks of the PC/104 Consortium.
* Other names and brands may be claimed as the property of others.
© Copyright 2017 VersaLogic Corporation

VL-EBX-38 Programmer’s Reference Manual iii
Product Release Notes
Release 1.06
Updated AUX_PSEN and GPIO3 register information
Release 1.05
Updated register information
Release 1.00
Initial Release
Support
The EBX-38 support page contains additional information and resources for this product
including:
Reference Manual (PDF format)
Operating system information and software drivers
Data sheets and manufacturers’ links for chips used in this product
BIOS information and upgrades
Utility routines and benchmark software
This is a private page for EBX-38 users that can be accessed only be entering this address
directly. It cannot be reached from the VersaLogic homepage.
The VersaTech KnowledgeBase is an invaluable resource for resolving technical issues with
your VersaLogic product.
VersaTech KnowledgeBase

iv VL-EBX-38 Programmer’s Reference Manual
Contents
Introduction ...................................................................................................................1
Related Documents.............................................................................................................1
System Resources and Maps.......................................................................................2
Memory Map ......................................................................................................................2
Interrupts.............................................................................................................................2
FPGA Registers.............................................................................................................4
FPGA I/O Space .................................................................................................................4
ISA Bus Addressing and LPC I/O and Memory Map ...........................................4
FPGA Register Descriptions...............................................................................................6
Product Information Registers..........................................................................................11
BIOS and Jumper Status Register........................................................................12
Timer Registers....................................................................................................13
SPI Control Registers ..........................................................................................16
SPI Data Registers...............................................................................................18
SPI Debug Control Register and mSATA/PCIe Select Control Register............19
ADM – A/D and D/A SPI Device Control Register............................................20
Miscellaneous FPGA Registers...........................................................................21
DIOCR – Digital I/O Control Register................................................................25
8254 Timer Address 0/1/2/3 Registers................................................................36
Programming Information for Hardware Interfaces..................................................38
Processor WAKE# Capabilities........................................................................................38
Watchdog Timer............................................................................................................... 38
Industrial I/O Functions and SPI Interface.......................................................................39
Programmable LED..........................................................................................................39
Tables
Table 1: Memory Map ........................................................................................................ 2
Table 2: I/O Map................................................................................................................. 3
Table 3: FPGA I/O Map...................................................................................................... 4
Table 4: ISA Bus I/O Map.................................................................................................. 5
Table 5: ISA Memory Map................................................................................................. 5
Table 6: PCR – Product Code and LED Register............................................................. 11
Table 7: PSR – Product Status Register............................................................................ 11
Table 8: SCR –Status/Control Register ............................................................................ 12
Table 9: TICR – 8254 Timer Interrupt Mask Register ..................................................... 13
Table 10: TISR – 8254 Timer Interrupt Status Register................................................... 14
Table 11: TCR – 8254 Timer Control Register ................................................................ 15

Contents
VL-EBX-38 Programmer’s Reference Manual v
Table 12: SPI Interface Control Register.......................................................................... 16
Table 13: SPI Interface Status Register ............................................................................ 17
Table 14: SPI – SPI Debug Control Register.................................................................... 19
Table 15: MISCR1 – Misc. Control Register #1 .............................................................. 21
Table 16: MISCSR2 – Misc. Control Register #2............................................................ 22
Table 17: MISCR3 – Misc. Control Register #3 .............................................................. 23
Table 18: DIOIMASK1 – Digital I/O 8-1 Interrupt Mask Register.................................. 24
Table 19: DIOISTAT1 – Digital I/O 8-1 Interrupt Status Register .................................. 24
Table 20: DIOCR – Digital I/O Control Register............................................................. 25
Table 21: AUXDIR – AUX GPIO Direction Control Register ........................................ 26
Table 22: AUXPOL – AUX GPIO Polarity Control Register.......................................... 26
Table 23: AUXOUT – AUX GPIO Output Control Register........................................... 26
Table 24: AUXIN – AUX GPIO Input Status Register .................................................... 27
Table 25: AUXICR – AUX GPIO Interrupt Mask Register............................................. 27
Table 26: AUXISTAT – AUX GPIO Interrupt Status Register........................................ 27
Table 27: AUXMODE1 – AUX I/O Mode Register ........................................................ 28
Table 28: WDT_CTL – Watchdog Control Register........................................................ 29
Table 29: WDT_VAL – Watchdog Control Register....................................................... 30
Table 30: XCVRMODE – COM Transceiver Mode Register.......................................... 30
Table 31: AUXMODE2 - AUX I/O Mode Register #2.................................................... 31
Table 32: FANCON – Fan Control Register .................................................................... 31
Table 33: FANTACHLS – FANTACH Status Register Least Significant Bits ............... 32
Table 34: FANTACHMS – FANTACH Status Register Most Significant Bits............... 32
Table 35: TEMPICR – Temperature Interrupt Control Register...................................... 33
Table 36: TEMPISTAT – Temperature Interrupt Status Register.................................... 34
Table 37: ISACON1 – ISA Control Register #1............................................................... 35
Table 38: ISACON2 – ISA Control Register #2............................................................... 36
Table 37: UARTxCR – UART Control Registers............................................................ 37

1 VL-EBX-38 Programmer’s Reference Manual
Introduction
This document provides information for users requiring register-level information for developing
applications with the VL-EBX-38.
Related Documents
The following documents available are on the EBX-38 Product Support Web Page:
EBX-38 Hardware Reference Manual – provides information on the board’s hardware
features including connectors and all interfaces.
This document is available through the software page:
VersaAPI Installation and Reference Guide – describes the shared library of API calls for
reading and controlling on-board devices on certain VersaLogic products.
1

VL-EBX-38 Programmer’s Reference Manual 2
System Resources and Maps
Memory Map
Table 1: Memory Map
Address Range Description
00000h – 9FFFFh
Legacy system (DOS) area
A0000h – B7FFFh
ISA memory area (VGA frame buffer is not accessible)
B8000h – BFFFFh
Text mode buffer
C0000h – CFFFFh
Video BIOS area
D0000h – DFFFFh
PCI ROM expansion area
E0000h – FFFFFh
Legacy BIOS (reserved)
Interrupts
The LPC SERIRQ is used for interrupt interface to the Bay Trail SoC.
Each of the following devices can have an IRQ interrupt assigned to it and each with an interrupt
enable control for IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, IRQ9, IRQ10, and IRQ11:
8254 timers (with three interrupt status bits)
32 SPI based digital I/Os (with one interrupt status bit)
8 AUX GPIOs (with one interrupt status bit)
COM 1 UART (with 16550 interrupt status bits) from the SCH3114
COM 2 UART (with 16550 interrupt status bits) from the SCH3114
COM 3 UART (with 16550 interrupt status bits) from the SCH3114
COM 4 UART (with 16550 interrupt status bits) from the SCH3114
Watchdog timer (one status bit)
SPX expansion interface (status is determined by the devices on this interface). This uses
selects from four of the “usual” IRQs.
Thermal event and battery-low interrupts
ISA interrupts
The ISA bus supports 11 interrupts: IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, IRQ9, IRQ10, IRQ11,
IRQ12, IRQ14, and IRQ15. There is an interrupt enable control for each and by default they are
all disabled. ISA bus interrupts simply pass through to the SERIRQ (no capture in the FPGA).
Common interrupts can be assigned to multiple devices if software can deal with it (this is
common on UARTs being handled by a common ISR).
Interrupt status bits for everything except the UARTs will “stick” and are cleared by a “write-
one” to a status register bit. The 16550 UART interrupts behave as defined for the 16550
registers and are a pass-through to the LPC SERIRQ via the SCH3114.
2

System Resources and Maps
3 VL-EBX-38 Programmer’s Reference Manual
Per the VersaAPI standard, anytime an interrupt on the SERIRQ is enabled, the slot becomes
active. All interrupts in the SERIRQ are high-true so when the slot becomes active, the slot will
be low when there is no interrupt and high when there is an interrupt.
Table 2: I/O Map
I/O Address Range Device/Owner
2E8h – 2EFh
COM4 serial port default
2F8h – 2FFh
COM2 serial port default
3B0h – 3DFh
Legacy VGA registers
3E8h – 3EFh
COM3 serial port default
3F8h – 3FFh
COM1 serial port default
400h – 47Fh
ACPI / Power management (reserved)
500h – 5FFh
PCH GPIO (reserved)
C80h – CBBh
EBX-38 FPGA Board Control Registers
CBCh – CBFh
EBX-38 FPGA 8254 Timer Registers
CC0h – CCFh
EBX-38 FPGA Additional Registers

FPGA Registers
VL-EBX-38 Programmer’s Reference Manual 4
FPGA Registers
FPGA I/O Space
The FPGA will be mapped into I/O space on the LPC bus. The only other devices on the LPC
bus are the SCH3114 Super I/O and the TPM, but the TPM is a Memory mapped device which is
not allowed to use I/O space anymore (see the main TPM section).
FPGA Access: LPC I/O Space
FPGA Access Size: All 8-bit Byte accesses (16-bit like registers are aligned on 16-bit word
boundaries to make word access possible in software but the LPC bus still splits the accesses
into two 8-bit accesses)
FPGA Address Range: 0xC80 to 0xCCF (80 byte window)
The three 8254 timers only require 4 bytes of addressing and will be put at the end of the first 64-
byte I/O block (staying consistent with other Bay Trail boards). The only requirement is that the
base address must be aligned on a 4-byte block. Some previous FPGAs had the timer base
address programmable but there is no need for that.
Table 3: FPGA I/O Map
Address Range Device Size
0xC80 – 0xCBB
FPGA registers
60 bytes
0xCBC – 0xCBF
8254 timer address registers
4 bytes
0xCC0 – 0xCCF
Additional Registers (for
SCH3114 UART support)
16 Bytes
ISA BUS ADDRESSING AND LPC I/O AND MEMORY MAP
The FPGA implements an LPC-to-ISA bridge. The LPC bus only has the FPGA, the SCH3114,
and the TPM device on it. The TPM is a memory mapped device at base address 0xFED40000.
The SCH3114 uses I/O addresses 0x2E/0x2F for its index/data port. It also uses I/O space
0xC00-0xC7F for Runtime Registers. The FPGA uses I/O space 0xC80-0xCCF. The ISA bus
addressing can go up to 16Mbytes (24-bits of address). As such, the following will be the
allowed memory and I/O map for the ISA bus. Basically, all LPC I/O cycles that are unclaimed
by the FPGA will pass through to the ISA bus.
All LPC memory cycles below 16Mbytes will be passed through to the ISA bus. Note that the
actual cycles on the LPC bus are not known.
3

FPGA Registers
5 VL-EBX-38 Programmer’s Reference Manual
Table 4: ISA Bus I/O Map
Address Range Device Size
0x2E-0x2F
SCH3114
Index/Data Port
0xC00-0xC7F
SCH3114
Runtime Registers
0xC80-0xCCF
FPGA Registers
80 Bytes
All Other LPC I/O Cycles ISA Bus
Depends on SoC LPC I/O traffic and
whether COM ports are enabled.
Table 5: ISA Memory Map
Address Range Device Size
0x0 – 0xFFFFFF LPC memory cycles
ISA bus
Depends on SoC LPC memory traffic
0x1000000 and higher LPC memory
cycles
Ignored by FPGA
TPM is the only memory device on the
LPC bus

FPGA Registers
6VL-EBX-38 Programmer’s Reference Manual
FPGA Register Descriptions
Register Access Key
R/W Read/Write
RO Read-only (status or reserved)
R/WC Read-status/Write-1-to-Clear
WO
Write-Only
ROC
Read-Only and clear-to-0 after reading
RSVD Reserved. Only write 0 to this bit; ignore all read values.
Reset Key
POR Power-on reset (only resets one time when input power comes on)
Platform Resets prior to the processor entering the S0 power state (i.e., at power-on and in sleep states)
resetSX
If AUX_PSEN is a '0' in MISCSR1 (default setting) then this is the same as the Platform reset. If AUX_PSEN is a
programmed to a '1' then it is the same as the power-on reset POR.
n/a Reset doesn't apply to status or reserved registers

FPGA Registers
VL-EBX-38 Programmer’s Reference Manual 7
Identifier
I/O
Address
Offset
Reset
D7
D6
D5
D4
D3
D2
D1
D0
PCR
C80
0
Platform
PLED
PRODUCT_CODE
PSR
C81
1
n/a
REV_LEVEL
EXTEMP
CUSTOM
BETA
SCR
C82
2
Platform
BIOS_JMP
BIOS_OR
BIOS_SEL
LED_DEBUG
WORKVER
0
GPI_JMP
0
TIMR
C83
3
Platform
IRQEN
IRQSEL2
IRQSEL1
IRQSEL0
0
IMASK_TC5
IMASK_TC4
IMASK_TC3
TISR
C84
4
Platform
INTRTEST
TMRTEST
TMRIN4
TMRIN3
0
ISTAT_TC5
ISTAT_TC4
ISTAT_TC3
TCR
C85
5
Platform
TIM5GATE
TIM4GATE
TIM3GATE
TM45MODE
TM4CLKSEL
TM3CLKSEL
TMROCTST
TMRFULL
Reserved
C86
6
n/a
0
0
0
0
0
0
0
0
Reserved
C87
7
n/a
0
0
0
0
0
0
0
0
SPICONTROL
C88
8
Platform
CPOL
CPHA
SPILEN1
SPILEN0
MAN_SS
SS2
SS1
SS0
SPISTATUS
C89
9
Platform
IRQSEL1
IRQSEL0
SPICLK1
SPICLK0
HW_IRQ_EN
LSBIT_1ST
HW_INT
BUSY
SPIDATA0
C8A
A
Platform
msb
<============>
lsb
SPIDATA1
C8B
B
Platform
msb
<============>
lsb
SPIDATA2
C8C
C
Platform
msb
<============>
lsb
SPIDATA3
C8D
D
Platform
msb
<============>
lsb
SPIMISC
C8E
E
Platform
0
MUXSEL2
MUXSEL1
MUXSEL0
0
SERIRQEN
SPILB
0
ADM
C8F
F
Platform
0
0
0
DACLDA0
0
ADCBUSY0
0
ADCONVST0
MISCSR1
C90
10
POR
0
0
0
0
0
MINI1_PSDIS
AUX_PSEN
MINI0_PSDIS
MISCSR2
C91
11
POR
USB_HUBMODE
W_DISABLE
ETH1_OFF
ETH0_OFF
0
USB_HUBDIS
USB_PBDIS
USB_OBDIS
MISCSR3
C92
12
Platform
0
0
0
0
USB_PBOC
PBRESET
USB_PB_SMBEN
USB_OB_SMBEN
Reserved
C93
13
n/a
0
0
0
0
0
0
0
0
Reserved
C94
14
n/a
0
0
0
0
0
0
0
0
Reserved
C95
15
n/a
0
0
0
0
0
0
0
0
Reserved
C96
16
n/a
0
0
0
0
0
0
0
0

FPGA Registers
8VL-EBX-38 Programmer’s Reference Manual
Identifier
I/O
Address
Offset
Reset
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
C97
17
n/a
0
0
0
0
0
0
0
0
Reserved
C98
18
n/a
0
0
0
0
0
0
0
0
Reserved
C99
19
n/a
0
0
0
0
0
0
0
0
Reserved
C9A
1A
n/a
0
0
0
0
0
0
0
0
Reserved
C9B
1B
n/a
0
0
0
0
0
0
0
0
DIOIMASK1
C9C
1C
Platform
0
0
0
0
0
0
0
IMASK_DIO1
DIOIMASK2
C9D
1D
n/a
0
0
0
0
0
0
0
0
DIOISTAT1
C9E
1E
Platform
0
0
0
0
0
0
0
ISTAT_DIO1
DIOISTAT2
C9F
1F
n/a
0
0
0
0
0
0
0
0
DIOCR
CA0
20
Platform
IRQEN
IRQSEL2
IRQSEL1
IRQSEL0
0
0
0
0
AUXDIR
CA1
21
resetSX
DIR_GPIO8
DIR_GPIO7
DIR_GPIO6
DIR_GPIO5
DIR_GPIO4
DIR_GPIO3
DIR_GPIO2
DIR_GPIO1
AUXPOL
CA2
22
resetSX
POL_GPIO8
POL_GPIO7
POL_GPIO6
POL_GPIO5
POL_GPIO4
POL_GPIO3
POL_GPIO2
POL_GPIO1
AUXOUT
CA3
23
resetSX
OUT_GPIO8
OUT_GPIO7
OUT_GPIO6
OUT_GPIO5
OUT_GPIO4
OUT_GPIO3
OUT_GPIO2
OUT_GPIO1
AUXIN
CA4
24
n/a
IN_GPIO8
IN_GPIO7
IN_GPIO6
IN_GPIO5
IN_GPIO4
IN_GPIO3
IN_GPIO2
IN_GPIO1
AUXIMASK
CA5
25
Platform
IMASK_GPIO8
IMASK_GPIO7
IMASK_GPIO6
IMASK_GPIO5
IMASK_GPIO4
IMASK_GPIO3
IMASK_GPIO2
IMASK_GPIO1
AUXISTAT
CA6
26
Platform
ISTAT_GPIO8
ISTAT_GPIO7
ISTAT_GPIO6
ISTAT_GPIO5
ISTAT_GPIO4
ISTAT_GPIO3
ISTAT_GPIO2
ISTAT_GPIO1
AUXMODE1
CA7
27
resetSX
MODE_GPIO8
MODE_GPIO7
MODE_GPIO6
MODE_GPIO5
MODE_GPIO4
MODE_GPIO3
MODE_GPIO2
MODE_GPIO1
WDT_CTL
CA8
28
Platform
IRQEN
IRQSEL2
IRQSEL1
IRQSEL0
0
RESET_EN
WDT_EN
WDT_STAT
WDT_VAL
CA9
29
Platform
msb
<============>
lsb
XCVRMODE
CAA
2A
Platform
0
0
0
0
COM4_MODE
COM3_MODE
COM2_MODE
COM1_MODE
AUXMODE2
CAB
2B
Platform
IRQEN
IRQSEL2
IRQSEL1
IRQSEL0
0
0
0
0
FANCON
CAC
2C
Platform
0
0
0
0
0
0
0
FAN_OFF
Reserved
CAD
2D
n/a
0
0
0
0
0
0
0
0
FANTACHLS
CAE
2E
Platform
msb
<============>
lsb

FPGA Registers
9 VL-EBX-38 Programmer’s Reference Manual
Identifier
I/O
Address
Offset
Reset
D7
D6
D5
D4
D3
D2
D1
D0
FANTACHMS
CAF
2F
Platform
msb
<============>
lsb
TEMPICR
CB0
30
Platform
IRQEN
IRQSEL2
IRQSEL1
IRQSEL0
IMASK_BATTLO
W
IMASK_EVENT
IMASK_THERM
IMASK_ALERT
TEMPISTAT
CB1
31
Platform
BATTLOW
0
0
0
ISTAT_BATTLOW
ISTAT_EVENT
ISTAT_THERM
ISTAT_ALERT
Reserved
CB2
32
n/a
0
0
0
0
0
0
0
0
Reserved
CB3
33
n/a
0
0
0
0
0
0
0
0
Reserved
CB4
34
n/a
0
0
0
0
0
0
0
0
Reserved
CB5
35
n/a
0
0
0
0
0
0
0
0
UARTMODE1
CB6
36
n/a
0
0
0
0
0
0
0
0
UARTMODE2
CB7
37
n/a
0
0
0
0
0
0
0
0
ISACON1
CB8
38
Platform
ISA_IRQ11
ISA_IRQ10
ISA_IRQ9
ISA_IRQ7
ISA_IRQ6
ISA_IRQ5
ISA_IRQ4
ISA_IRQ3
ISACON2
CB9
39
Platform
ISA_ACCESS
0
0
ISA_16MODE
0
ISA_IRQ15
ISA_IRQ14
ISA_IRQ12
Reserved
CBA
3A
n/a
0
0
0
0
0
0
0
0
Reserved
CBB
3B
n/a
0
0
0
0
0
0
0
0
8254 Timers
Address 0
CBC
3C
Platform
msb
<============>
lsb
8254 Timers
Address 1
CBD
3D
Platform
msb
<============>
lsb
8254 Timers
Address 2
CBE
3E
Platform
msb
<============>
lsb
8254 Timers
Address 3
CBF
3F
Platform
msb
<============>
lsb
Reserved
CC0
40
n/a
0
0
0
0
0
0
0
0
Reserved
CC1
41
n/a
0
0
0
0
0
0
0
0
Reserved
CC2
42
n/a
0
0
0
0
0
0
0
0
Reserved
CC3
43
n/a
0
0
0
0
0
0
0
0
UART1CR
CC4
44
Platform
UART1_EN
0
0
0
UART1_BASE3
UART1_BASE2
UART1_BASE1
UART1_BASE0
UART2CR
CC5
45
Platform
UART2_EN
0
0
0
UART2_BASE3
UART2_BASE2
UART2_BASE1
UART2_BASE0

FPGA Registers
10 VL-EBX-38 Programmer’s Reference Manual
Identifier
I/O
Address
Offset
Reset
D7
D6
D5
D4
D3
D2
D1
D0
UART3CR
CC6
46
Platform
UART3_EN
0
0
0
UART3_BASE3
UART3_BASE2
UART3_BASE1
UART3_BASE0
UART4CR
CC7
47
Platform
UART4_EN
0
0
0
UART4_BASE3
UART4_BASE2
UART4_BASE1
UART4_BASE0
Reserved
CC8
48
n/a
0
0
0
0
0
0
0
0
Reserved
CC9
49
n/a
0
0
0
0
0
0
0
0
Reserved
CCA
4A
n/a
0
0
0
0
0
0
0
0
Reserved
CCB
4B
n/a
0
0
0
0
0
0
0
0
Reserved
CCC
4C
n/a
0
0
0
0
0
0
0
0
Reserved
CCD
4D
n/a
0
0
0
0
0
0
0
0
Reserved
CCE
4E
n/a
0
0
0
0
0
0
0
0
Reserved
CCF
4F
n/a
0
0
0
0
0
0
0
0
Passed to ISA Bus
CD0-FFFF
--
--
Unknown

FPGA Registers
VL-EBX-38 Programmer’s Reference Manual 11
Product Information Registers
This register drives the PLED on the paddleboard. It also provides read access to the product
code.
Table 6: PCR – Product Code and LED Register
Bit Identifier Access Default Description
7 PLED R/W 0 Drives the programmable LED on the paddleboard. 0 – LED is off (default)
1 – LED is on (can be used by software)
6-0
PRODUCT_CODE
RO
“0010111”
Product Code for the EBX-38 (0x17)
Table 7: PSR – Product Status Register
Bit Identifier Access Default Description
7:3 REV_LEVEL[4:0] RO N/A
Revision level of the PLD (incremented every FPGA release)
0 – Indicates production release revision level when BETA
status bit (bit 0) is set to ‘0’
1 – Indicates development release revision level when BETA
status bit (bit 0) is set to ‘1’
2 EXTEMP RO N/A Extended or Standard Temp Status (set via external resistor): 0 – Standard Temp
1 – Extended Temp
1 CUSTOM RO N/A Custom or Standard Product Status (set in FPGA): 0 – Standard Product
1 – Custom Product or PLD/FPGA
0 BETA RO N/A Beta or Production Status (set in FPGA): 1 – Beta (or Debug)
0 – Production

FPGA Registers
12 VL-EBX-38 Programmer’s Reference Manual
BIOS AND JUMPER STATUS REGISTER
Table 8: SCR –Status/Control Register
Bit Identifier Access Default Description
7 BIOS_JMP RO N/A Status of the external BIOS switch (jumper): 1 – Primary BIOS selected
0 – Secondary BIOS selected
6 BIOS_OR R/W 0 BIOS Switch (jumper) Override 0 – BIOS Select will follow the BIOS_JMP switch setting. (Note)
1 – BIOS Select will follow the BIOS_SEL register setting
5 BIOS_SEL R/W 0 BIOS Select (see BIOS_OR): 1 – Primary BIOS selected
0 – Backup BIOS selected
4 LED_DEBUG R/W 0 Debug LED (controls the yellow LED): 0 – LED is off and follows its primary function (MSATA_DAS)
1 – LED is on (indicates FPGA is programmed by default)
3 WORKVER RO N/A
Status used to indicate that the FPGA is not officially released
and is still in a working state.
0 – FPGA is released
1 – FPGA is in a working state (not released)
2 RESERVED RO N/A Reserved. Writes are ignored; reads always return 0.
1
GPI_JMP
RO
N/A Status of the GPI Jumper (switch):
0 – Switch is Off
1 – Switch is On
FYI – this is a traditional “jumper” that goes to the FPGA. It may
or may not be connected to a switch on the board.
0
RESERVED RO
0
Reserved. Writes are ignored; reads always return 0.
Note: This corresponds to the setting of position 6 of the SW1 Configuration Switch block. Refer to the EBX-38
Hardware Reference Manual for more information regarding the configuration switches.

FPGA Registers
VL-EBX-38 Programmer’s Reference Manual 13
TIMER REGISTERS
The FPGA implements an 8254-compatible timer/counter that includes three 16-bit timers.
Table 9: TICR – 8254 Timer Interrupt Mask Register
Bit Identifier Access Default Description
7 IRQEN R/W 0 8254 Timer interrupt enable/disable: 0 – Interrupts disabled
1 – Interrupts enabled
6-4 IRQSEL(2:0) R/W 000
8254 Timer interrupt IRQ select in LPC SERIRQ:
000 – IRQ3
001 – IRQ4
010 – IRQ5
011 – IRQ10
100 – IRQ6
101 – IRQ7
110 – IRQ9
111 – IRQ11
3 RESERVED RO 0 Reserved. Writes are ignored; reads always return 0.
2 IMSK_TC5 R/W 0 8254 timer #5 interrupt mask: 0 – Interrupt disabled
1 – Interrupt enabled
1 IMSK_TC4 R/W 0 8254 timer #4 interrupt mask: 0 – Interrupt disabled
1 – Interrupt enabled
0 IMSK_TC3 R/W 0 8254 timer #3 interrupt mask: 0 – Interrupt disabled
1 – Interrupt enabled

FPGA Registers
14 VL-EBX-38 Programmer’s Reference Manual
Table 10: TISR – 8254 Timer Interrupt Status Register
Bit Identifier Access Default Description
7 INTRTEST R/W 0
Debug/Test Only -- 8254 Timer Interrupt Test (test mode only):
0 – No test interrupt:Must be set to 0 for normal operation.
1 – If IRQEN is a 1 then an interrupt will assert in the selected
IRQ in the LPC SERIRQ stream (no timer interrupt mask needs
to be set for this)
6 TMRTEST R/W 0
Debug/Test Only -- 8254 Timer Test Mode:
0 – Normal operation:Must be set to 0 for normal operation.
1 – Timer test mode. In test mode the OCTC3, OCTC4 (and
OCTC5 if ever implemented) outputs are set to Hi-Z and the
ICTC3, ICTC4 timer inputs are ignored. This is basically the
internal timer test mode not requiring external signals.
5 TMRIN4 R/W 0
Debug/Test Only -- 8254 Timer #4 test signal. When TMRTEST
= 1 this signal is used for the timer input control instead of the
external ICTC4 signal. When INTRTEST = 0 this is ignored.
0 – deasserted
1 – asserted
4 TMRIN3 R/W 0
Debug/Test Only -- 8254 Timer #3 test signal. When TMRTEST
= 1 this signal is used for the timer input control instead of the
external ICTC3 signal. When INTRTEST = 0 this is ignored.
0 – deasserted
1 – asserted
3
RESERVED
RO
0
Reserved. Writes are ignored; reads always return 0.
2 ISTAT_TC5 RW/C N/A
Status for the 8254 Timer #5 output (terminal count) interrupt
when read. This bit is read-status and a write-1-to-clear.
0 – Timer output (terminal count) has not transitioned from 0 to
a 1 level
1 – Timer output (terminal count) has transitioned from a 0 to a
1 level
1 ISTAT_TC4 RW/C N/A
Status for the 8254 Timer #4 output (terminal count) interrupt
when read. This bit is read-status and a write-1-to-clear.
0 – Timer output (terminal count) has not transitioned from 0 to
a 1 level
1 – Timer output (terminal count) has transitioned from a 0 to a
1 level
0 ISTAT_TC3 RW/C N/A
Status for the 8254 Timer #3 output (terminal count) interrupt
when read. This bit is read-status and a write-1-to-clear.
0 – Timer output (terminal count) has not transitioned from 0 to
a 1 level
1 – Timer output (terminal count) has transitioned from a 0 to a
1 level

FPGA Registers
VL-EBX-38 Programmer’s Reference Manual 15
Table 11: TCR – 8254 Timer Control Register
Bit Identifier Access Default Description
7 TMR5GATE R/W 0
Debug/Test Only: Controls the “gate” signal on 8254 timer #5 when not
using an external gate signal:
0 – Gate on signal GCTC5 is disabled
1 – Gate on signal GCTC5 is enabled
Always set to 0 when configuring timer modes except when TMRFULL
is ‘0’ and then it should be set to ‘1’ and not changed unless using
internal clocking.
6 TMR4GATE R/W 0
Controls the “gate” signal on 8254 timer #4 when not using an external
gate signal:
0 – Gate on signal GCTC4 is disabled
1 – Gate on signal GCTC4 is enabled
Always set to 0 when configuring timer modes except when TMRFULL
is ‘0’ and then it should be set to ‘1’ and not changed unless using
internal clocking
5 TMR3GATE R/W 0
Controls the “gate” signal on 8254 timer #3 when not using an external
gate signal:
0 – Gate on signal GCTC3 is disabled
1 – Gate on signal GCTC3 is enabled
Always set to 0 when configuring timer modes except when TMRFULL
is ‘0’ and then it should be set to ‘1’ and not changed unless using
internal clocking
4 TM45MODE R/W 0
Mode to set timers #4 and #5 in:
0 – Timer #4 and #5 form one 32-bit timer controlled by timer #1 signals
1 – Timer #4 and Timer #5 are separate 16-bit timers with their own
control signals.
Almost always used in 32-bit mode especially when TMRFULL is a ‘0’
(the 16-bit timer #5 is of limited use)
3 TM4CLKSEL R/W 0
Timer #4 Clock Select:
0 – Use internal 4.125 MHz clock (derived from PCI clock)
1 – Use external ICTC4
Timer #5 is always on internal clock if configured as a 16-bit clock
2 TM3CLKSEL R/W 0 Timer #3 Clock Select:
0 – Use internal 4.125 MHz clock (derived from PCI clock)
1 – Use external ICTC3 assigned to Digital I/O
1 TMROCTST R/W 0 Debug/Test Only: Used to derive OCTCx outputs with TMRxGATE
signals for continuity testing only: Must be set to 0 for normal
operation.
0 TMRFULL R/W 0
GPIOs to use for Timer signals (MODE_GPIO[8:3] must each be a ‘1’
in AUXMODE1 Register to use all the external timer signals).:
0 – 4-wire timers (GPIO4 and GPIO3 external gate signals not used)
are external Timer control signals
1 – 8-wire timers; six GPIOs (GPIO8 – GPIO3) are external Timer
control signals
Note: Since the gates-controls are not connected to GPIOs when
TMRFULL is a ‘0’ the TMRxGATE gate controls in this register are used
so they need to be set to ‘1’ and should not be toggled during operation
with external timers (since there is no continuous clock to synchronize
them to) but can be toggled if using the internal clock. If you need
gating in external modes then you really need to set TMRFULL to a ‘1’.