VersaLogic SandCat User manual

Programmer’s
Reference
Manual
REV. November 2018
SandCat
(VL-EPM-39)
Intel®Atom™-based Single
Board Computer with Ethernet,
Video, USB, SATA, Serial I/O,
Digital I/O, Counter/Timers, Mini
PCIe, mSATA and
PCI/104-Plus Interface.

EPM-39 Programmer’s Reference Manual ii
WWW.VERSALOGIC.COM
12100 SW Tualatin Road
Tualatin, OR 97062-7341
[phone]
Fax [phone]
Copyright © 2018 VersaLogic Corp. All rights reserved.
Notice:
Although every effort has been made to ensure this document is error-free, VersaLogic makes no
representations or warranties with respect to this product and specifically disclaims any implied warranties
of merchantability or fitness for any particular purpose.
VersaLogic reserves the right to revise this product and associated documentation at any time without
obligation to notify anyone of such changes.
PC/104, PC/104-Plus, and the PC/104 logo are trademarks of the PC/104 Consortium.

EPM-39 Programmer’s Reference Manual iii
Product Release Notes
Release 1
First release of this document.
Support
The EPM-39 support page contains additional information and resources for this product
including:
Reference Manual (PDF format)
Operating system information and software drivers
Data sheets and manufacturers’ links for chips used in this product
BIOS information and upgrades
Utility routines and benchmark software
The VersaTech KnowledgeBase is an invaluable resource for resolving technical issues with
your VersaLogic product.
VersaTech KnowledgeBase

EPM-39 Programmer’s Reference Manual iv
Contents
Introduction ...................................................................................................................1
Related Documents.............................................................................................................1
System Resources and Maps.......................................................................................2
Memory Map ......................................................................................................................2
Interrupts.............................................................................................................................2
FPGA Registers.............................................................................................................4
FPGA I/O Space .................................................................................................................4
ISA Bus Addressing and LPC I/O and Memory Map ...........................................4
FPGA Register Map ...........................................................................................................5
FPGA Register Descriptions...............................................................................................8
Product Information Registers...............................................................................8
BIOS and Jumper Status Register.......................................................................... 9
Timer Registers....................................................................................................10
Miscellaneous FPGA Registers...........................................................................13
Programming Information for Hardware Interfaces..................................................28
Processor WAKE# Capabilities........................................................................................28
Watchdog Timer...............................................................................................................28
Programmable LED.......................................................................................................... 28
Tables
Table 1: Memory Map ........................................................................................................ 2
Table 2: I/O Map................................................................................................................. 3
Table 3: FPGA I/O Map...................................................................................................... 4
Table 4: ISA Bus I/O Map.................................................................................................. 4
Table 5: ISA Memory Map................................................................................................. 4
Table 6: PCR – Product Code and LED Register............................................................... 8
Table 7: PSR – Product Status Register.............................................................................. 8
Table 8: SCR –Status/Control Register .............................................................................. 9
Table 9: TICR – 8254 Timer Interrupt Control Register.................................................. 10
Table 10: TISR – 8254 Timer Interrupt Status Register................................................... 11
Table 11: TCR – 8254 Timer Control Register................................................................ 12
Table 12: MISCR1 – Misc. Control Register #1 .............................................................. 13
Table 13: MISCSR2 – Misc. Control Register #2............................................................ 14
Table 14: MISCR3 – Misc. Control Register #3 .............................................................. 15
Table 15: AUXDIR – AUX GPIO Direction Control Register ........................................ 16
Table 16: AUXPOL – AUX GPIO Polarity Control Register.......................................... 16

Contents
EPM-39 Programmer’s Reference Manual v
Table 17: AUXOUT – AUX GPIO Output Control Register........................................... 16
Table 18: AUXIN – AUX GPIO Input Status Register .................................................... 17
Table 19: AUXICR – AUX GPIO Interrupt Mask Register............................................. 17
Table 20: AUXISTAT – AUX GPIO Interrupt Status Register........................................ 17
Table 21: AUXMODE1 – AUX I/O Mode Register ........................................................ 18
Table 22: WDT_CTL – Watchdog Control Register........................................................ 19
Table 23: WDT_VAL – Watchdog Value Register.......................................................... 20
Table 24: XCVRMODE – COM Transceiver Mode Register.......................................... 20
Table 25: AUXMODE2 - AUX I/O Mode Register #2.................................................... 21
Table 29: TEMPICR – Temperature Interrupt Control Register ...................................... 22
Table 30: TEMPISTAT – Temperature Interrupt Status Register.................................... 22
Table 31: UART1CR – UART1 Control Register (COM1)............................................. 23
Table 32: UARTMODE1 – UART MODE Register #1................................................... 24
Table 33: UARTMODE2 – UART MODE Register #2................................................... 26
Table 34: ISACON1 – ISA Control Register #1............................................................... 27
Table 35: ISACON2 – ISA Control Register #2............................................................... 27

EPM-39 Programmer’s Reference Manual 1
Introduction
This document provides information for users requiring register-level information for developing
applications with the VL-EPM-39.
Related Documents
The following documents available are on the EPM-39 Product Support Web Page:
EPM-39 Hardware Reference Manual – provides information on the board’s hardware
features including connectors and all interfaces.
1

EPM-39 Programmer’s Reference Manual 2
System Resources and Maps
Memory Map
Table 1: Memory Map
Address Range Description
00000h – 9FFFFh
Legacy system (DOS) area
A0000h – B7FFFh
ISA memory area (VGA frame buffer is not accessible)
B8000h – BFFFFh
Text mode buffer
C0000h – CFFFFh
Video BIOS area
D0000h – DFFFFh
PCI ROM expansion area
E0000h – FFFFFh
Legacy BIOS (reserved)
Interrupts
The LPC SERIRQ is used for interrupt interface to the BayTrail SoC.
Each of the following devices can have an IRQ interrupt assigned to it and each with an interrupt
enable control for IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, IRQ9, IRQ10, and IRQ11:
8254 timers (with three interrupt status bits)
8 AUX GPIOs (with one interrupt status bit)
COM 1 UART (with 16550 interrupt status bits)
Watchdog timer (one status bit)
Thermal event interrupts
ISA interrupts
The ISA bus supports 11 interrupts: IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, IRQ9, IRQ10, IRQ11,
IRQ12, IRQ14, and IRQ15. There is an interrupt enable control for each and by default they are
all disabled. ISA bus interrupts simply pass through to the SERIRQ (no capture in the FPGA).
Common interrupts can be assigned to multiple devices if software can deal with it (this is
common on UARTs being handled by a common ISR).
Interrupt status bits for everything except the UARTs will “stick” and are cleared by a “write-
one” to a status register bit. The 16550 UART interrupts behave as defined for the 16550
registers and are a pass-through to the LPC SERIRQ.
Per the VersaAPI standard, anytime an interrupt on the SERIRQ is enabled, the slot becomes
active. All interrupts in the SERIRQ are high-true so when the slot becomes active, the slot will
be low when there is no interrupt and high when there is an interrupt.
2

System Resources and Maps
EPM-39 Programmer’s Reference Manual 3
Table 2: I/O Map
I/O Address Range Device/Owner
3F8h – 3FFh
COM1 serial port default
400h – 47Fh
ACPI / Power management (reserved)
500h – 5FFh
PCH GPIO (reserved)
C80h – CBBh
EPM-39 FPGA Board Control Registers
CBCh – CBFh
EPM-39 FPGA 8254 Timer Registers

EPM-39 Programmer’s Reference Manual 4
FPGA Registers
FPGA I/O Space
The FPGA is mapped into I/O space on the LPC bus
FPGA access: LPC I/O space
FPGA access size: All 8-bit byte accesses (16-bit like registers are aligned on 16-bit word
boundaries to make word access possible in software but the LPC bus still splits the accesses
into two 8-bit accesses)
FPGA address range: 0xC80 to 0xCBF (64-byte window)
The three 8254 timers only require four bytes of addressing and are located at the end of the
64-byte I/O block. The only requirement is that the base address must be aligned on a 4-byte
block. The table below lists the FPGA’s I/O map.
Table 3: FPGA I/O Map
Address Range Device Size
0xC80 – 0xCBB
FPGA registers
60 bytes
0xCBC – 0xCBF
8254 timer address registers
4 bytes
ISA BUS ADDRESSING AND LPC I/O AND MEMORY MAP
The FPGA implements an LPC-to-ISA bridge. The LPC bus only has the he FPGA uses I/O
space 0xC80-0xCBF. The ISA bus memory address space is16 Mbytes (24-bits of address); ISA
busy I/O addressing is limited to 64 Kbytes (16 bits of address). As such, the following will be
the allowed memory and I/O map for the ISA bus.
All LPC I/O cycles that are unclaimed by the FPGA will pass through to the ISA bus. Similarly,
all LPC memory cycles below 16 Mbytes will be passed through to the ISA bus.
Table 4: ISA Bus I/O Map
Address Range Device Size
0xC80 - 0xCBF
FPGA registers
64 bytes
All other LPC I/O cycles
ISA bus
Depends on SoC LPC I/O traffic
Table 5: ISA Memory Map
Address Range Device Size
0x0 – 0xFFFFFF LPC memory cycles
ISA bus
Depends on SoC LPC memory traffic
0x1000000 and higher LPC memory
cycles
Ignored by FPGA
TPM is the only memory device on the
LPC bus
3

EPM-39 Programmer’s Reference Manual 5
FPGA Register Map
Register Access Key Reset Status Key
R/W Read/Write POR Power-on reset (only resets one time when input power comes on)
RO Read-only (status or reserved) Platform Resets prior to the processor entering the S0 power state (that is, at power-on
and in sleep states)
R/WC Read-status/Write-1-to-Clear resetSX
•If FPGA_PSEN is a '0' in MISCSR1 (default setting), then this is the
same as the Platform reset.
•If FPGA_PSEN is a programmed to a '1', then it is the same as the
Power-On Reset (POR).
RSVD Reserved. Only write 0 to this bit; ignore all read values. n/a Reset doesn't apply to status or reserved registers
Identifier
I/O
Address
Offset
Reset
Type
D7 D6 D5 D4 D3 D2 D1 D0
PCR C80 0 Platform PLED PRODUCT_CODE
PSR C81 1 n/a REV_LEVEL EXTEMP CUSTOM BETA
SCR C82 2 Platform LED_DEBUG WORKVER RSVD RSVD RSVD
TICR C83 3 Platform IRQEN IRQSEL2 IRQSEL1 IRQSEL0 RSVD IMASK_TC5 IMASK_TC4 IMASK_TC3
TISR C84 4 Platform RSVD RSVD RSVD RSVD RSVD ISTAT_TC5 ISTAT_TC4 ISTAT_TC3
TCR C85 5 Platform TIM5GATE TIM4GATE TIM3GATE TM45MODE TM4CLKSEL TM3CLKSEL RSVD TMRFULL
Reserved C86 6 n/a RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD
Reserved C87 7 n/a RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD
Reserved
C88 8 n/a RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD
Reserved
C89 9 n/a RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD
Reserved
C8A A n/a RSVD RSVD RSVD
Reserved
C8B B n/a RSVD RSVD RSVD
Reserved
C8C C n/a RSVD RSVD RSVD
Reserved C8D D n/a RSVD RSVD RSVD
Reserved
C8E E n/a RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD

FPGA Registers
EPM-39 Programmer’s Reference Manual 6
Identifier
I/O
Address
Offset
Reset
Type
D7 D6 D5 D4 D3 D2 D1 D0
Reserved C8F F n/a RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD
MISCSCR1 C90 10 POR RSVD RSVD RSVD RSVD RSVD RSVD FPGA_PSEN MINI_PSDIS
MISCSR2 C91 11 POR USB_HUBMODE W_DISABLE USB_USBID USB_HUBDIS USB_PBDIS USB_OBDIS
MISCSR3 C92 12 Platform RSVD RSVD RSVD RSVD USB_PBOC PBRESET RSVD RSVD
Reserved C93 13 n/a RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD
AUXDIR CA1 21 resetSX DIR_GPIO8 DIR_GPIO7 DIR_GPIO6 DIR_GPIO5 DIR_GPIO4 DIR_GPIO3 DIR_GPIO2 DIR_GPIO1
AUXPOL CA2 22 resetSX POL_GPIO8 POL_GPIO7 POL_GPIO6 POL_GPIO5 POL_GPIO4 POL_GPIO3 POL_GPIO2 POL_GPIO1
AUXOUT CA3 23 resetSX OUT_GPIO8 OUT_GPIO7 OUT_GPIO6 OUT_GPIO5 OUT_GPIO4 OUT_GPIO3 OUT_GPIO2 OUT_GPIO1
AUXIN CA4 24 n/a IN_GPIO8 IN_GPIO7 IN_GPIO6 IN_GPIO5 IN_GPIO4 IN_GPIO3 IN_GPIO2 IN_GPIO1
AUXIMASK CA5 25 Platform IMASK_GPIO8 IMASK_GPIO7 IMASK_GPIO6 IMASK_GPIO5 IMASK_GPIO4 IMASK_GPIO3 IMASK_GPIO2 IMASK_GPIO1
AUXISTAT CA6 26 Platform ISTAT_GPIO8 ISTAT_GPIO7 ISTAT_GPIO6 ISTAT_GPIO5 I STAT_GPIO4 ISTAT_GPIO3 ISTAT_GPIO2 ISTAT_GPIO1
AUXMODE1 CA7 27 resetSX MODE_GPIO8 MODE_GPIO7 MODE_GPIO6 MODE_GPIO5 MODE_GPIO4 MODE_GPIO3 MODE_GPIO2 MODE_GPIO1
WDT_CTL CA8 28 Platform IRQEN IRQSEL2 IRQSEL1 IRQSEL0 RSVD RESET_EN WDT_EN WDT_STAT
WDT_VAL CA9 29 Platform MSB <========================> LSB
XCVRMODE CAA 2A Platform RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
COM2_MODE COM1_MODE
AUXMODE2 CAB 2B Platform IRQEN IRQSEL2 IRQSEL1 IRQSEL0 RSVD RSVD RSVD RSVD
FANCON CAC 2C Platform RSVD RSVD RSVD RSVD RSVD RSVD RSVD FAN_OFF
Reserved CAD 2D n/a RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD
FANTACHLS CAE 2E Platform MSB <========================> LSB
FANTACHMS CAF 2F Platform MSB <========================> LSB
TEMPICR CB0 30 Platform IRQEN IRQSEL2 IRQSEL1 IRQSEL0 MASK_BATTLOW IMASK_EVENT IMASK_THERM IMASK_ALERT
TEMPISTAT CB1 31 Platform BATTLOW RSVD RSVD RSVD ISTAT_BATTLOW ISTAT_EVENT ISTAT_THERM ISTAT_ALERT
UART1CR CB2 32 Platform IRQEN IRQSEL2 IRQSEL1 IRQSEL0 UART1_BASE3 UART1_BASE2 UART1_BASE1 UART1_BASE0
UART2CR CB3 33 Platform IRQEN IRQSEL2 IRQSEL1 IRQSEL0 UART2_BASE3 UART2_BASE2 UART2_BASE1 UART2_BASE0
Reserved CB4 34 n/a RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD
Reserved CB5 35 n/a RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD
UARTMODE1 CB6 36 Platform RSVD RSVD UART2_485ADC UART1_485ADC RSVD RSVD UART2_EN UART1_EN

FPGA Registers
EPM-39 Programmer’s Reference Manual 7
Identifier
I/O
Address
Offset
Reset
Type
D7 D6 D5 D4 D3 D2 D1 D0
UARTMODE2 CB7 37 Platform RSVD RSVD RSVD RSVD RSVD RSVD RSVD FAST_MODE
ISACON1 CB8 38 Platform ISA_IRQ11 ISA_IRQ10 ISA_IRQ9 ISA_IRQ7 ISA_IRQ6 ISA_IRQ5 ISA_IRQ4 ISA_IRQ3
ISACON2 CB9 39 Platform RSVD RSVD RSVD RSVD RSVD ISA_IRQ15 ISA_IRQ14 ISA_IRQ12
Reserved CBA 3A n/a RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD
Reserved CBB 3B n/a RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD
8254_ADD0 CBC 3C Platform MSB <========================> LSB
8254_ADD1 CBD 3D Platform MSB <========================> LSB
8254_ADD2 CBE 3E Platform MSB <========================> LSB
8254_ADD3 CBF 3F Platform MSB <========================> LSB

EPM-39 Programmer’s Reference Manual 8
FPGA Register Descriptions
Register Access Key
R/W Read/Write
RO Read-only (status or reserved)
R/WC Read-status/Write-1-to-Clear
RSVD Reserved. Only write 0 to this bit; ignore all read values.
PRODUCT INFORMATION REGISTERS
This register drives the PLED on the paddleboard. It also provides read access to the product
code.
Table 6: PCR – Product Code and LED Register
Bit Identifier Access Default Description
7 PLED R/W 0 Drives the programmable LED on the paddleboard. 0 – LED is off (default)
1 – LED is on (can be used by software)
6-0
PRODUCT_CODE
RO
0010001
Product Code for the EPM-39 (0x11)
Table 7: PSR – Product Status Register
Bit Identifier Access Default Description
7:3 REV_LEVEL[4:0] RO N/A
Revision level of the PLD (incremented every FPGA release)
0 – Indicates production release revision level when BETA
status bit (bit 0) is set to ‘0’
1 – Indicates development release revision level when BETA
status bit (bit 0) is set to ‘1’
2 EXTEMP RO N/A Extended or Standard Temp Status (set via external resistor): 0 – Standard Temp
1 – Extended Temp (probably always set)
1 CUSTOM RO N/A Custom or Standard Product Status (set in FPGA): 0 – Standard Product
1 – Custom Product or PLD/FPGA
0 BETA RO N/A Beta or Production Status (set in FPGA): 1 – Beta (or Debug)
0 – Production

FPGA Registers
EPM-39 Programmer’s Reference Manual 9
BIOS AND JUMPER STATUS REGISTER
Table 8: SCR –Status/Control Register
Bit Identifier Access Default Description
7
RESERVED
6
RESERVED
5
RESERVED
4 LED_DEBUG R/W 0 Debug LED (controls the yellow LED): 0 – LED is off and follows its primary function (MSATA_DAS)
1 – LED is on (indicates FPGA is programmed by default)
3 WORKVER RO N/A
Status used to indicate that the FPGA is not officially released
and is still in a working state.
0 – FPGA is released
1 – FPGA is in a working state (not released)
2 RESERVED RO N/A Reserved. Writes are ignored; reads always return 0.
1
RESERVED RO
N/A
Reserved. Writes are ignored; reads always return 0.
0
RESERVED RO
0
Reserved. Writes are ignored; reads always return 0.
Note: This corresponds to the setting of position 6 of the SW1 Configuration Switch block. Refer to the EPM-39
Hardware Reference Manual for more information regarding the configuration switches.

FPGA Registers
EPM-39 Programmer’s Reference Manual 10
TIMER REGISTERS
The FPGA implements an 8254-compatible timer/counter that includes three 16-bit timers.
Table 9: TICR – 8254 Timer Interrupt Control Register
Bit Identifier Access Default Description
7 IRQEN R/W 0 8254 Timer interrupt enable/disable: 0 – Interrupts disabled
1 – Interrupts enabled
6-4 IRQSEL(2:0) R/W 000
8254 Timer interrupt IRQ select in LPC SERIRQ:
000 – IRQ3
001 – IRQ4
010 – IRQ5
011 – IRQ10
100 – IRQ6
101 – IRQ7
110 – IRQ9
111 – IRQ11
3 RESERVED RO 0 Reserved. Writes are ignored; reads always return 0.
2 IMSK_TC5 R/W 0 8254 timer #5 interrupt mask: 0 – Interrupt disabled
1 – Interrupt enabled
1 IMSK_TC4 R/W 0 8254 timer #4 interrupt mask: 0 – Interrupt disabled
1 – Interrupt enabled
0 IMSK_TC3 R/W 0 8254 timer #3 interrupt mask: 0 – Interrupt disabled
1 – Interrupt enabled

FPGA Registers
EPM-39 Programmer’s Reference Manual 11
Table 10: TISR – 8254 Timer Interrupt Status Register
Bit Identifier Access Default Description
7
RESERVED
RO
0
Reserved. Writes are ignored; reads always return 0.
6
RESERVED
RO
0
Reserved. Writes are ignored; reads always return 0.
5
RESERVED
RO
0
Reserved. Writes are ignored; reads always return 0.
4
RESERVED
RO
0
Reserved. Writes are ignored; reads always return 0.
3
RESERVED
RO
0
Reserved. Writes are ignored; reads always return 0.
2 ISTAT_TC5 RW/C N/A
Status for the 8254 Timer #5 output (terminal count) interrupt
when read. This bit is read-status and a write-1-to-clear.
0 – Timer output (terminal count) has not transitioned from 0 to
a 1 level
1 – Timer output (terminal count) has transitioned from a 0 to a
1 level
1 ISTAT_TC4 RW/C N/A
Status for the 8254 Timer #4 output (terminal count) interrupt
when read. This bit is read-status and a write-1-to-clear.
0 – Timer output (terminal count) has not transitioned from 0 to
a 1 level
1 – Timer output (terminal count) has transitioned from a 0 to a
1 level
0 ISTAT_TC3 RW/C N/A
Status for the 8254 Timer #3 output (terminal count) interrupt
when read. This bit is read-status and a write-1-to-clear.
0 – Timer output (terminal count) has not transitioned from 0 to
a 1 level
1 – Timer output (terminal count) has transitioned from a 0 to a
1 level

FPGA Registers
EPM-39 Programmer’s Reference Manual 12
Table 11: TCR – 8254 Timer Control Register
Bit Identifier Access Default Description
7 TMR5GATE R/W 0
Debug/Test Only: Controls the “gate” signal on 8254 timer #5 when not
using an external gate signal:
0 – Gate on signal GCTC5 is disabled
1 – Gate on signal GCTC5 is enabled
Always set to 0 when configuring timer modes except when TMRFULL
is ‘0’ and then it should be set to ‘1’ and not changed unless using
internal clocking.
6 TMR4GATE R/W 0
Controls the “gate” signal on 8254 timer #4 when not using an external
gate signal:
0 – Gate on signal GCTC4 is disabled
1 – Gate on signal GCTC4 is enabled
Always set to 0 when configuring timer modes except when TMRFULL
is ‘0’ and then it should be set to ‘1’ and not changed unless using
internal clocking
5 TMR3GATE R/W 0
Controls the “gate” signal on 8254 timer #3 when not using an external
gate signal:
0 – Gate on signal GCTC3 is disabled
1 – Gate on signal GCTC3 is enabled
Always set to 0 when configuring timer modes except when TMRFULL
is ‘0’ and then it should be set to ‘1’ and not changed unless using
internal clocking
4 TM45MODE R/W 0
Mode to set timers #4 and #5 in:
0 – Timer #4 and #5 form one 32-bit timer controlled by timer #1 signals
1 – Timer #4 and Timer #5 are separate 16-bit timers with their own
control signals.
Almost always used in 32-bit mode especially when TMRFULL is a ‘0’
(the 16-bit timer #5 if of limited use)
3 TM4CLKSEL R/W 0
Timer #4 Clock Select:
0 – Use internal 4.125 MHz clock (derived from PCI clock)
1 – Use external ICTC4
Timer #5 is always on internal clock if configured as a 16-bit clock
2 TM3CLKSEL R/W 0 Timer #3 Clock Select:
0 – Use internal 4.125 MHz clock (derived from PCI clock)
1 – Use external ICTC3 assigned to Digital I/O
1
RESERVED
RO
0
Reserved. Writes are ignored; reads always return 0.
0 TMRFULL R/W 0
DIOs to use for timer signals (TMREN must be a ‘1’ in the DIOCR
register to use the timers).
0 – 4-wire timers and DIO16-DIO13 are external timer control signals
1 – 8-wire and DIO16-DIO9 are external timer control signals
Because the gates-controls are not connected to digital I/Os when
TMRFULL is a ‘0’, the TIMxGATE gate controls in this register are used
so they need to be set to ‘1’ and should not be toggled during operation
with external timers (since there is no continuous clock to synchronize
them to) but can be toggled if using the internal clock. If you need
gating in external modes, set TMRFULL to a ‘1’.

FPGA Registers
EPM-39 Programmer’s Reference Manual 13
MISCELLANEOUS FPGAREGISTERS
MISCR1 – Miscellaneous Control Register #1
This is a register in the always-on power well of the FPGA. It holds its state during sleep modes
and can only be reset by a power cycle. This is a placeholder register for features like pushing
the power-button and also for software initiated resets should those be needed. This register is
only reset by the main power-on reset since it must maintain its state in Sleep modes (for
example, S3).
Table 12: MISCR1 – Misc. Control Register #1
Bits Identifier Access Default Description
7-2 Reserved RO 000000 Reserved. Writes are ignored; reads always return 0.
1 FPGA_PSEN R/W 0
FPGA digital I/O and AUX GPIO bank I/O power enable
0 – The digital I/O and AUX GPIO bank will be powered down in
sleep modes (only power in S0)
1 – The digital I/O and AUX GPIO bank will not be powered down in
sleep modes and the configuration will remain.
The FPGA 3.3 V I/O bank power switch is controlled by the “OR” of
the S0 power control signal and FPGA_PSEN.
Note: Some register resets are conditional on the state of
FPGA_PSEN
0 MINI_PSDIS R/W 0
Minicard 3.3 V power disable
0 – Minicard 3.3 V power stays on always (this is normally how
minicards operate if they support any Wake events)
1 – Minicard 3.3 V power will be turned off when not in S0 (in sleep
modes).
The Minicard 3.3 V power switch is controlled by the “OR” of the S0
power control signal and the inverse of MINI_PSDIS.
MISCR2 – Miscellaneous Control Register #2
This is a register in the always-on power well of the FPGA. It holds its state during sleep
modes and can only be reset by a power cycle. It is primarily used for control signals for
the always-powered Ethernet controllers and the USB hubs. This register is only reset by
the main power-on reset since it must maintain its state in sleep modes (for example, S3).

FPGA Registers
EPM-39 Programmer’s Reference Manual 14
Table 13: MISCSR2 – Misc. Control Register #2
Bit Identifier Access Default Description
7 USB_HUBMODE R/W 0
Determines whether the hub resets only once (to support wake-up from
sleep modes on USB ports) or resets every time it enters sleep modes
using the platform reset:
0 – USB hub is reset once at power on. Use USB_HUBDIS to manually
control the reset if necessary. This supports USB wake-up modes
1 – USB hub is reset by platform reset every time (will be reset when
entering all sleep modes). USB ports cannot be used to wake-up
6 W_DISABLE R/W 0
Used to control the W_DISABLE (Wireless Disable) signal going to the
PCIe Mincard:
0 – W_DISABLE signal is not asserted (Enabled)
1 – W_DISABLE signal is asserted (Disabled)
Note: There are other control sources that can be configured to control
this signal and if enabled the control becomes the “OR” of all sources
5
Reserved
4 ETHOFF0 R/W 0
Used to disable the Ethernet controller #0 (controls the ETH_OFF#
input to the I210-IT):
0 – Ethernet controller is enabled (On)
1 – Ethernet controller is disabled (Off)
3 USB_USBID R/W 0
Set to use the “ID” signal on the on-board USB 3.0 signal to control the
VBUS power. USB OTG (on-the-go) uses this signal to tell whether an
“A” or “B” cable is plugged in a micro-USB 3.0 “AB” connector. When
USB_USBID is set to a ‘1’, an “A” cable will turn VBUS power on and a
“B” will turn it off (because “B” devices are not supported).
0 – Do not use “ID” signal to control VBUS power (VBUS power
controlled only by USB_OBDIS)
1 – Use “ID” signal to control VBUS power (USB_OBDIS will still
disable VBUS power)
2 USB_HUBDIS R/W 0 Control the reset on the USB2513B Hub.
0 – USB2513 hub is enabled (reset released)
1 – USB2513 hub is in reset
1 USB_PBDIS R/W 0
Disable control for the paddleboard USB port VBUS power switches
(there are two power-switches but they have a common power enable
and overcurrent status)
0 – VBUS power switches are enabled
1 – VBUS power switched are disabled.
Note: The I2164 power switches latch-off in overcurrent and can only
be re-enabled by a power-cycle or by setting this bit to a 1, wait >1 ms,
and then a 0
0 USB_OBDIS R/W 0
Disable control for the on-board USB port VBUS power switches (there
are two with a common overcurrent):
0 – VBUS power switches are enabled
1 – VBUS power switched are disabled.
Note: The I2164 power switches latch-off in overcurrent and can only
be re-enabled by a power-cycle of by setting this bit to a 1 and then a 0
with at least 1 ms in between

FPGA Registers
EPM-39 Programmer’s Reference Manual 15
MISCR3 – Miscellaneous Control Register #3
This register sets the SMBus addresses on the 4-Port PCIe Switch.
Table 14: MISCR3 – Misc. Control Register #3
Bits Identifier Access Default Description
7-4 Reserved RO 0000 Reserved. Writes are ignored; reads always return 0.
3 USB_PBOC RO N/A
Reads the overcurrent status for the USB paddleboard power
switches (there are two power switches for the four ports but they
have a common overcurrent status).
0 – Overcurrent is not asserted (power switch is on)
1 – Overcurrent is asserted (power switch is off)
2 PBRESET R/W ---
When written to, this will do the same thing as pushing the reset
button, which could be useful for a software-initiated watchdog.
0 – No action
1 – Activate the reset push-button
Note: Because this generates a reset that will reset this register, it
isn’t likely a value of a ‘1’ can ever be read-back, so it is somewhat
“write-only”.
1-0
Reserved
RO
00
Reserved. Writes are ignored; reads always return 0.