Phytec phyCORE-AM65x User manual

A product of a PHYTEC Technology Holding company
phyCORE®-AM65x
Hardware Manual
Document No.:
L-860e.A1
SOM Prod. No.:
PCM-067
SOM PCB. No.:
1498.2
CB Prod. No.:
PCM-941
CB PCB. No.:
1499.3
Edition:
Oct 2023

PCM-067/phyCORE-AM65x System on Module
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1Table of Contents
1Table of Contents.................................................................................................................................. 2
1.1 List of Figures................................................................................................................................. 6
1.2 List of Tables.................................................................................................................................. 7
2SOM Features....................................................................................................................................... 9
3Conventions, Abbreviations and Acronyms........................................................................................... 10
3.1 Conventions................................................................................................................................. 10
3.2 Abbreviations and Acronyms......................................................................................................... 10
3.3 Types of Signals........................................................................................................................... 12
4Introduction......................................................................................................................................... 13
Block Diagram........................................................................................................................................ 14
4.1 Physical Dimensions..................................................................................................................... 15
4.2 Connector Alignment for Mating to Carrier Boards ......................................................................... 17
4.3 Component Placement Diagram.................................................................................................... 19
4.4 Technical and Electrical Specifications.......................................................................................... 21
4.5 Minimum Requirements for Operation ........................................................................................... 21
4.6 Solder Jumpers............................................................................................................................ 22
4.7 Pin Descriptions ........................................................................................................................... 27
4.8 Pinout Table................................................................................................................................. 29
4.9 Thermal Management................................................................................................................... 37
4.10 Layout Guidelines......................................................................................................................... 38
4.10.1 High-Speed Differential Signal Routing Guidelines.................................................................. 38
4.10.2 General Signal Routing Guidelines......................................................................................... 39
5Power................................................................................................................................................. 39
5.1 Primary System Power (VIN)......................................................................................................... 40
5.1.1 Primary Power Reference Circuit............................................................................................ 40
5.2 Backup Power (VBAT).................................................................................................................. 41
5.3 Reset........................................................................................................................................... 41

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5.4 Power Sequencing ....................................................................................................................... 43
5.5 Safe Shutdown and Sudden Power Loss....................................................................................... 43
6System Memory.................................................................................................................................. 44
6.1 SOM Memory............................................................................................................................... 44
6.1.1 DDR4 RAM........................................................................................................................... 44
6.1.2 EEPROM .............................................................................................................................. 44
6.1.3 eMMC Flash.......................................................................................................................... 44
6.2 External Memory Bus ................................................................................................................... 45
6.2.1 OSPI and HYPERBUS........................................................................................................... 45
6.2.2 SD/MMC/SDIO...................................................................................................................... 46
6.3 System Boot Configuration............................................................................................................ 48
7Serial Interfaces.................................................................................................................................. 52
7.1 CAN............................................................................................................................................. 52
7.1.1 CAN Pinout ........................................................................................................................... 52
7.1.2 CAN Reference Circuit........................................................................................................... 52
7.2 Ethernet....................................................................................................................................... 52
7.2.1 Ethernet Pinout...................................................................................................................... 53
7.2.2 Ethernet Design In Guide....................................................................................................... 62
7.2.3 Ethernet Reference Circuits ................................................................................................... 66
7.3 I2C............................................................................................................................................... 67
7.3.1 I2C Pinout.............................................................................................................................. 68
7.4 MCASP........................................................................................................................................ 68
7.4.1 MCASP Pinout ...................................................................................................................... 69
7.5 PCIe............................................................................................................................................ 70
7.5.1 PCIe Pinout........................................................................................................................... 70
7.5.2 PCIe (SERDES) Design In Considerations.............................................................................. 71
7.5.3 PCIe Reference Circuits......................................................................................................... 71
7.6 SPI .............................................................................................................................................. 72
7.6.1 SPI Pinout............................................................................................................................. 73

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7.7 UART........................................................................................................................................... 73
7.7.1 UART Pinout ......................................................................................................................... 74
7.8 USB............................................................................................................................................. 75
7.8.1 USB Pinout............................................................................................................................ 75
7.8.2 USB Design In Considerations............................................................................................... 76
7.8.3 USB Reference Circuits......................................................................................................... 77
8Display and Camera Interfaces............................................................................................................ 78
8.1 VOUT .......................................................................................................................................... 79
8.1.1 VOUT Pinout......................................................................................................................... 79
8.2 OLDI/LVDS.................................................................................................................................. 80
8.2.1 OLDI/LVDS Pinout................................................................................................................. 80
8.2.2 OLDI/LVDS Design In Considerations..................................................................................... 80
8.2.3 OLDI/LVDS Reference Circuits............................................................................................... 81
8.3 CSI.............................................................................................................................................. 81
8.3.1 CSI Pinout............................................................................................................................. 81
8.3.2 CSI Design In Considerations................................................................................................. 82
8.3.3 CSI Reference Circuits........................................................................................................... 83
8.4 Parallel Video Input Port ............................................................................................................... 84
8.4.1 Parallel Video Input Port Pinout.............................................................................................. 84
9Control Interfaces................................................................................................................................ 84
9.1 Enhanced Capture........................................................................................................................ 84
9.1.1 ECAP Pinout ......................................................................................................................... 85
9.2 Enhanced Pulse-Width Modulation................................................................................................ 85
9.2.1 EPWM Pinout........................................................................................................................ 85
9.3 Enhanced Quadrature Encoder Pulse ........................................................................................... 86
9.3.1 EQEP Pinout......................................................................................................................... 86
10 Peripheral Interfaces ........................................................................................................................... 86
10.1 ADC............................................................................................................................................. 86
10.1.1 ADC Pinout ........................................................................................................................... 87

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10.2 GPIO ........................................................................................................................................... 87
10.2.1 GPIO Pinout.......................................................................................................................... 87
10.3 WIFI/BT ....................................................................................................................................... 92
10.3.1 WIFI/BT Pinout...................................................................................................................... 93
11 Debug Interfaces................................................................................................................................ 93
11.1 JTAG........................................................................................................................................... 93
11.1.1 JTAG Pinout.......................................................................................................................... 93
11.1.2 JTAG Reference Circuit......................................................................................................... 94
11.2 UART1......................................................................................................................................... 95
11.2.1 UART1 Pinout ....................................................................................................................... 95
11.2.2 UART1 Reference Circuits..................................................................................................... 95
12 System Interfaces................................................................................................................................ 97
12.1 RTC Pinout.................................................................................................................................. 97
13 Integrating and Updating the phyCORE-AM65x.................................................................................... 98
13.1 Integration.................................................................................................................................... 98
13.2 Modification.................................................................................................................................. 98
13.3 In-Field Updates........................................................................................................................... 98
13.4 Product Change Management....................................................................................................... 99
14 Additional Information.........................................................................................................................100
15 Revision History.................................................................................................................................102

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1.1 List of Figures
Figure 1. phyCORE-AM65x SOM............................................................................................................. 13
Figure 2. phyCORE-AM65x Block Diagram............................................................................................. 14
Figure 3. phyCORE-AM65x Dimensions Top View ................................................................................. 15
Figure 4. phyCORE-AM65x Dimensions Bottom View............................................................................ 16
Figure 5. phyCORE-AM65x Dimensions End View ................................................................................. 16
Figure 6. Top Down View of Mating Connectors..................................................................................... 17
Figure 7. Carrier Board Alignment Hole Placement................................................................................ 18
Figure 8. phyCORE-AM65x Component Placement (processor side) .................................................... 19
Figure 9. phyCORE-AM65x Component Placement (connector side)..................................................... 20
Figure 10. 3-Position Solder Jumper Pad Numbering Scheme ............................................................... 22
Figure 11. Jumper Locations (Processor side)........................................................................................ 25
Figure 12. Jumper Locations (Connector side) ....................................................................................... 26
Figure 13. Pinout of the phyCORE-Connector........................................................................................ 27
Figure 14. Pinout example using X_MMC1_DAT1 in our schematic....................................................... 28
Figure 15. Primary Power VIN(VCC_3V3) reference circuit ..................................................................... 40
Figure 16. SOM current reader reference circuit ..................................................................................... 41
Figure 17. Carrier board power reference circuit..................................................................................... 43
Figure 18. MMC1 SD-card Reader Reference Schematic......................................................................... 48
Figure 19. MMC1 Load Switch Reference Schematic.............................................................................. 48
Figure 20. BOOTMODE pullups/pulldowns.............................................................................................. 49
Figure 21. Reference Schematic for BOOTMODE configuration............................................................. 51
Figure 22. MCAN0 Reference Schematic................................................................................................. 52
Figure 23. RJ45 Reference Schematic..................................................................................................... 66
Figure 24. RGMII PHY Strapping Resistors Reference Schematic .......................................................... 67
Figure 25. RGMII PHY Reference Schematic ........................................................................................... 67
Figure 26. PCIe Connector Reference Schematic.................................................................................... 72
Figure 27. PCIe Clock Generator Reference Schematic .......................................................................... 72
Figure 28. USB 3.0 Connector Reference Schematic .............................................................................. 77
Figure 29. USB Micro Connector Reference Schematic.......................................................................... 78
Figure 30. USB Power Switch Reference Schematic............................................................................... 78
Figure 31. OLDI Connector Reference Schematic................................................................................... 81
Figure 32. CSI Power Toggle Reference Schematic ................................................................................ 83
Figure 33. CSI Connector Reference Schematic...................................................................................... 83
Figure 34. JTAG Reference Schematic.................................................................................................... 94
Figure 35. UART0 to USB Bridge Reference Schematic.......................................................................... 95

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Figure 36. UART0 to USB Regulator Reference Schematic..................................................................... 96
1.2 List of Tables
Table 1 Abbreviations and Acronyms used in this Manual ..................................................................... 11
Table 2 Signal Types Used in this Manual............................................................................................... 12
Table 3 Technical Specifications............................................................................................................. 21
Table 4 Recommended Operating Conditions for the Input and Output Power Domains....................... 21
Table 5 Solder Jumper Settings............................................................................................................... 22
Table 6 Voltage Domain Configurations.................................................................................................. 23
Table 7 phyCORE-AM65x Connector X1, Column A Pinout .................................................................... 29
Table 8 phyCORE-AM65x Connector X1, Column B Pinout .................................................................... 31
Table 9 phyCORE-AM65x Connector X2, Column A Pinout .................................................................... 33
Table 10 phyCORE-AM65x Connector X2, Column B Pinout................................................................... 35
Table 11 Thermal Management Parts....................................................................................................... 37
Table 12 External Supply Voltages.......................................................................................................... 39
Table 13 Reset Pin Description................................................................................................................ 43
Table 14 OSPI/HYPERBUS Connections at the phyCORE-Connector..................................................... 45
Table 15 MMC Connections at the phyCORE-Connector ........................................................................ 46
Table 16 phyCORE-AM65x MMC1 Layout Characteristics....................................................................... 47
Table 17 MCU_BOOTMODE Description.................................................................................................. 50
Table 18 BOOTMODE Description ........................................................................................................... 51
Table 19 MCAN Connections at the phyCORE-Connector ...................................................................... 52
Table 20 Ethernet PHY Default Strapping Configuration......................................................................... 53
Table 21 Ethernet Connections at the phyCORE-Connector................................................................... 53
Table 22 IEP Connections at the phyCORE-Connector........................................................................... 54
Table 23 PRU_ICSSG0 Connections at the phyCORE-Connector........................................................... 55
Table 24 PRU_ICSSG1 Connections at the phyCORE-Connector........................................................... 57
Table 25 PRU_ICSSG2 Connections at the phyCORE-Connector........................................................... 59
Table 26 phyCORE-AM65x CPSW_ETH0 Layout Characteristics............................................................ 62
Table 27 phyCORE-AM65x RGMII Timing Requirements......................................................................... 63
Table 28 phyCORE-AM65x PRG1 RMGII1 Trace Length Characteristics ................................................ 63
Table 29 phyCORE-AM65x PRG1 RMGII2 Trace Length Characteristics ................................................ 64
Table 30 phyCORE-AM65x PRG2 RMGII1 Trace Length Characteristics ................................................ 64
Table 31 phyCORE-AM65x PRG2 RMGII2 Trace Length Characteristics ................................................ 65
Table 32 phyCORE-AM65x PRG0 RMGII1 Trace Length Characteristics ................................................ 65
Table 33 phyCORE-AM65x PRG0 RMGII2 Trace Length Characteristics ................................................ 65

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Table 34 I2C Connections at the phyCORE-Connector............................................................................ 68
Table 35 MCASP Connections at the phyCORE-Connector.................................................................... 69
Table 36 PCIe Connections at the phyCORE-Connector......................................................................... 70
Table 37 phyCORE-AM64xx SERDES Layout Characteristics................................................................. 71
Table 38 SPI Connections at the phyCORE-Connector........................................................................... 73
Table 39 UART Connections at the phyCORE-Connector....................................................................... 74
Table 40 USB Connections at the phyCORE-Connector ......................................................................... 75
Table 41 phyCORE-AM65x USB2.0 Layout Characteristics..................................................................... 76
Table 42 phyCORE-AM64xx USB3.1 Layout Characteristics................................................................... 77
Table 43 VOUT Connections at the phyCORE-Connector....................................................................... 79
Table 44 OLDI/LVDS Connections at the phyCORE-Connector .............................................................. 80
Table 45 phyCORE-AM65x OLDI0 Layout Characteristics....................................................................... 80
Table 46 CSI Connections at the phyCORE-Connector........................................................................... 81
Table 47 phyCORE-AM65x USB0 Layout Characteristics ....................................................................... 82
Table 48 Parallel Video Input Port Connections at the phyCORE-Connector......................................... 84
Table 49 ECAP Connections at the phyCORE-Connector....................................................................... 85
Table 50 EPWM Connections at the phyCORE-Connector...................................................................... 85
Table 51 EQEP Connections at the phyCORE-Connector....................................................................... 86
Table 52 ADC Connections at the phyCORE-Connector......................................................................... 87
Table 53 Total Available GPIO.................................................................................................................. 87
Table 54 GPIO0 Accessibility at phyCORE-Connector............................................................................ 87
Table 55 GPIO1 Accessibility at phyCORE-Connector............................................................................ 90
Table 56 WKUP_GPIO0 Accessibility at phyCORE-Connector................................................................ 91
Table 57 MMC1_SELECT Configuration .................................................................................................. 92
Table 58 WIFI/BT Signals......................................................................................................................... 93
Table 59 JTAG Connections at the phyCORE-Connector ....................................................................... 93
Table 60 UART1 Connections at the phyCORE-Connector..................................................................... 95
Table 61 RTC Connections at the phyCORE-Connector.......................................................................... 97
Table 62 Document Revision History......................................................................................................102

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2SOM Features
The phyCORE-AM65x offers the following features:
•Insert-ready, sub-miniature (55 mm x 65 mm) System on Module (SOM) subassembly in low EMI design,
achieved through advanced SMD technology
•Populated with the Texas Instruments AM65x microcontroller (23 x 23 mm, 0.8 mm pitch S-PBGA)
•Up to 1.1 GHz core clock frequency
•Single supply voltage of +3.3V with on-board power management
•Up to 4GB DDR4 RAM with optional ECC
•Up to 32GB on-board eMMC
•4KB I2C EEPROM
•On-board I2C RTC
•360 pin interconnect: 2x 0.5mm pitch 2x90 pin Samtec connectors (BSH-090-01-L-D-A-TR) that expose the
following interfaces
•1x General-purpose memory controller
•1x MMC/SD 4-bit interface
•1x SuperSpeed USB3.1 dual-role port
•1x USB 2.0 dual-role port
•2x Independent 1-lane or a single 2-lane PCIe Gen3 interface
•1x 10/100/1000 Mbit Ethernet interface provided via on-board PHY
•3x Gigabit PRU industrial subsystems featuring up to 2x 10/100/1000 ethernet ports each
•2x MCAN interfaces
•3x MCASP Audio interfaces
•1x MIPI DPI parallel display interface
•1x OLDI LVDS display interface
•1x MIPI CSI-2 camera interface
•1x Video Input Port parallel camera interface
•6x I2C interfaces
•4x SPI interfaces
•2x OSPI interfaces
•1x Hyperbus interface
•5x UART interfaces
•4x ADC inputs
•6x Enhanced High Resolution PWM modules
•1x Enhanced Captures (eCAP) module
•2x Enhanced Quadrature Encoder Pulse modules (eQEP)
•1x JTAG debug port
•GPIO
NOTE:
Some of the features listed are not available simultaneously due to the multiplexing options of the various
processor pins. Refer to the sections 5 –12 of the manual for further information on available multiplexing
options and the pinout of signals.

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3Conventions, Abbreviations and Acronyms
This hardware manual describes the PCM-067 System onModule, henceforth referred to as phyCORE-AM65x. The manual
specifies the phyCORE-AM65x's design and function. Precise specifications for the Texas Instruments AM65xx SoC can be
found in the AM65xx Technical Reference Manual.
We refrain from providing detailed part specific information within this manual which could be subject to changes. This is
due to the continuous maintenance of our products. Please read section 13.4 Product Change Management for more
information.
The BSP delivered with the phyCORE-AM65x includes drivers and/or software for controlling all components such as
interfaces, memory, etc. Therefore, programming close to the hardware (at the register level) is not necessary in most
cases. For this reason, this manual contains no detailed description of the processor's registers, or information relevant
for software development. Please refer to the AM65xx Technical Reference Manual if such information is needed.
3.1 Conventions
The conventions used in this manual are as follows:
•Signals that are preceded by an "n" or end in z (e.g.: nRD or RDz), are designated as active low signals. That is,
their active state is when they are driven low, or are driving low.
•A "0" indicates a logic zero or low-level signal, while a "1" represents a logic one or high-level signal.
•The hex-numbers given for addresses of I2C devices always represent the 7 most-significant bits (MSB) of the
address byte. The correct value of the least-significant bit (LSB) will depend on the desired command (read (1) or
write (0)) and must be added to get the complete address byte. E.g. given the address in this manual 0x41 => the
complete address byte = 0x83 reads from the device and 0x82 to writes to the device
•Text in blue italics indicate a cross-reference to an internal section of this Document. Click these links to quickly
jump to the applicable part, chapter, table, or figure.
•Text in underlined in blue indicate an external link. Click these links to quickly jump to the applicable URL.
•References made to the phyCORE-Connector always refer to the high density Samtec connectors on the
undersides of the phyCORE-AM65x System on Module.
3.2 Abbreviations and Acronyms
Many acronyms and abbreviations are used throughout this manual. Use the table below to navigate unfamiliar terms
used in this document.

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Table 1 Abbreviations and Acronyms used in this Manual
Abbreviation
Definition
BSP
Board Support Package (Software delivered with the Development Kit including an operating system
(Linux) preinstalled on the module and Development Tools)
CB
Carrier Board; used in reference to the phyCORE Development Kit Carrier Board
DDR
Double data rate
DRAM
Dynamic random access memory
EMC
Electromagnetic Compatibility
EMI
Electromagnetic Interference
FSI
Fast Serial Interface
GPIO
General-Purpose Input/Output
GPT
General-Purpose Timer
J
Solder Jumper: these types of jumpers require solder equipment to remove and place
JP
Solderless Jumper: these types of jumpers can be removed and placed by hand with no special tools
JTAG
Joint Test Action Group (a serial bus protocol usually used for test purposes)
LCD
Liquid Crystal Display
PCB
Printed circuit board
PCI
Peripheral Component Interconnect
PCIe
PCI express
PCM/PCL
phyCORE Module (connectorized / direct solder)
PCN
Product Change Notification
PDI
PHYTEC Display Interface; defined to connect PHYTEC display adapter boards, or custom adapters
PEB
PHYTEC Expansion Board
PMIC
Power management IC
POR
Power-on reset
PRU
Programmable Realtime Unit
PWM
Pulse-width Modulation
RTC
Real-time clock
SD
Secure Digital
SMT
Surface mount technology
SOC
System on Chip
SOM
System on Module; used in reference to the BOARD DESIGNATOR/ SOM BOARD NAME module
SPI
Serial Peripheral Interface
Sx
User button Sx(e.g. S1, S2, etc.) used in reference to the available user buttons, or DIP-Switches on
the Carrier Board
UART
Universal Asynchronous Receiver/Transmitter
USB
Universal Serial Bus

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3.3 Types of Signals
Different types of signals are brought out at the phyCORE-Connector. Table 2 below lists the abbreviations used to specify
the type of a signal.
Table 2 Signal Types Used in this Manual
Signal Type
Description
Abbreviation
Analog
Analog
A
Power
Supply voltage input
PWR_I
Input
Digital input
I
Output
Digital output
O
IO
Bidirectional input/output
I/O
OD-Bidir PU
Open drain input/output with pull up
OD-BI
OD-Output
Open drain output without pull-up, requires an external pull-up
OD
5V Input PD
5 V tolerant input with pull down
5V_PD
LVDS Input
Differential line pairs 100 ΩLVDS level input
LVDS_I
LVDS Output
Differential line pairs 100 ΩLVDS level output
LVDS_O
USB IO
Differential line pairs 90 ΩUSB level bidirectional input/output
USB_I/O
ETHERNET Input
Differential line pairs 100 ΩEthernet level input
ETH_I
ETHERNET Output
Differential line pairs 100 ΩEthernet level output
ETH_O
ETHERNET IO
Differential line pairs 100 ΩEthernet level bidirectional input/output
ETH_I/O
PCIe Input
Differential line pairs 100 ΩPCIe level input
PCIe_I
PCIe Output
Differential line pairs 100 ΩPCIe level output
PCIe_O
MIPI CSI-2 Input
Differential line pairs 100 ΩMIPI CSI-2 level input
CSI-2_I

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4Introduction
Figure 1. phyCORE-AM65x SOM
The phyCORE-AM65x belongs to PHYTEC’s phyCORE System on Module family. The phyCORE boards integrate all core
elements of a SoC on a single module and are designed in a manner that ensures their easy expansion and embedding in
peripheral hardware developments.
The phyCORE-AM65x is a 55mm x 65mm insert-ready System on Module populated with the Texas Instrument’s
AM65xx SoC. Its universal design enables its insertion in a wide range of embedded applications. Most of the SoC signals
and ports extend from the SoC to the high-density pitch (0.5 mm) connectors aligning two sides of the board, allowing it
to be plugged directly into a target application.
Implementing a phyCORE-AM65x SOM as the core of your embedded design allows for increased focus on hardware
peripherals and firmware without expending resources to re-invent microprocessor circuitry or other commonly used
circuitry that has already been implemented on the phyCORE-AM65x including a DDR4 RAM, an eMMC, a power
distribution network, an Ethernet PHY, an RTC, and an EEPROM. Production-ready board support packages (BSPs), design
services for our hardware, and lifecycle maintenance of our parts will further reduce development time, risk, and allows
for increased focus on product expertise. Take advantage of PHYTEC products to shorten time-to-market, reduce
development costs, and avoid substantial design issues and risks. With this new innovative full system solution, new ideas
can be brought to market in the most timely and cost-efficient manner.
Precise specifications for the processor populating the board can be found in the applicable processor reference manual
or datasheet. The descriptions in this manual are based on the Texas Instrument’s AM65xx. No descriptions of compatible
SoC derivative functions are included; these are not relevant for the basic functioning of the phyCORE-AM65x.

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Block Diagram
Figure 2. phyCORE-AM65x Block Diagram

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4.1 Physical Dimensions
Figure 3. phyCORE-AM65x Dimensions Top View

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Figure 4. phyCORE-AM65x Dimensions Bottom View
Figure 5. phyCORE-AM65x Dimensions End View

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4.2 Connector Alignment for Mating to Carrier Boards
The phyCORE-AM65x has two mounting holes in the lower left and upper right corner sized for M2.5 screws/components.
It is recommended to use the following mounting hardware to secure the SOM to a mating carrier board:
•2x M2.5x5mm Female-Female Standoffs
•4x M2.5x4mm Screws
•4x M2.5 Washers
Figure 6. Top Down View of Mating Connectors

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Figure 7. Carrier Board Alignment Hole Placement

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4.3 Component Placement Diagram
Figure 8. phyCORE-AM65x Component Placement (processor side)

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Figure 9. phyCORE-AM65x Component Placement (connector side)
A searchable pdf of the phyCORE-AM65x component placement can be found here.