VIA Technologies QSM-8Q60 Guide

1.01-09022020-175700
DESIGN GUIDE
Carrier Board
for VIA QSM-8Q60 Qseven™ ARM module

Copyright
Copyright © 2017-2020 VIA Technologies Incorporated. All rights reserved.
No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language,
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information and product specifications within this document are subject to change at any time, without notice and without obligation
to notify any person of such change.
VIA Technologies, Inc. reserves the right the make changes to the products described in this manual at any time without prior notice.
Regulatory Compliance
FCC-A Radio Frequency Interference Statement
This equipment has been tested and found to comply with the limits for a class A digital device, pursuant to part 15 of the FCC rules.
These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a
commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in
accordance with the instruction manual, may cause harmful interference to radio communications. Operation of this equipment in a
residential area is likely to cause harmful interference, in which case the user will be required to correct the interference at his
personal expense.
Notice 1
The changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to
operate the equipment.
Notice 2
Shielded interface cables and A.C. power cord, if any, must be used in order to comply with the emission limits.
Notice 3
The product described in this document is designed for general use, VIA Technologies assumes no responsibility for the conflicts or
damages arising from incompatibility of the product. Check compatibility issue with your local sales representatives before placing
an order.

Carrier Board Design Guide for VIA QSM-8Q60
iii
Revision History
Revision
Date
Description
1.00 03/07/2017 Initial release
1.01 09/02/2020 Updated VIA logo and copyright year

Carrier Board Design Guide for VIA QSM-8Q60
iv
Table of Contents
1. Introduction ...................................................................................................................................1
1.1. Document Overview.........................................................................................................................................1
1.2. Acronyms and Definitions ...............................................................................................................................2
1.3. Illustrations and Schematics............................................................................................................................3
2. General Carrier Board Recommendations ...............................................................................4
2.1. PCB Stackup Example.......................................................................................................................................4
2.1.1. Microstrip Versus Stripline Designs .......................................................................................................4
2.2. General Layout and Routing Guidelines ......................................................................................................6
2.2.1. Routing Styles and Topology ..................................................................................................................6
2.2.2. General Trace Attribute Recommendations ........................................................................................7
2.2.3. General Clock Routing Considerations .................................................................................................7
3. Qseven Specification Overview.................................................................................................9
3.1. Qseven Module Placement.............................................................................................................................9
3.2. Qseven Mechanical Characteristics...............................................................................................................9
3.3. VIA QSM-8Q60 Module and Carrier Board Dimensions........................................................................... 10
3.4.MXM Connector ............................................................................................................................................. 11
3.4.1. MXM Connector Dimensions................................................................................................................ 11
3.4.2. MXM Connector Footprint .................................................................................................................... 12
3.4.3. VIA QSM-8Q60 Module and MXM Connector Footprint ............................................................. 12
3.5. MXM Connector Pinouts............................................................................................................................... 13
4. Layout and Routing Recommendations ..................................................................................17
4.1. PCI Express Interface ..................................................................................................................................... 17
4.1.1. MiniPCIe Slot............................................................................................................................................ 17
4.1.2. PCI Express Layout and Routing Recommendations ....................................................................... 19
4.1.3. PCI Express Reference Schematics ...................................................................................................... 20
4.2. Ethernet Interface ........................................................................................................................................... 21
4.2.1. Ethernet Interface Topology................................................................................................................. 22
4.2.2. Gigabit Ethernet Layout and Routing Recommendations............................................................... 23
4.2.3. Gigabit Ethernet Reference Schematics ............................................................................................. 24
4.3. USB Interface ................................................................................................................................................... 25
4.3.1. USB Layout and Routing Recommendations ..................................................................................... 25
4.3.2. USB Reference Schematics.................................................................................................................... 28
4.4. LVDS Interface................................................................................................................................................. 29
4.4.1. LVDS Layout and Routing Recommendations................................................................................... 30
4.4.2. LVDS Reference Schematics ................................................................................................................. 32
4.5. HDMI Interface ................................................................................................................................................ 33
4.5.1. HDMI Layout and Routing Recommendations.................................................................................. 34
4.5.2. HDMI Reference Schematics................................................................................................................. 35
4.6. Audio Interface ............................................................................................................................................... 36
4.6.1. Audio Layout and Routing Recommendations ................................................................................. 36
4.6.2. Audio Reference Schematics ................................................................................................................ 37

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List of Figures
Figure 1: Conventions pertaining to schematics............................................................................................................3
Figure 2: Six-layer microstrip PCB stackup example....................................................................................................4
Figure 3: Six-layer stripline PCB stackup example .......................................................................................................4
Figure 4: Point-to-point and multi-drop examples ......................................................................................................6
Figure 5: Daisy-chain example ..........................................................................................................................................6
Figure 6: Alternate multi-drop example.........................................................................................................................6
Figure 7: Suggested clock trace spacing.........................................................................................................................7
Figure 8: Clock trace layout in relation to the ground plane ....................................................................................8
Figure 9: Series termination for multiple clock loads .................................................................................................8
Figure 10: Qseven module placement on carrier board PCB....................................................................................9
Figure 11: Carrier board with Qseven module installed ............................................................................................9
Figure 12: Qseven module and carrier board height distribution ............................................................................9
Figure 13: Dimensions of the VIA QSM-8Q60 module (top view) ....................................................................... 10
Figure 14: Dimensions of the carrier board (top view) ............................................................................................ 10
Figure 15: Dimensions of the MXM connector (top view) ...................................................................................... 11
Figure 16: Dimensions of the MXM connector (side view)..................................................................................... 11
Figure 17: Carrier board PCB footprint for the MXM connector............................................................................ 12
Figure 18: PCB footprint for Qseven module inserted in the MXM connector on the carrier board............ 12
Figure 19: MXM connector schematics ........................................................................................................................ 16
Figure 20: MiniPCIe card and slot diagram.................................................................................................................. 18
Figure 21: MiniPCI Express interface topology example ......................................................................................... 19
Figure 22: PCI Express trace spacing diagram ............................................................................................................ 19
Figure 23: MiniPCIe slot reference circuitry ................................................................................................................ 20
Figure 24: Gigabit Ethernet layout recommendations (integrated magnetic module) ..................................... 22
Figure 25: Gigabit Ethernet reference circuitry........................................................................................................... 24
Figure 26: USB differential signal layout recommendations ................................................................................... 25
Figure 27: USB differential signal routing example................................................................................................... 26
Figure 28: USB 2.0 trace spacing diagram ................................................................................................................... 26
Figure 29: USB host reference circuitry........................................................................................................................ 28
Figure 30: USB client reference circuitry...................................................................................................................... 28
Figure 31: LVDS panel interface implementation ...................................................................................................... 30
Figure 32: LVDS connector example ............................................................................................................................ 32
Figure 33: LVDS panel power reference circuitry...................................................................................................... 32
Figure 34: LVDS backlight reference circuitry............................................................................................................. 32
Figure 35: HDMI interface connector diagram ........................................................................................................... 33
Figure 36: HDMI interface reference circuitry............................................................................................................. 35
Figure 37: Onboard I2S audio codec implementation example ............................................................................ 36
Figure 38: I2S Audio Codec implementation example ............................................................................................. 37

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List of Tables
Table 1: Acronyms and definitions ..................................................................................................................................2
Table 2: General six-layer microstrip PCB stackup ......................................................................................................5
Table 3: PCB stack-up detail .............................................................................................................................................5
Table 4: Recommended trace width and spacing........................................................................................................7
Table 5: MXM connector sample.................................................................................................................................. 11
Table 6: MXM connector pinout ................................................................................................................................... 15
Table 7: PCI Express signal group and definition...................................................................................................... 17
Table 8: MiniPCIe slot pinout definition ...................................................................................................................... 18
Table 9: PCI Express interface routing guidelines ..................................................................................................... 20
Table 10: PCI Express interface layout guidelines .................................................................................................... 20
Table 11: PCI Express interface trace properties....................................................................................................... 20
Table 12: Ethernet signal definition.............................................................................................................................. 21
Table 13: Gigabit Ethernet interface routing guidelines .......................................................................................... 23
Table 14: Gigabit Ethernet interface layout guidelines............................................................................................ 23
Table 15: Gigabit Ethernet interface trace properties .............................................................................................. 24
Table 16: USB signal definition...................................................................................................................................... 25
Table 17: USB interface routing guidelines................................................................................................................. 26
Table 18: USB interface layout guidelines .................................................................................................................. 27
Table 19: USB interface trace properties..................................................................................................................... 27
Table 20: LVDS signal definition ................................................................................................................................... 29
Table 21: LVDS interface routing guidelines .............................................................................................................. 30
Table 22: LVDS interface layout guidelines................................................................................................................ 31
Table 23: LVDS interface trace properties .................................................................................................................. 31
Table 24: HDMI interface signal definition ................................................................................................................. 33
Table 25: HDMI interface routing guidelines ............................................................................................................. 34
Table 26: HDMI interface layout guidelines ............................................................................................................... 34
Table 27: HDMI interface trace properties ................................................................................................................. 34
Table 28: Audio interface signal definition................................................................................................................. 36
Table 29: Audio interface routing guidelines............................................................................................................. 36
Table 30: Audio interface layout guidelines .............................................................................................................. 37
Table 31: Audio interface trace properties................................................................................................................. 37

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1. Introduction
This document provides design guidelines to the developers of a custom Qseven compliant carrier board
that supports the features of VIA QSM-8Q60™module. This document includes the layout and routing
guidelines for general board designs and major underlying interfaces such as PCI Express, Gigabit Ethernet,
USB, LVDS, HDMI and Audio. In addition, the document includes the mechanical information of the
ruggedized MXM connector that provides high speed interfaces between the carrier board and the
module.
Please note that this document is considered to be a reference guide only. This document is not intended
to be a specification. All information and examples listed below are considered to accurate as of the
publication date; however developers must be aware that this document is only a referencing guide.
1.1. Document Overview
A brief description of each chapter is given below.
Chapter 1: Introduction
Briefly introduces the structure of the design guide document.
Chapter 2: General Carrier Board Recommendations
General design schemes and recommended layout rules are shown in this chapter.
Chapter 3: Qseven Specification Overview
Detailed information about the MXM connector placement and dimensions are described.
Chapter 4: Layout and Routing Recommendations
Detailed layout and routing guidelines for each major interface are described.
Appendix A: Carrier Board Reference Schematics
Reference schematics of COMEDB2 evaluation carrier board.

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1.2. Acronyms and Definitions
Term
Description
ASIC
Application-Specific Integrated Circuit
EMI Electromagnetic Interference
GBE Gigabit Ethernet
HDMI
High-Definition Multimedia Interface
IC Integrated Circuit
IEEE Institute of Electrical and Electronics Engineers
IO
Input/Output
I
2
S
Integrated Interchip Sound / Inter-IC Sound
LAN Local Area Network
LCD Liquid Crystal Display
LVDS
Low-Voltage Differential Signaling
MiniPCIe Mini PCI Express
MXM Mobile PCI Express Module
NC
Not Connected / No Connection
OTG On-The-Go
PCB Printed Circuit Board
PCIe
Peripheral Component Interconnect Express
PCIe x1
PCI Express one lane
RJ-45 Registered Jack-45
USB
Universal Serial Bus
Table 1: Acronyms and definitions

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1.3. Illustrations and Schematics
Illustrations and schematics depicted in this document may show the directional flow of signals.
Directional flow is indicated by the pointed ends of the arrow shapes. See Figure 1.
IC
input signal flow output signal flow
bidirectional signal flow
Figure 1: Conventions pertaining to schematics

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2. General Carrier Board Recommendations
This section contains general guidelines for the PCB stackup and the layout of traces. General guidelines
for routing style, topology, and trace attribute recommendations are also discussed.
2.1. PCB Stackup Example
Figure 2 illustrates an example of a PCB with a six-layer stackup. The stackup consists of three signal layers
and three reference (power and ground) layers. The three signal layers are referred to as the component
layer, inner layer and solder layer. The example below also shows the PCB stackup in a microstrip design.
Microstrip stackup design
Solder layer
Ground layer
Power layer
Inner layer
Ground layer
Component layer
Reference layer
Signal layers
Figure 2: Six-layer microstrip PCB stackup example
2.1.1. Microstrip Versus Stripline Designs
Carrier board designers can choose between two basic categories of PCB design: microstrip and stripline.
Microstrip designs have the outer signal layers exposed. Stripline designs have the outermost signal layers
shielded by reference layers.
Stripline stackup design
Ground layer
Solder layer
Power layer
Inner layer
Component layer
Ground layer
Reference layer
Signal layers
Figure 3: Six-layer stripline PCB stackup example
The choice of microstrip or stripline design depends on the application for which the carrier board is
being designed. If the carrier board is being designed for locations where sensitivity to EMI is an issue, a
stripline design is recommended for reducing EMI and noise coupling. For applications where the
tolerance for EMI levels is greater, a microstrip design is recommended to reduce costs. Due to the
inherent nature of stripline PCB stacks, broad-side coupling is possible.

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Layer Description
Thickness Value
Spacing (mil)
Component Layer 0.5 oz. Copper + Planting
~62 mils
Prepeg 2.4 ~3.5 mils thickness
Ground Layer
1.0 oz. Copper
Prepeg
2.4 ~3.5 mils thickness
Inner Layer ~52.3 mils thickness
Prepeg
2.4 ~3.5 mils thickness
Power Layer
1.0 oz. Copper
Prepeg 2.4 ~3.5 mils thickness
Ground Layer
1.0 oz. Copper
Prepeg
2.4 ~ 3.5 mils thickness
Solder Layer 0.5 oz. Copper + Planting
Table 2: General six-layer microstrip PCB stackup
Description
Value
Notes
Dielectric constant (Ɛr) of Prepeg
3.6 ~ 4.2
@ 1GHz
Board Impedance
55Ω± 10%
For all signal layers
Table 3: PCB stack-up detail
Notes:
1. It is not recommended to have any signal routings on either power layer or the ground layer. If a signal must
be routed on the power layer, then it should be routed as short as possible.
2. Signal routing on the ground layer is not allowed.
3. Lower trace impedance providing better signal quality is preferred over higher trace impedance for clock
signals.

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2.2. General Layout and Routing Guidelines
This section provides general layout rules and routing guidelines for designing carrier boards for VIA
QSM-8Q60 module.
2.2.1. Routing Styles and Topology
Topology is the physical connectivity of a net or a group of nets. There are two types of topologies for a
motherboard layout: point-to-point and multi-drop. An example of these topologies is shown in Figure 4.
ASIC
Multi-Drop
Point-to-Point
ASIC
or
Connector
ASIC
ASIC
or
Connector
Figure 4: Point-to-point and multi-drop examples
High-speed bus signals are sensitive to transmission line stubs, which can result in ringing on the rising
edge caused by the high impedance of the output buffer in the high state. In order to maintain better
signal quality, transmission stubs should be kept as short as possible (less than 1.5”). Therefore, daisy
chain style routing is strongly recommended for these signals. Figure 5 below shows an example of daisy
chain routing.
trace segment
ASICASIC
short stub
ASIC
or
Connector
ASIC
or
Connector
Figure 5: Daisy-chain example
If daisy chain routing is not allowed in some circumstances, different routings may be considered. An
alternative topology is shown in Figure 6. In this case, the branch point is somewhere between both ends.
It may be near the source or near the loads. Being close to the load side is best. The separated traces
should be equal in length.
equal length
ASIC
somewhere
in the middle
ASIC
or
Connector
ASIC
or
Connector
Figure 6: Alternate multi-drop example

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2.2.2. General Trace Attribute Recommendations
A 5 mils trace width and 10 mils spacing are generally advised for most signal traces on a carrier board
layout. To reduce trace inductance the minimum power trace width is recommended to be 30 mils.
As a quick reference, the overall recommended trace width and spacing for different trace types are listed
in Table 4, and the recommended trace width and spacing for each signal group is shown in Chapter 4.
Trace Type
Trace Width (mil)
Spacing (mil)
Regular Signal
5 or wider
10 or wider
Interface or Bus Reference Voltage Signal
20 or wider
20 or wider
Power 30 or wider 20 or wider
Table 4: Recommended trace width and spacing
General rules for minimizing crosstalk in high-speed bus designs are listed below:
•Maximize the distance between traces. Maintain 10 mils minimum spaces between traces
wherever possible.
•Maximize the distance (30 mils minimum) between two adjacent routing areas of different signal
groups wherever possible.
•Avoid parallelism between traces on adjacent layers.
•Select a board stack-up that minimizes coupling between adjacent traces.
2.2.3. General Clock Routing Considerations
Clock routing guidelines are listed below:
•The recommended clock trace width is 5 mils.
•The minimum space between one clock trace and adjacent clock traces is 20 mils. The minimum
space from one segment of a clock trace to other segments of the same clock trace is at least
two times of the clock width. That is, more space is needed from one clock trace to others or its
own trace to avoid signal coupling (see Figure 7).
•Clock traces should be parallel to their reference ground planes. That is, a clock trace should be
right beneath or on top of its reference ground plane (see Figure 8).
•Series terminations (damping resistors) are needed for all clock signals (typically 0 to 47 ohm Ω).
When two loads are driven by one clock signal, the series termination layout is shown in Figure 9.
When multiple loads (more than two) are applied, a clock buffer solution is preferred.
•Isolating clock synthesizer power and ground planes through ferrite beads or narrow channels
(typically 20 mils to 50 mils wide) is preferred.
•No clock traces on the internal layer if a six-layer board is used.
clock
segment
clock
synthesizer
clock trace
20 mils
at least two times
of the width of the
clock segment
Figure 7: Suggested clock trace spacing

Carrier Board Design Guide for VIA QSM-8Q60
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another ground plane
clock trace
relative ground plane
Recommended
another ground plane
clock trace
relative ground plane
NOT recommended
Figure 8: Clock trace layout in relation to the ground plane
in equal length
clock source
damping resistors
in equal length
clock load
clock load
Figure 9: Series termination for multiple clock loads

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3. Qseven Specification Overview
The carrier board for VIA QSM-8Q60 module must follow the placement defined in the Qseven
specification.
3.1. Qseven Module Placement
Figure 10 shows a depiction of the top view of 3.5” SBC form factor carrier board PCB with appropriate
amount of space reserved for the Qseven module (VIA QSM-8Q60).
70mm
70mm
2.5mm
18mm
13.5mm
3mm
3.95mm
Carrier Board PCB
Figure 10: Qseven module placement on carrier board PCB
3.2. Qseven Mechanical Characteristics
Heatsink
MXM connector
Carrier Board PCB
Qseven module (QSM-8Q60)
Hex spacer
Screw
Figure 11: Carrier board with Qseven module installed
1.8mm
1.6mm
2mm (heatsink base plate
7.8mm
5mm
5mm
Figure 12: Qseven module and carrier board height distribution

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3.3. VIA QSM-8Q60 Module and Carrier Board Dimensions
The mechanical dimensions of the QSM-Q860module and reference carrier board (QSMDB2) are shown
below.
70mm
70mm
5mm 5.1mm
64.9mm
18mm
2.5mm
70mm
3mm
52mm
54.53mm
3.95mm
62.11mm
2.69mm
Figure 13: Dimensions of the VIA QSM-8Q60 module (top view)
QSMDB2
137.19mm
95.24mm
3mm
102mm
3.68mm
146mm
5mm
Figure 14: Dimensions of the carrier board (top view)

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3.4. MXM Connector
The MXM connector can handle high-speed signals and comprises of 230-pins to connect the VIA QSM-
8Q60 module.
Table 5 shows the specification of MXM connector with 7.8mm height.
Part Number
Resulting height between
Qseven module and carrier board
Height
Vendor
AS0B326-S78N-7F
5mm
7.8mm
Foxconn
Table 5: MXM connector sample
3.4.1. MXM Connector Dimensions
0.5mm
51mm
5.5mm
1.42mm
2.08mm
Pin no. 229
69mm
Pin no. 1 Pitch
Pin no. 2
5.5mm
1.16mm
2.32mm
51mm
Pin no. 230
0.15mm
Figure 15: Dimensions of the MXM connector (top view)
5mm
30
MXM Card Module
1.2mm
7.8mm
Figure 16: Dimensions of the MXM connector (side view)

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3.4.2. MXM Connector Footprint
5.5mm
3.5mm
51mm
0.5mm
(Pitch) Pin no. 229
0.36mm
Pin no. 1
1.1mm
5.5mm
3.5mm
0.61mm
51mm
61.5mm
Pin no. 2
68.12mm
Pin no. 230
0.30mm
Connector outline
1.6mm
5.15mm (2X)
3mm (2X)
2.0mm
2.5mm
0.98mm
Figure 17: Carrier board PCB footprint for the MXM connector
3.4.3. VIA QSM-8Q60 Module and MXM Connector Footprint
Carrier BoardPCB
Figure 18: PCB footprint for Qseven module inserted in the MXM connector on the carrier board

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3.5. MXM Connector Pinouts
The MXM connector is used for connecting the VIA QSM-8Q60 module to the Qseven carrier board. The
MXM connector is consists of 230-pins. The pinout of the MXM connector is shown below.
Pin#
Pin Name
Signal
Pin#
Pin Name
Signal
1
GND
GND
2
GND
GND
3 GBE_MDI3- TXRXM_D 4 GBE_MDI2- TXRXM_C
5 GBE_MDI3+ TXRXP_D 6 GBE_MDI2+ TXRXP_C
7
GBE_LINK100-
NC
8
GBE_LINK1000-
NC
9 GBE_MDI1- TXRXM_B 10 GBE_MDI0- TXRXM_A
11 GBE_MDI1+ TXRXP_B 12 GBE_MDI0+ TXRXP_A
13
GBE_LINK#
LED2_LINK-
14
GBE_ACT#
LED1_ACT-
15
GBE_CTREF
NC
16
SUS_S5#
GPIO_19_PLED
17 WAKE- NC 18 SUS_S3- USB_OTG_PWR_EN
19
SUS_STAT-
NC
20
PWRBTN-
NC
21
SLP_BTN-
NC
22
LID_BTN-
NC
23 GND GND 24 GND GND
25
GND
GND
26
PWGIN
NC
27
BATLOW-
NC
28
RSTBTN#
RESET_N
29 SATA0_TX+ SATA0_TX+ 30 SATA1_TX+ UART3_RX
31
SATA0_TX-
SATA0_TX-
32
SATA1_TX-
UART3_TX
33
SATA_ACT-
SATA_ACT-
34
GND
GND
35 SATA0_RX+ SATA0_RX+ 36 SATA1_RX+ UART3_-CTS
37 SATA0_RX- SATA0_RX- 38 SATA1_RX- UART3_-RTS
39
GND
GND
40
GND
GND
41 BIOS_DISABLE-
/BOOT_ALT-
NC 42 SDIO_CLK- SD1_CLK
43 SDIO_CD- SD1_CD- 44 SDIO_LED SD1_LED
45
SDIO_CMD
SD1_CMD
46
SDIO_WP
SD1_WP
47
SDIO_PWR-
SD1_PWR-
48
SDIO_DATA1
SD1_DATA1
49 SDIO_DATA0 SD1_DATA0 50 SDIO_DATA3 SD1_DATA3
51
SDIO_DATA2
SD1_DATA2
52
SDIO_DATA5
SD1_DATA5
53
SDIO_DATA4
SD1_DATA4
54
SDIO_DATA7
SD1_DATA7
55 SDIO_DATA6 SD1_DATA6 56 RSVD NC
57
GND
GND
58
GND
GND
59 HDA_SYNC
/I2S_WS
AUD4_TXFS 60 SMB_CLK
/GP1_I2C_CLK
UART2_RX
61 HDA_RST#
/I2S_RST#
GPIO_0_CLKO 62 SMB_DAT
/GP1_I2C_DAT
UART2_TX
63 HDA_BITCLK
/I2S_CLK
AUD4_TXC 64 SMB_ALERT- NC
65 HDA_SDI
/I2S_SDI
AUD4_TXD 66 GP0_I2C_CLK I2C3_SCL
67 HDA_SDO
/I2S_SDO
AUD4_RXD 68 GP0_I2C_DAT I2C3_SDA
69
THRM-
NC
70
WDTRIG-
NC
71 THRMTRIP- NC 72 WDOUT WDOG_B
73 GND GND 74 GND GND
75 USB_P7-
/USB_SSTX0-
NC 76 USB_P6-/USB_SSRX0- NC
77 USB_P7-
/USB_SSTX0+
NC 78 USB_P6-/USB_SSRX0+ NC
79 USB_6_7_OC- NC 80 USB_4_5_OC# USB_4_OC

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81 USB_P5-
/USB_SSTX1-
NC 82 USB_P4-/USB_SSRX1- USBD_T4-
83 USB_P5-
/USB_SSTX1+
NC 84 USB_P4-/USB_SSRX1+ USBD_T4+
85
USB_2_3_OC#
USB_2_3_OC
86
USB_0_1_OC#
USB_0_OTG_OC
87 USB_P3- USBD_T3- 88 USB_P2- USBD_T2-
89
USB_P3+
USBD_T3+
90
USB_P2+
USBD_T2+
91
USB_CC
NC
92
USB_ID
USBD_OTG_ID
93 USB_P1- OTG_USBD_T1- 94 USB_P0- USBD_T0-
95
USB_P1+
OTG_USBD_T1+
96
USB_P0+
USBD_T0+
97
GND
GND
98
GND
GND
99 eDP0_TX0+
/LVDS_A0+
LVDS0_TX0_P 100 eDP1_TX0+
/LVDS_B0+
LVDS1_TX0_P
101 eDP0_TX0-
/LVDS_A0-
LVDS0_TX0_N 102 eDP1_TX0-
/LVDS_B0-
LVDS1_TX0_N
103 eDP0_TX1+
/LVDS_A1+
LVDS0_TX1_P 104 eDP1_TX1+
/LVDS_B1+
LVDS1_TX1_P
105 eDP0_TX1-
/LVDS_A1-
LVDS0_TX1_N 106 eDP1_TX1-
/LVDS_B1-
LVDS1_TX1_N
107 eDP0_TX2+
/LVDS_A2+
LVDS0_TX2_P 108 eDP1_TX2+
/LVDS_B2+
LVDS1_TX2_P
109 eDP0_TX2-
/LVDS_A2-
LVDS0_TX2_N 110 eDP1_TX2-
/LVDS_B2-
LVDS1_TX2_N
111 LVDS_PPEN LVDS_PPEN 112 LVDS_BLEN LVDS_BLEN
113 eDP0_TX3+
/LVDS_A3+
LVDS0_TX3_P 114 eDP1_TX3+
/LVDS_B3+
LVDS1_TX3_P
115 eDP0_TX3-
/LVDS_A3-
LVDS0_TX3_N 116 eDP1_TX3-
/LVDS_B3-
LVDS1_TX3_N
117 GND GND 118 GND GND
119 eDP0_AUX+
/LVDS_A_CLK+
LVDS0_CLK_P 120 eDP1_AUX+
/LVDS_B_CLK+
LVDS1_CLK_P
121 eDP0_AUX-
/LVDS_A_CLK-
LVDS0_CLK_N 122 eDP1_AUX-
/LVDS_B_CLK-
LVDS1_CLK_N
123 LVDS_BLT_CTRL
/GP_PWM_OUT0
LVDS_PWM2 124 GP_1-Wire_Bus NC
125 GP2_I2C_DAT
/LVDS_DID_DAT
I2C1_SDA 126 eDP0_HPD#
/LVDS_BLC_DAT
USB_0_2_3_4_EN
127 GP2_I2C_CLK
/LVDS_DID_CLK
I2C1_SCL 128 eDP1_HPD#
/LVDS_BLC_CLK
HDMI_CEC_IN
129
CAN0_TX
CAN_TX1
130
CAN0_RX
CAN_RX1
131 DP_LANE3+
/TMDS_CLK+
HDMI_CLKP 132 RSVD(Differential) TP_2
133 DP_LANE3-
/TMDS_CLK-
HDMI_CLKM 134 RSVD(Differential) TP_3
135
GND
GND
136
GND
GND
137 DP_LANE1+
/TMDS_LANE1+
HDMI_D1P 138 DP_AUX+ NC
139 DP_LANE1-
/TMDS_LANE1-
HDMI_D1M 140 DP_AUX- NC
141
GND
GND
142
GND
GND
143 DP_LANE2+
/TMDS_LANE0+
HDMI_D0P 144 RSVD(Differential) NC
145 DP_LANE2-
/TMDS_LANE0-
HDMI_D0M 146 RSVD(Differential) NC
147
GND
GND
148
GND
GND