VIA Technologies SOM-9X35 Guide

DESIGN GUIDE
Carrier Board
for SOM-9X35 Module
1.00-18012022

Copyright
Copyright ©2022 VIA Technologies Incorporated. All rights reserved.
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Carrier Board Design Guide for SOM-9X35 Module
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Revision History
Revision Date Descripon
1.00 18/01/2022 Inial release

Carrier Board Design Guide for SOM-9X35 Module
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Table of Contents
1. Introducon.................................................................................................................................................... 1
1.1 Document Overview ............................................................................................................................. 1
1.2 Acronyms Used ..................................................................................................................................... 2
1.3 I/O Parameter Denions..................................................................................................................... 3
1.4 Schemac Convenons......................................................................................................................... 3
2. General Carrier Board Recommendaons ..................................................................................................... 4
2.1 PCB Stack-Up......................................................................................................................................... 4
2.1.1 6-Layer PCB Stack-up Example ...................................................................................................... 5
2.1.2 Impedance Requirements.............................................................................................................. 5
2.2 General Layout & Roung Guidelines ................................................................................................... 6
2.2.1 General Layout & Roung Guidelines ........................................................................................... 6
2.2.2 General Trace Aribute Recommendaon .................................................................................... 7
2.2.3 General Clock Roung Consideraons........................................................................................... 8
2.2.4 Trace Bend Geometry .................................................................................................................... 9
2.2.5 Signal Proximity ............................................................................................................................. 9
2.2.6 Trace Stubs................................................................................................................................... 10
2.2.7 Ground Planes Under Pads .......................................................................................................... 10
2.2.8 Dierenal Pair Signals ................................................................................................................ 11
2.2.9 Length Matching.......................................................................................................................... 11
3. SOM-9X35 Module & M.2 Slot Specicaon Overview ............................................................................... 15
3.1 SOM-9X35 Module Placement ........................................................................................................... 15
3.2 SOM-9X35 Module & Carrier Board Dimensions ............................................................................... 16
3.3 M.2 Slot .............................................................................................................................................. 17
3.3.1 M.2 Slot Dimensions ................................................................................................................... 17
3.3.2 M.2 Slot Height Notes ................................................................................................................. 18
3.3.3 M.2 Slot Placement (unit mm)..................................................................................................... 18
3.4 M.2 Slot Pin Assignments................................................................................................................... 18
3.4.1 M.2 Slot Reference Schemacs.................................................................................................... 28
4. Layout & Roung Recommendaon............................................................................................................. 30
4.1 HDMI Interface ................................................................................................................................... 30
4.1.1 HDMI Signal Denion................................................................................................................. 30
4.1.2 HDMI Layout & Roung Recommendaons ................................................................................ 31
4.1.3 HDMI Reference Schemacs ....................................................................................................... 32
4.2 MIPI DSI Interface .............................................................................................................................. 34
4.2.1 MIPI DSI Signal Denion ............................................................................................................ 34
4.2.2 MIPI DSI Layout & Roung Recommendaons............................................................................ 35
4.2.3 MIPI DSI Reference Schemacs ................................................................................................... 36
4.2.4 LCD Backlight & Bias Voltage Reference Schemacs ................................................................... 37
4.3 LVDS Interface .................................................................................................................................... 37
4.3.1 LVDS Signal Denion.................................................................................................................. 37
4.3.2 LVDS Reference Schemacs ......................................................................................................... 40
4.4 MIPI CSI Interface ............................................................................................................................... 41
4.4.1 MIPI CSI Signal Denion ............................................................................................................ 41

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4.4.2 MIPI CSI Layout & Roung Recommendaons ............................................................................ 42
4.4.3 MIPI CSI Reference Schemacs ................................................................................................... 45
4.5 USB Interface ...................................................................................................................................... 48
4.5.1 USB Signal Denion ................................................................................................................... 48
4.5.2 USB Layout & Roung Recommendaons .................................................................................. 49
4.5.3 USB Reference Schemacs........................................................................................................... 50
4.6 SDC Interface ...................................................................................................................................... 52
4.6.1 SDC Signal Denion ................................................................................................................... 52
4.6.2 SDC Layout & Roung Recommendaons .................................................................................. 52
4.6.3 SDC Reference Schemacs........................................................................................................... 54
4.7 Analog Audio Interface ...................................................................................................................... 54
4.7.1 Analog Audio Signal Denion ................................................................................................... 54
4.7.2 PCB Layout Requirement ............................................................................................................. 55
4.7.3 Schemacs Requirement ............................................................................................................. 55
4.7.4 Audio Analog Reference Schemacs............................................................................................ 56
4.8 GPIO Interface .................................................................................................................................... 58
4.8.1 GPIO Signal Denion ................................................................................................................. 58
4.8.2 GPIO Extender ............................................................................................................................. 59
4.9 ADC Interface ..................................................................................................................................... 59
4.9.1 ADC Signal Denion ................................................................................................................... 59
4.9.2 ADC Design Notes ........................................................................................................................ 59
4.10 System Boot Interface ........................................................................................................................ 60
4.10.1 System Boot Signal Denion...................................................................................................... 60
4.10.2 System Boot Design Notes........................................................................................................... 60
4.10.3 System Boot Reference Schemacs............................................................................................. 61
4.11 PWM Interface ................................................................................................................................... 61
4.11.1 PWM Signal Denion................................................................................................................. 61
4.11.2 PWM Design Notes ...................................................................................................................... 61
4.12 I2C Interface ....................................................................................................................................... 62
4.12.1 I2C Signal Denion..................................................................................................................... 62
4.12.2 I2C Design Notes.......................................................................................................................... 62
4.13 UART & SPI Interface........................................................................................................................... 63
4.13.1 UART & SPI Signal Denion........................................................................................................ 63
4.13.2 UART & SPI Design Notes............................................................................................................. 64
4.14 MCU Interface .................................................................................................................................... 65
4.14.1 MCU Signal Denion.................................................................................................................. 65
4.14.2 MCU Design Notes....................................................................................................................... 65
4.14.3 MCU Reference Schemacs ......................................................................................................... 65
4.14.4 MCU GPIO List.............................................................................................................................. 66
4.15 Buon Interface.................................................................................................................................. 67
4.15.1 Buon Signal Denion ............................................................................................................... 67
4.15.2 Buon Design Notes .................................................................................................................... 68
4.16 Power Manage Interface..................................................................................................................... 69
4.16.1 Power Manage Signal Denion.................................................................................................. 69
4.16.2 Power Manage Design Notes....................................................................................................... 69
4.17 Gas Gauge Interface............................................................................................................................ 69

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4.17.1 Gas Gauge Signal Denion......................................................................................................... 69
4.17.2 Gas Gauge Design Notes.............................................................................................................. 70

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List of Figures
Figure 01: Schemac convenons......................................................................................................................... 3
Figure 02: Microstrip PCB stack-up example ......................................................................................................... 4
Figure 03: Stripline PCB stack-up example ............................................................................................................ 4
Figure 04: 6-Layer PCB board stack-up detail ........................................................................................................ 5
Figure 05: Point-to-point and mul-drop examples ............................................................................................. 6
Figure 06: Daisy-chain example............................................................................................................................. 6
Figure 07: Alternate mul-drop example .............................................................................................................. 6
Figure 08: Single-ended trace width and spacing example ................................................................................... 7
Figure 09: Dierenal trace width and spacing example ...................................................................................... 7
Figure 10: Suggested clock trace spacing .............................................................................................................. 8
Figure 11: Clock trace layout in relaon to the ground plane ............................................................................... 8
Figure 12: Series terminaon for mulple clock loads .......................................................................................... 8
Figure 13: Use 135° bends instead of 90°.............................................................................................................. 9
Figure 14: Suggested minimum distance and segment length at bends ............................................................... 9
Figure 15: Try to increase spacing between traces whenever it is possible .......................................................... 9
Figure 16: Avoid stub traces by daisy chain roung ............................................................................................ 10
Figure 17: Remove ground plane under large pads............................................................................................. 10
Figure 18: Do not put any components or vias between dierenal pairs ......................................................... 11
Figure 19: Place vias symmetrical........................................................................................................................ 11
Figure 20: Route pairs on the same layer, place same amount of vias................................................................ 11
Figure 21: Route pairs on the same layer, place same amount of vias................................................................ 12
Figure 22: Add length correcon to the mismatching point................................................................................ 12
Figure 23: Place length compensaon close to a bend ....................................................................................... 12
Figure 24: Length dierences need to be compensated in each segment .......................................................... 13
Figure 25: Pairs within same Interface should be routed preferable on same layer ........................................... 13
Figure 26: Preferred symmetrical breakout......................................................................................................... 13
Figure 27: Preferred breakout of dierenal pairs.............................................................................................. 14
Figure 28: SOM-9X35 module placement example on the carrier board............................................................ 15
Figure 29: Dimensions of the SOM-9X35 module ............................................................................................... 16
Figure 30: Dimensions of the reference carrier board ........................................................................................ 16
Figure 31: Dimensions of the M.2 slot (top view) ............................................................................................... 17
Figure 32: Dimensions of the M.2 slot (side view) .............................................................................................. 17
Figure 33: M.2 slot placement............................................................................................................................. 18
Figure 34: M.2 slot reference circuitry (part 1) ................................................................................................... 28
Figure 35: M.2 slot reference circuitry (part 2) ................................................................................................... 29
Figure 36: M.2 slot reference circuitry (part 3) ................................................................................................... 29
Figure 37: HDMI roung topology....................................................................................................................... 30
Figure 38: HDMI dierenal trace width and spacing example .......................................................................... 31
Figure 39: HDMI single-ended trace width and spacing example ....................................................................... 31
Figure 40: HDMI reference circuitry (Part 1) ....................................................................................................... 32
Figure 41: HDMI reference circuitry (Part 2) ....................................................................................................... 33
Figure 42: HDMI reference circuitry (Part 3) ....................................................................................................... 33
Figure 43: MIPI DSI roung topology .................................................................................................................. 34
Figure 44: MIPI DSI dierenal trace width and spacing example ...................................................................... 35
Figure 45: MIPI DSI reference circuitry................................................................................................................ 36
Figure 46: LCD backlight & bias voltage reference circuitry ................................................................................ 37
Figure 47: LVDS roung topology ........................................................................................................................ 38
Figure 48: LVDS dierenal trace width and spacing example............................................................................ 38
Figure 49: LVDS reference circuitry...................................................................................................................... 40
Figure 50: MIPI CSI roung topology................................................................................................................... 42
Figure 51: MIPI CSI dierenal trace width and spacing example ...................................................................... 42
Figure 52: Camera main clock oscillator reference circuitry................................................................................ 45
Figure 53: Camera I2C Bus level shi reference circuitry .................................................................................... 46
Figure 54: Camera control pin level shi reference circuitry............................................................................... 46
Figure 55: Camera power control reference circuitry.......................................................................................... 47
Figure 56: MIPI 4-lane camera reference circuitry (Part 1).................................................................................. 47

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Figure 57: MIPI 4-lane camera reference circuitry (Part 2).................................................................................. 48
Figure 58: USB roung topology.......................................................................................................................... 48
Figure 59: USB dierenal trace width and spacing example ............................................................................. 49
Figure 60: USB Port0 reference circuitry ............................................................................................................. 50
Figure 61: USB Port1 reference circuitry (Part1) ................................................................................................. 51
Figure 62: USB Port1 reference circuitry (Part2) ................................................................................................. 51
Figure 63: SDC roung topology.......................................................................................................................... 52
Figure 64: SDC single-ended trace width and spacing example .......................................................................... 53
Figure 65: SDC reference circuitry ....................................................................................................................... 54
Figure 66: Audio bias voltage LDO reference circuitry ........................................................................................ 55
Figure 67: On-board MIC reference circuitry....................................................................................................... 56
Figure 68: Line-out & MIC-in jack reference circuitry.......................................................................................... 56
Figure 69: Speaker connector reference circuitry ............................................................................................... 57
Figure 70: Class-D amplier reference circuitry .................................................................................................. 57
Figure 71: GPIO level shi reference circuitry ..................................................................................................... 58
Figure 72: GPIO expander reference circuitry ..................................................................................................... 59
Figure 73: ADC reference circuitry....................................................................................................................... 60
Figure 74: SOM-9X35 power switch reference circuitry...................................................................................... 61
Figure 75: SOM-9X35 BATSNS reference circuitry ............................................................................................... 61
Figure 76: SOM-9X35 PWM level shi reference circuitry .................................................................................. 62
Figure 77: SOM-9X35 I2C level shi IC reference circuitry .................................................................................. 63
Figure 78: SOM-9X35 I2C level shi reference circuitry ...................................................................................... 63
Figure 79: SOM-9X35 I2C level shi IC reference circuitry .................................................................................. 64
Figure 80: SOM-9X35 MCU IC reference circuitry ............................................................................................... 65
Figure 81: SOM-9X35 MCU power supply reference circuitry............................................................................. 66
Figure 82: SOM-9X35 MCU ash connector reference circuitry.......................................................................... 66
Figure 83: SOM-9X35 reset buon reference circuitry........................................................................................ 68
Figure 84: SOM-9X35 download buon reference circuitry................................................................................ 68
Figure 85: SOM-9X35 power buon reference circuitry ..................................................................................... 68
Figure 86: SOM-9X35 baery leakage protect reference circuitry ...................................................................... 70
Figure 87: SOM-9X35 gas gauge current sense reference circuitry ..................................................................... 70
Figure 88: 2:1 voltage divided voltage following reference circuitry................................................................... 71

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List of Table
Table 01: Acronyms used ..................................................................................................................................... 2
Table 02: I/O parameter denions..................................................................................................................... 3
Table 03: Impedance requirements ..................................................................................................................... 5
Table 04: Recommended trace width and spacing .............................................................................................. 7
Table 05: M.2 slot sample .................................................................................................................................. 17
Table 06: M.2 slot pinouts.................................................................................................................................. 28
Table 07: HDMI signal denion........................................................................................................................ 30
Table 08: HDMI layout guidelines ...................................................................................................................... 31
Table 09: SOM-9X35 HDMI trace & via delay..................................................................................................... 32
Table 10: MIPI DSI signal denion.................................................................................................................... 34
Table 11: MIPI DSI layout guidelines.................................................................................................................. 35
Table 12: SOM-9X35 MIPI DSI trace & via delay ................................................................................................ 36
Table 13: LVDS signal denion ......................................................................................................................... 38
Table 14: LVDS layout guidelines........................................................................................................................ 39
Table 15: SOM-9X35 LVDS trace & via delay ...................................................................................................... 39
Table 16: MIPI CSI0 signal denion.................................................................................................................. 41
Table 17: MIPI CSI1 signal denion.................................................................................................................. 42
Table 18: MIPI CSI layout guidelines .................................................................................................................. 43
Table 19: SOM-9X35 MIPI CSI0 4-lane trace & via delay.................................................................................... 43
Table 20: SOM-9X35 MIPI CSI0A 2-lane trace & via delay.................................................................................. 44
Table 21: SOM-9X35 MIPI CSI0B 2-lane trace & via delay.................................................................................. 44
Table 22: SOM-9X35 MIPI CSI1 4-lane trace & via delay.................................................................................... 45
Table 23: USB signal denion........................................................................................................................... 48
Table 24: USB layout guidelines ......................................................................................................................... 49
Table 25: USB port0 OTG.................................................................................................................................... 49
Table 26: USB port0 Host/Device....................................................................................................................... 49
Table 27: USB Port0 trace & via delay................................................................................................................ 50
Table 28: USB Port1 trace & via delay................................................................................................................ 50
Table 29: SDC signal denion........................................................................................................................... 52
Table 30: SDC layout guidelines ......................................................................................................................... 53
Table 31: SOM-9X35 SDC trace & via delay........................................................................................................ 53
Table 32: Analog audio signal denion ............................................................................................................ 54
Table 33: SOM-9X35 GPIO signal denion....................................................................................................... 58
Table 34: SOM-9X35 ADC signal denion ........................................................................................................ 59
Table 35: SOM-9X35 system boot signal denion............................................................................................ 60
Table 36: SOM-9X35 PWM signal denion ...................................................................................................... 61
Table 37: SOM-9X35 I2C signal denion .......................................................................................................... 62
Table 38: SOM-9X35 UART & SPI signal denion ............................................................................................. 64
Table 39: SOM-9X35 MCU signal denion ....................................................................................................... 65
Table 40: SOM-9X35 MCU GPIO list................................................................................................................... 67
Table 41: SOM-9X35 buon signal denion .................................................................................................... 67
Table 42: SOM-9X35 power management signal denion............................................................................... 69
Table 43: SOM-9X35 power management status............................................................................................... 69
Table 44: SOM-9X35 gas gauge signal denion................................................................................................ 69

Carrier Board Design Guide for SOM-9X35 Module
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1. Introducon
This document provides design guidelines and rule recommendaons for the developers of a carrier board that
supports the features of VIA SOM-9X35 module. This document includes the layout and roung guidelines for
general board designs and major underlying interfaces (ex. MIPI, LVDS, HDMI, USB). In addion, the document
includes the placement and mechanical informaon on the M.2 slot which is used to provide high-speed
interfaces between the carrier board and the SOM-9X35 module.
Please note that this document is considered to be a reference guide only. This document is not intended to be
a specicaon. All informaon and examples listed below are considered to be accurate as of the publicaon
date. However, developers must be aware that this document is only a reference guide.
1.1 Document Overview
A brief descripon of each chapter is given below.
Chapter 1: Introducon
This chapter briey introduces the structure of the design guide document.
Chapter 2: General Carrier Board Recommendaons
The general design schemes and recommended layout rules are shown in this chapter.
Chapter 3: SOM-9X35 Module and M.2 Slot Specicaon Overview
Detailed informaon about the SOM-9X35 module and M.2 slot placement and dimensions are described in
this chapter.
Chapter 4: Layout and Roung Recommendaons
Detailed layout and roung guidelines for each major interface are described in this chapter.

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1.2 Acronyms Used
Term Descripon
ADC Analog to Digital Converter
AMIC Analog Microphone Jack
ASIC Applicaon-specic Integrated Circuit
BAM Bus Access Manager/Module
BLSP BAM Low Speed Peripheral
BMS Baery Management System
CMOS Complementary Metal Oxide Semiconductor
CSI Camera Serial Interface
CTP Capacitance Touch Panel
DIO Digital Input /Output
DMIC Digital Microphone Jack
DSI Display Serial Interface
EMI Electromagnec Interference
ESD Electrostac-discharge
GPIO General Purpose Input/Output
HDMI High-Denion Mulmedia Interface
I/O Input/Output
I2C Inter-IC
IC Integrated Circuit
LCD Liquid-Crystal Display
LVDS Low-Voltage Dierenal Signaling
M.2 Next Generaon Form Factor
MIPI Mobile Industry Processor Interface
MMC Mul Media Card
NVMe Non Volale Memory Host Controller Interface Specicaon
P2P Point-to-Point
PCB Printed Circuit Board
PCIe Peripheral Component Interconnect Express
PMIC Power Management Integrated Circuit
PWM Pulse Width Modulaon
RTC Real Time Clock
SD Secure Digital Memory Card
SDC Secure Digital Controller
SIM Subscriber Identy Module
SMPS Switched-mode Power Supply
SOM System-On-Module
SPI Serial Peripheral Interface
UART Universal Asynchronous Receiver-Transmier
USB Universal Serial Bus
Table 01: Acronyms used

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1.3 I/O Parameter Denions
Symbol Descripon
Pad aribute
AI Analog Input (does not include the pad circuitry)
AO Analog Output (does not include the pad circuitry)
BBidireconal digital with CMOS input
DI Digital Input (CMOS)
DO Digital Output (CMOS)
HHigh-Voltage tolerant
SSchmi trigger input
ZHigh-impedance (high-Z) output
Pad pull details for digital I/O
nppdpukp Programmable pull resistor. The default pull direcon is indicated using capital
leers and is a prex to other programmable opons:
NP:pdpukp = default no-pull with programmable opons following the colon (:)
PD:nppukp = default pull-low (pull-down) with programmable opons following
the colon (:)
PU:nppdkp = default pull-high (pull-up) with programmable opons following the
colon (:)
KP:nppdpu = default keeper with programmable opons following the colon (:)
KP Contains an internal weak keeper device (keepers cannot drive external buses)
NP Contains no internal pull
PU Contains an internal pull-high device
PD Contains an internal pull-low device
Table 02: I/O parameter denions
1.4 Schemac Convenons
The reference schemacs depicted in this document show the direconal ows of the signals. Direconal ow
is indicated by the pointed ends of the arrow shapes.
Bidirec�onal signal flow
IC/Connector
Input signal flow
Output signal flow
Figure 01: Schemac convenons

Carrier Board Design Guide for SOM-9X35 Module
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2. General Carrier Board Recommendaons
This secon contains general guidelines for the PCB stack-up and the layout of traces. The general guide lines
for roung style, topology, and trace aribute recommendaons are also discussed.
2.1 PCB Stack-Up
The PCB stack-up consists of signal layers and reference (power and ground) layers. The signal layers are
referred to as the component layer (top), inner layer and solder layer (boom).
The carrier board designers can choose between two basic categories of PCB stack-up design: micro strip and
strip line. Microstrip designs have the outer signal layers exposed while stripline designs have the outermost
signal layers shielded by reference layers.
The following gures show examples of microstrip and stripline designs.
Microstrip Stack-Up Design
Signal layers
Reference layers
Component layer
Ground layer
Inner layer
Power layer
Ground layer
Solder layer
Figure 02: Microstrip PCB stack-up example
Stripline Stack-Up Design
Signal layers
Reference layers
Inner layer
Ground layer
Inner layer
Power layer
Ground layer
Inner layer
Figure 03: Stripline PCB stack-up example
The choice of microstrip or stripline design depends on the applicaon for which the carrier board is being
designed. If the carrier board is being designed for locaons where sensivity to EMI is an issue, a stripline
design is recommended for reducing EMI and noise coupling. For applicaons where the tolerance for EMI
levels is greater, a microstrip design is recommended to reduce costs. Due to the inherent nature of stripline
PCB stacks, broad-side coupling is possible.

Carrier Board Design Guide for SOM-9X35 Module
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2.1.1 6-Layer PCB Stack-up Example
The following gure shows the recommended 6-layer PCB stack-up design for the carrier board of the VIA SOM-
9X35 module.
Core = 4.0mil (Er = 4.1)
PP =4.3 (Er = 4.2)
Solder mask = 0.4mil (Er=3.5)
Pla�ng = 0.8mil
LAYER 1
LAYER 2
LAYER 3
LAYER 4
63.4mil
TOP = 0.5oz (0.8mil) Copper foil + Plang
GROUND1 = 1.0oz (1.2mil) Copper foil
PP = 42mil (Er =4.4)
(adjustable)
INNER1 = 1.0oz (1.2mil) Copper foil + Plang
Core = 4.0mil (Er = 4.1)
PP = 4.3mil (Er = 4.2mil)
LAYER 5
LAYER 6
GROUND2=1.0oz (1.2mil) Copper foil
BOTTOM = 0.5 oz (0.8mil)
Solder mask = 0.4mil (Er = 3.5)
Pla�ng = 0.8mil
Copper foil + Plang
INNER2 = 1.0oz (1.2mil) Copper foil
Figure 04: 6-Layer PCB board stack-up detail
2.1.2 Impedance Requirements
Funcon Type Other
Signal USB MIPI DSI MIPI CSI HDMI LVDS Ethernet
Trace Type Single-
ended Dierenal Dierenal Dierenal Dierenal Dierenal Dierenal
Required value 50Ω 90Ω 100Ω 100Ω 100Ω 100Ω 100Ω
Trace & Spacing (mil)
(W:S:W)
Micro strip
76.1 : 5.6 :
6.1
5.6: 8.3 :
5.6
5.6: 8.3 :
5.6
5.6: 8.3 :
5.6
5.6: 8.3 :
5.6
5.6: 8.3 :
5.6
Trace & Spacing (mil)
(W:S:W)
Strip line
54.4 : 6.4 :
4.4
3.9 : 9.1 :
3.9
3.9 : 9.1 :
3.9
3.9 : 9.1 :
3.9
3.9 : 9.1 :
3.9
3.9 : 9.1 :
3.9
Table 03: Impedance requirements

Carrier Board Design Guide for SOM-9X35 Module
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2.2 General Layout & Roung Guidelines
This secon provides general layout rules and roung guidelines for designing carrier boards for the SOM-9X35
module.
2.2.1 General Layout & Roung Guidelines
Topology is the physical connecvity of a net or a group of nets. There are two types of topologies for a carrier
board layout: point-to-point (P2P) and mul-drop. An example of these topologies is shown in Figure 5.
Figure 05: Point-to-point and mul-drop examples
High-speed bus signals are sensive to transmission line stubs, which can result in ringing on the rising edge
caused by the high impedance of the output buer in the high state. In order to maintain beer signal quality,
transmission stubs should be kept as short as possible (less than 1.5”). Therefore, daisy chain style roung is
strongly recommended for these signals. Figure 6 below shows an example of daisy chain roung.
Figure 06: Daisy-chain example
If daisy chain roung is not allowed in some circumstances, dierent roungs may be considered. An
alternave topology is shown in Figure 7. In this case, the branch point is somewhere between both ends. It
may be near the source or the loads, but being close to the load side is preferred. The separated traces should
be equal in length.
Figure 07: Alternate mul-drop example

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2.2.2 General Trace Aribute Recommendaon
A 5mil trace width and 15mil spacing are generally advised for most signal traces on a carrier board layout. To
reduce trace inductance, the minimum power trace width is recommended to be 30mil.
As a quick reference, the overall recommended trace width and spacing for dierent trace types are listed in
Table 4, and the recommended trace width and spacing for each signal group is shown in Chapter 4.
Trace Type Trace Width (mil) Spacing (mil)
Regular Signal 5 or wider 15 or wider
Interface or Bus Reference Voltage
Signal 20 or wider 20 or wider
Power 30 or wider 20 or wider
Table 04: Recommended trace width and spacing
General rules for minimizing crosstalk in high-speed bus designs are listed below:
• Maximize the distance between traces. Maintain 15mil minimum spaces between traces wherever
possible.
• Maximize the distance (30mil minimum) between two adjacent roung areas of dierent signal groups
wherever possible.
• Avoid parallelism between traces on adjacent layers.
• Select a board stack-up that minimizes coupling between adjacent traces.
S
Reference Plane
W
S
Signal
Figure 08: Single-ended trace width and spacing example
S1
S
S
Reference Plane
W W
Signal Signal
Figure 09: Dierenal trace width and spacing example
Note:
1. W: Trace width
2. S: The spacing to other traces
3. S1: Dierenal pair spacing

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2.2.3 General Clock Roung Consideraons
The clock roung guidelines are listed below:
• The recommended clock trace width is 5mil.
• The minimum space between one clock trace and adjacent clock traces is 20mil. The minimum space
from one segment of a clock trace to other segments of the same clock trace is at least two mes of
the clock width. That is, more space is needed from one clock trace to others or its own trace to avoid
signal coupling (see Figure 10).
• The clock traces should be parallel to their reference ground planes. That is, a clock trace should be right
beneath or on top of its reference ground plane (see Figure 11).
• The series terminaons (damping resistors) are needed for all clock signals (typically 0Ω to 47Ω). When
two loads are driven by one clock signal, the series terminaon layout is shown in Figure 12. When
mulple loads (more than two) are applied, a clock buer soluon is preferred.
• Isolang clock synthesizer power and ground planes through ferrite beads or narrow channels (typically
20mil to 50mil wide) is preferred.
• No clock traces on the internal layer if a 6-layer board is used.
Figure 10: Suggested clock trace spacing
Figure 11: Clock trace layout in relaon to the ground plane
Figure 12: Series terminaon for mulple clock loads

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2.2.4 Trace Bend Geometry
When roung high-speed signals, bends should be minimized. If bends are needed, use 135° bends instead of
90°.
Figure 13: Use 135° bends instead of 90°
Serpenne traces (also called meander) are oen needed when a certain trace length needs to be achieved.
For high-speed interfaces, if there is space available, it is suggested to keep a minimum distance of four mes
the trace width between adjacent copper in a single trace. If its space is ght such as LPDDR3 interface, keep
a minimum distance of two mes the trace width between adjacent copper in a single trace. The individual
segments of the bends should be at least 1.5 mes the trace width.
>4x trace width
>1.5x trace width
>1.5x trace
width
Figure 14: Suggested minimum distance and segment length at bends
2.2.5 Signal Proximity
A minimum distance is required in order to minimize crosstalk between high-speed signals traces. The level
of crosstalk depends on the distance between two traces and the length in which they are closely routed.
Somemes, bolenecks can force the roung of traces closer than to what is normally permied. Try to
minimize such areas and enlarge the distance between the signals outside the boleneck. If there is space
available, try to enlarge the distance between the high speed-signals (and between high-speed and low-speed
signals) even if the minimum trace separaon requirement has been met.
Figure 15: Try to increase spacing between traces whenever it is possible

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2.2.6 Trace Stubs
Long stub traces can act as antennas and therefore increase problems complying with EMC standards. Stub
traces can also produce reecons which negavely impacts signal integrity. Common sources for stubs are
pull-up or pull-down resistors on high-speed signals. If such resistors are required, route the signals as a daisy
chain.
Figure 16: Avoid stub traces by daisy chain roung
Vias can also act as stubs. For example, in a 6-layer board, when a signal changes from layer 1 to 3 by using a
via, the via creates a stub which reaches layer 6. Back-drilling the vias in order to avoid such stubs is a quite
expensive technology and one which is not supported by most PCB manufacturers. The only praccal soluon
is to reduce the number of vias in high-speed traces.
2.2.7 Ground Planes Under Pads
The impedance of a trace depends on its width and the distance between trace and reference plane. A wide
trace has lower impedance than a thin one with the same distance. The same eect also exists for connector
and component pads. A large pad has signicantly lower impedance than the trace which is connected to
the pad. This impedance disconnuity can cause reecons reduces signal integrity. Therefore, under large
connector and component pads, a plane obstruct should be placed. The area of the plane should be decided by
means of simulaon. In this case, an acve reference plane should be placed on another layer. This reference
plane's net should be same as the normal reference plane. This reference plane needs to be stched with vias
to the normal reference plane.
Reference Plane
(Layer 2)
Reference Plane
(Layer 2)
Signal Trace Signal Trace Signal Trace
L4
L3
L2
L1
Ac�ve Reverence for
Connector Pad on Layer 1 Reference Plane for Layer 1
Signal Trace
Signal Trace Signal Trace Signal Trace
L4
L3
L2
L1
Ac�ve Reverence for
Connector Pad on Layer 1
Reference Plane for Layer 1
Signal Trace
Reference Plane for Layer 4Reference Plane for Layer 4
Plane Obstruct
Figure 17: Remove ground plane under large pads

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2.2.8 Dierenal Pair Signals
It is not permied to place any components or vias between the dierenal pairs, even if the signals are routed
symmetrically. Components and vias between the pairs could lead to EMC compliance problems and create an
impedance disconnuity.
Figure 18: Do not put any components or vias between dierenal pairs
Vias introduce a huge disconnuity in impedance. Try to reduce the amount of placed vias to a minimum and
place the vias symmetrically.
Figure 19: Place vias symmetrical
In order to meet the impedance requirements of a dierenal pair, both signal traces need to be routed on the
same layer. Add the same amount of vias to the traces.
Figure 20: Route pairs on the same layer, place same amount of vias
2.2.9 Length Matching
High-speed interfaces have addional requirements regarding the me of arrival skew between dierent traces
and pairs of signals. For example, in a high-speed parallel bus, all data signals need to arrive within a me
period in order to meet the setup and hold me requirements of the receiver. The carrier board designer needs
to make sure that the permied skew is not exceeded. In order to meet this requirement, length matching is
required. Oen, the requirements are given as a maximum me skew.
Dierenal pair signals oen require a very ght delay skew between the posive and negave signal traces.
Therefore, length dierences need to be compensated for using serpennes (also called meanders). The
geometry of serpenne traces needs to be carefully chosen in order to reduce impedance disconnuity. The
following gure shows the requirements for ideal serpenne traces.