XDS 910 User manual

Xerox Data Systems
Reference Manual

XDS 910 BASIC INSTRUCTIONS
ICentral Processorsj
Vlnemonic Code Name Page Mnemonic Code Name Page
LOAD/STORE TEST/SKIP
LDA A, T 76 Load A from Memory SKG
A, T 73 Skip if A
Greater Than Memory
13
STA A, T
35
Store A in Memory
SKM A, T 70 Skip if A = Memory on B Mask 13
LDB A, T
75
Load B from Memory SKA A, T 72 Skip if A and M
Do Not
STB
A, T 36 Store B in Memory Compare
Ones
13
LDX
A, T
71
Load Index from Memory
SKN
A, T 53 Skip if Memory
Negative
14
STX
A, T 37 Store Index
in Memory
EAX A, T 77 Copy Effective Address into Index SHIFT
ARITHMETIC
RSH N, T
066 OOOXX
Right Shift AB
14
RCY
N, T
066 200XX Right
Cycle AB
14
ADD A, T 55
Add Memory to A
LSH N, T 067 OOOXX
Left Shift AB
15
MIN
A, T
61
Memory Increment
LCY
N, T 067200XX
Left Cycle AB 15
MDE A, T 60 Memory Decrement
NOD N, T
067 100XX Normalize, Decrement X
15
SUB
A, T 54
Subtract Memory from A
MUS
A, T 64 Multiply Step CONTROL
DIS A, T 65 Divide Step
10
HLT
00 Halt
15
NOP 20 No Operation
16
LOGICAL
EXU A, T 23 Execute Instruction in Memory
16
ETR A, T
14
Extract
10
BREA KPOINT TESTS
MRG A, T
16
Merge
10
EOR
A, T
17 Exclusive OR
11
BPT 1 04020400
Breakpoint No. 1 Test
16
BPT 2 04020200 Breakpoint No.2 Test 16
BPT 3 04020100
Breakpoint No.3 Test
16
REGISTER CHANGE
BPT 4 04020040 Breakpoint No.4 Test 16
RCH
46 Register
Change
11
XAB 04600000 Exchange A and B
11
OVERFLOW
BAC 046 10000 Copy Binto A, Clear B
11
OVT o40 20001 Overflow Test; Reset
16
ABC
046 20000 Copy A into
B, Clear A
11
ROV o0220001 Reset Overflow 16
CLR
046 30000
Clear AB
11
BRANCH
INTERRUPT
EIR
002 20002 Enable Interrupts 20
BRU A, T
01
Branch Unconditionally
12
DIR 00220004
Di sabl e Interrupts 20
BRX A, T
41
Increment Index and Branch
12
lET 04020004
Interrupt Enabled Test
20
BRM A, T 43 Mark Place and Branch
12
!DT
040 20002 Interrupt Disabled Test 20
BRR A, T
51
Retu rn Bronc h
12
AIR 002 20020
Arm Interrupts 21
Legend: A = address, *A = indirect address; T = tag field; N = number of shifts

XOS 910 COMPUTER
REFERENCE MANUAL
90 00 080
February 1970
Price: $3.25
Xerox Data Systems/70i South Aviation Bouievard/Ei Segundo, Caiifornia 90245
:91963-1970, Xerox Data Systems, Inc Printed in U.S.A

ii
REVISION
This publication, 90 00 08D, is a minor revision of the XDS 910 Computer Reference
Manual, 90 00 08C, dated April 1966. Changes to the previous edition are indi-
cated by a vertical line in the margin of the affected page.
RELATED PUBLICATIONS
Title
XDS SYMBOL and META-SYMBOL Reference Manual
XDS MONARCH Reference Manual
XDS 910/925 Programmed Operators Technical Manual
XDS 910/920 Computer EXAMINER Diagnostic System Technical
Manual
XDS FORTRAN II Reference Manual
XDS 900 Series FORTRAN II Operations Manual
XDS ALGOL 60 Reference Manual
XDS Project Management System Reference Manual
XDS Business Language Reference Manual
XDS Sort/Merge Reference Manual
XDS 900 Series Utility and Debug Package (AID)
Publication No.
90 05 06
900566
90 00 18
90 00 19
90 00 03
9005 87
90 06 99
90 08 18
90 1022
9009 97
01 20 13

CONTENTS
1.
GENERAL DESCRIPTION
APPENDIXES
Introduction
1
A. CONVERSION TABLES
XDS910 Registers 2
XDS910 Memory 3 XDS Character Codes A-1
Instruction Word Format 4
Table of Powers of Two
A-2
Specia I Characteristics
5
Octal-Decimal IntegerConversion Table_ A-3
Programmed Operators 6
Octal-Decimal Fraction Conversion Table A-7
2.
MACHINE INSTRUCTIONS B.
TWO'S COMPLEMENT ARITHMETIC
A-10
Introduction
8
C.
COMPUTER OPERATING PROCEDURES_
A-11
Load/Store Instructions
8
Arithmetic Instructions
9 D.
DETAILED MACHINE FUNCTIONS
Logical Instructions 10
Instruction Execution
A-13
Regi ster Change Instructions 11
Typical Interrupt Cycle
A-15
Branch Instructions
12 Buffered
Input/Output
A-17
Test and Skip Instructions
13
Shift Instructions
14
E.
PROGRAMMED OPERATORS
A-19
Contro I Instructions
15
Breakpoint Tests 16
F.
INSTRUCTION LISTS
Overflow Instructions 16
Floating-Point Operations 17 Functional Categories
A-21
Numerical Order A-26
3.
INTERRUPT SYSTEM
Alphabetical Order.
A-29
Priority Assignment 18 INDEX
Index-1
Interrupt Level Operations 18
Interrupt Arm/Enable Response 19
Interrupt Enable/Disable Instructions
and Tests
20
ILLUSTRATIONS
Special Systems Interrupts
21
4.
INPUT/OUTPUT SYSTEM
XDS910 Computer (Frontispiece)
iv
l.
XDS 910 Computer Configuration
2
Introduction.
23
2.
Basic Register Flow Diagram 3
Primary
Input/Output Instructions ___
25
3.
Interrupt Arm-Enable Response 19
Buffer
Control EOM
26
4.
XDS 910 W (Y) Buffer.
24
Standard Buffer EOM Instructions
28
5.
Interlace Input/Output
32
Standard Buffer SKS Instructions 29
6. XDS910Controi Panel
36
Single-Word Transmission
30
7.
Card Read into Memory in Hollerith
43
Interlaced Block Transmission 32
8. Printer Control Indicator lights and
Direct Parallel Input/Output 34
Switches
48
Single-Bit Input/Output
35 9.
Instruction Execution Diagram
A-12
10.
Priority Interrupt System Diagram
A-14
5.
CONTROL CONSOLE
1l.
Buffer Operation, Single-Word
Controls
36
Transmission
A-16
12. Buffer Operation, Interlaced
Displays
37
Transmission
A-18
6. PERIPHERAL EQUIPMENT
TABLES
Input/Output Typewriter
38
Paper Tape Input/Output 38
l.
I nte rrupt LeveIs 18
Card Input/Output
43
2. Y Buffer Character Assembly Options
25
li ne Pri nter
48
3.
Unit Address Codes
27
Moanetic Tone T nnut/Outnut
52
4=
Format Control Characters
51
v • - 1- . -
'.- - -, - - - 1- - -
iii

XDS 910 Computer
iv

1. GENERAL DESCRIPTION
INTRODUCTION
The XDS 910, Figure 1, is a high-speed, low-cost,
general-purpose, digital computer with the following
characteristi cs:
•
•
•
24-bit word, plus parity bit
Bi nary arithmetic
Single-address instructions with
Index Register
Indirect Addressing
Programmed
Operators
• Basic core memory of 2048 or 4096 words, expand-
able to 16,384 words. All words are di rectly ad-
dressable with 8-microsecond cycle time
• 2048- and 4096-word memory modules available
• Typical execution times (including memory access
and indexing) in microseconds:
•
•
•
•
Fixed-Point Operations
Add 16
Multiply 248
Floating-Point Operations
24-bit Fraction (plus 9-bit exponent)
Add 432
Multiply 464
39-bit Fraction (plus 9-bit exponent)
Add 896
Multiply 1696
Program
interchangeability with other XDS 900
Series Computers
Parity
checking of memory and I/O operations
Priority Interrupt System
Two standard XDS hardware interrupts; up to
38 more, optional
Up to 896 optional special system interrupts
Memory nonvolatile in event of power failure; op-
tional power fail-safe feature permits saving con-
tents of programmable registers
•
•
•
•
•
•
•
•
Buffered input/output at rates in excess of 60,000
characters/second simultaneous with computation
Standard input/output
Display and manual control of internal registers
Full-word input/output buffer
The minimum 910 system includes either a
photoelectric paper tape reader or a key-
board printer with paper tape reader and
punch.
Optional input/output devices
Input/output typewriters
Keyboard pri nter with paper tape reader and
punch
300-character/second paper tape readers, 60-
character/second paper tape punches, paper
tape spooIers
MAGPAK
Magnetic Tape Systems
Magnetic tape units (IBM-compatible; binary
and BC D), disc fi les
Card readers, card punches, combination card
reader/punch, line printers
Off-line facility for printing directly from
punched cards or magnetic tape
Communications equi pment, tel etype consoles,
display osci1I0scopes, graph plotters
A to D converters, digital multiplexer equip-
ment, and other special system equipment
MONARCH Monitor Routine, FORTRAN II Com-
pi I er, and META-SYMBOL Assembl er, as part of
complete software package
All silicon semiconductors
O . t 100 to
55
0C
peratmg emperature range:
Dimensions (inches):
Doubl e
rack
mounting: 65-1/2 x 48-1/4 x 25-1/2
Single rack
mounting: 75-3/4 x 25-1/4 x 25-1/4
Power: 110v, 60 cps, 17 amp

Up to 896 special system interrupts
I I I I
I I I I I I , , I I I
Items with dotted lines are optional.
Single-Bit Control ---l .....
and Sense I/O
Word Parallel I/O
(24 lines) ..... --- ...
I I I I I I I I I : I
XDS 910
Computer
Memory expandable to 16,384 words
2048
or
~~~,-----~~--~
4096 __ _
r -,
I I
L_..J
l~--------_v~--------~)
I I
I I I
2048 or 4096 words
33 31
Buffer Interrupt Lines
----------------~
Full-word Buffer
(24 bits)
~2~~ ___ ..,
I Full-word Buffer I
I (24 bits) I
L------4-,
Character Buffer
(6
bits, plus parity)
to I/O
Device
W Buffer
Character Buffer
Y Buffer lJ
(6 to 24 bits, plus parity)
to I/O
Device
Figure 1. XDS 910 Computer Configuration
XDS 910 REGISTERS
The 910 Central Processor contains eight arithmetic and
control registers. Four of the registers are available to
the programmer and four are not.
REGISTERS AVAILABLE TO THE PROGRAMMER
The A, B, X, and P registers (see Figure 2, heavy lines)
are available to the programmer for arithmetic, compar-
ison, test, branch, and program control operations.
The 24-bit A register is the main accumulator for arith-
metic operations.
The 24-bit B register is used as an extension of the A
register. It contains the less significant portion of
doubl e-prec ision numbers.
The
24-bit X register is used to hold the index value in
address modification. Indexing operations with the 14
least significant bits (address portion) of the X register,
provide an indexing capability of up to 16,384 words.
The
14-bit P register (Program Counter) contains the
memory address of an instruction before and during the
time the instruction is being executed. Unless other-
wise specified by the program (with a branch, skip, or
2
EXECUTE instruction), the contents of the P register are
incremented by 1 after each instruction is executed.
REGISTERS NOT AVAILABLE TO THE PROGRAMMER
The
S, C, 0, and M registers (see Figure 2, light lines)
are not directly available to the programmer, but they
are used by the 910 Central Processor to implement in-
struction execution.
The 14-bit S register contains the address of the memory
location to be accessed for instructions or data.
The C register is a 24-bit arithmetic and control regis-
ter. All instructions and data obtained from memory
are brought into the C register for decoding. Address
modification and parity generation/detection take place
in the C register. Also, all input/output operations
are routed through the C register.
The 6-bit 0 register contains the operation code of the
instruction being executed.
The 25-bit M register (24-bit word, plus parity bit) con-
tains each computer word as it is accessed from memory.
Whenever memory is accessed, the contents of the M
register are copied back into memory, thus assuring non-
destructive readout of data and instructions.

A Register
B Register X Register
(Main Accumulator)
(Extended Accumulator)
(Index)
1 •
,
0
Reg.
(Ins
true tion)
. II
P Register
C Register
M Register
(Program Counter)
(Arithmetic and Control)
~
(Memory Access)
S Register
(Memory Address)
-----------------~
Memory
Figure 2. Basic Register Flow Diagram
XDS 910 MEMORY
The basic XDS 910 memory consists of one random access,
2048- or 4096-word magnetic core module with a word
size of 24 bits, plus parity. Additional 2048- or 4096-
word memory modules are available. The Central Pro-
cessor and the input/output buffers can directly address
all memory. Addresses for memory words extend from
octal location 00000 through 03777 (2K memory), 00000
through 07777 (4K memory), 00000 through 17777 (8K
memory), or 00000 through 37777 (16K memory). The
memory in a 16K system is a IIwrap-aroundli or circular
memory where the next location after 37777 is 00000.
An attempt to read from a location whose address is not
available causes zeros to be read. An attempt to store
into such a location essentially results in a IIno-opli op-
eration, with the next instruction in sequence being ex-
ecuted. Thus, a program can use this property to de-
termine the memory size of the machine within which it
is operating.
Before accessing a memory word, the computer checks
the power to ensure that the entire read/write cycle
can be successfu Ily compl eted. If it detects a power
loss, the computer halts. Special logic (optional) may
be inc I uded that prevents loss of information due to
transient power failure or manual power shutoff.
The computer automatically generates even pari ty or
checks for it during each read/write cycle. Setting a
control panel pari ty swi tch causes the computer to hal t
automatically in case of parity error detection.
MEMORY WORD FORMATS
An XDS 910 Computer word is 24 binary digits (bits)
long.
o I 2 3 4 5 6 7
IIIIIIIIIIIIIIIIIIJ II Jill
o 123 4 5 67 8 9101112131415161 18192 212223
These bits are numbered (as shown above) from the left,
or most significant end of the word, to the right, or
least significant end of the word. All references to bit
positions or bit numbers use this numbering scheme (e.g.,
bit 9 refers to bit position 9).
For simplicity of description, computer words are writ-
ten in octal notation. Since one octal digit represents
the absolute value of three binary digits, the 24-bit
number, 000001010011100101110111, is equiva-
lent to the 8-digit octal number 01234567. Octal digits
are also numbered in the same general manner as indi-
vidual bits, with octal 0 being the most significant digit
and octal 7 the least. Octal 3, for example refers to
bits 9, 10, and 11.
3

INSTRUCTION WORD FORMAT
The computer instruction word format is:
Address Field
I I
012 3
8910
Bit position 0 is not used by the centra I processor de-
coding logic.
Bit position 1 contains the index register bit (X).
23
Bit positions 2 through 8 contain the instruction code
field which determines the operation to be performed.
The Programmed Operator feature in the 910 uses bit
position 2; this bit position is a Iso part of the II tag"
field (bit positions 0 through 2).
Bit position 9 contains the indirect address bit (I).
Bit positions 10 through 23 contain the address fieId,
which usually represents the location of the operand
called for by the instruction code.
The following coding examples use standard META-
SYMBOL format in expressing instructions. This format is
LDA A, T
where:
LDA is a representative mnemonic instruction code,
A is a representative address, and T is a 1-digit
octal integer that represents the tag field.
To express indirect addressing (that is, a 1-bit in the
indirect address position), the programmer prefixes an
asterisk to the address field:
LDA *A, T
The
interpretation of the tag field (bit positions 0 through
2)
integer, T, is
4
Tag Field
Integer T
o(or blank)
2
3
4
5
6
7
Interpretation
No relative address, no index,
no Programmed Operator
Programmed Operator
Index
Programmed Operator and Index
Relative address
Programmed Operator and rela-
tive address
Both
relative address and index
Programmed Operator, index,
and relative address
Three-I etter Programmed Operator mnemonics (they have
octal instruction codes 100-177) are usually used to de-
note Programmed Operators. The high-order 1-bit, in
combination with tags of 0, 2, 4, 6, results in tags of
1, 3, 5, and 7, respectively. Programmed Operators
are discussed further in this section under "Special Char-
acteristics, II and in Appendix E.
FIXED-POINT FORMAT
Fixed-point data words have the format
o 1
23
Numbers held in this format are 8-digit octal numbers,
with
the sign incorporated as the "Ieading bit, II bit
position 0, in the most significant octal digit. Thus,
negative numbers have a 1 in bit position 0 and positive
numbers have a 0 in bit position O.
The memory holds fixed-point numbers as 23-bit fractions
with an assumed binary point to the left of bit position
1. A
full-word binary number has an equivalent pre-
cision of over six decimal digits. The range of values
of a fixed-point number is from -1 to less than +1.
Programmers sometimesconsiderfixed-point numbers as
integers, with the binary point to the right of bit posi-
tion 23. The range of integer values is from -8,388,608
to +8,388,607 (-2
23
to +223_1).
When performing
computations with fixed-point numbers,
the program must scale the values to keep them within
the capacity of the computer registers, and align binary
points
so as to arrive at correct results.
The memory holds negative; fixed-point numbers in two's
complement form and the computer operates arithmeti-
cally on these numbers using a two's complement number
system.
See Appendix B for a discussion of two's com-
plement arithmetic.
FLOA lING-POINT FORMAT
XDS offers standard Programmed Operator subroutines
for performing
double- and single-precision, floating-
point arithmetic. Standard floating-point number for-
mats are described below.
Double-Precision, Floating-Point Format
Most
significant word
o 1
23

Least significant word
o
141516
23
The fractional portion of a double-precision, floating-
point number is a 39-bit proper fraction, with the lead-
ing bit being the sign bit and the assumed binary point
being just to the left of the most significant magnitude
bit (bit 1 of the upper word). The floating-point expo-
nent is a 9-bit integer, with the leading bit being the
sign. Standard routines operate on both fraction and
exponent in two's complement form. If F represents the
contents of the fractional fi eld and E represents the con-
tents of the exponent field, the number has the form
F x 2±E.
Double-precision, floating-point numbers have over 11
decimal digits of precision and a decimally equivalent
exponent range of 10-
77
to 10+
77
•
Standard Programmed Operators assume that the more
significant word is in the A register, or stored in memory
location M+ 1, and that the less significant word is in
the B register, or stored in memory location M.
Single-Precision, Floating-Poi nt Format
Fractional word
" 1
v I
Exponent word
o 141516
23
23
The fractional portion of a single-precision, floating-
point number is a 24-bit proper fraction, with the lead-
ing bit being the sign and the assumed binary point be-
ing just to the left of the most significant magnitude bit.
The floating-point exponent is a 9-bit integer with a
leading sign bit. Standard routines operate on both
fraction and exponent in two's complement form.
Single-precision, floating-point numbers have over six
decimal digits of precision and a decimally equivalent
exponent range of 10-
77
to 10+
77
•
Standard Programmed Operators assume that the frac-
tional word is in A, or stored in memory location M+ 1,
and that the exponent word is in B, or stored in memory
location M. When enterina a stcmcJrm1 Prnnrnmmpej
Operator routine, bits 0-14"" of the ex~onen;:~;d··;r-e
ignored. .
SPECIAL CHARACTERISTICS
Certain computer features simplify programming and pro-
vide significant economi es in memory uti I ization and
program running time.
ADDRESS MODIFICATION
Address modification is accomplished through indexing
and indirect addressing, used singly or in combination.
In both indexing and indirect addressing, the computer
performs address modification after bringing the instruc-
tion from memory but before executing it. The instruc-
tion remains in memory in its original form. The result
of the address modification forms the "effective address"
of the instruction operand.
Indexing
The computer contains an index (X) register for address
modification. The use of this register to modify the
address in an instruction does not increase instruction
execution time.
If bit position 1 of an instruction contains a 1, the
computer adds the contents of bits 10 through 23 of the
X register to the contents of the address field of the
instruction prior to execution. This addition does not
retain any overflow or carry beyond the most significant
address bi t.
The computer's instruction set provides instructions for
modifying and testing the X register and for transfering
information between the X register and memory.
Indirect Addressing
The indirect address bit is in bit position 9 of the in-
struction. This bit position determines whether or not
the computer uses indirect addressing with the instruc-
tion being executed.
A 0 in bit position 9 of an instruction causes the com-
puter to use the contents of the address field (bit posi-
tions 10-23 of the instruction) as the 14-bit address
requested by the instruction. A 1 in the index bit
posi tion causes the computer to add the contents of the
X register to this address to form the effective address.
A 1 in bit position 9 of an instruction causes the com-
puter to decode the contents of the location, accessed
as described above, as if it were an instruction without
an instruction code; that is, the computer's address logic
reinitiates address decoding, using the word specified
by the instruction.
For example, the instruction ADD 01000 causes the com-
puter to obtain a \AlOrd from location 01000 (assume it
contains 00001005) and add it to the contents of the
accumulator (A register). However, if the instruction
5

ADD *01000 is given, the computer obtains the word in
location 01000, decodes the address it contains (01005),
and adds the contents of location 01005 to the accumu-
lator. If the word in location 01000 also has a 1 in the
indirect address bit, the process of decoding is reiterated.
Indirect addressing to as many levels as specified adds
one cycle time to each instruction cycle time, for each
level of indirect addressing performed.
If the instruction (or any subsequent word treated as an
instruction) also calls for indexing, the contents of the
index register are added to the address field of the in-
struction before indirect addressing occurs.
Exampl es: Indexing and Indirect Addressing
The
octal instruction code for LOAD A register (L DA),
used in
the examples is 76. Parentheses denote "con-
tents of. "
Location Contents
Effect
X register
00000001
01000
00001001
01001
00041002
01002 00001003
01003
00000002
02000 076 01000
(1000) =00001001 ~A
02001 276 01000 (1 000 + 1) = (1 001) =
00041002 ----.A
02002 07641000
((1000)) = (1 001) =
00041002~A
02003 27641000 ((1 000 + 1)) = ((1 001 )) =
(41002) = ((1002)) = (1003) =
00000002~A
PROGRAMMED OPERATORS
Programmed Operators permit subroutines to be used in
a program by
giving a single "calling" instruction of
the some mnemonic form as built-in machine instructions.
The computer interprets the codes 0100-0177 as special
instructions and transfers to a subroutine uniquely deter-
mined by each code. The computer records the return
address at location 00000 so that program continuity is
maintained. By means of indirect addressing through
location 00000, the subroutine can gain access to the
address of the call ing instruction.
Programmed Operator subroutines are assigned three-
letter, mnemonic designations in the same manner as
built-in machine instructions described in Section 2.
6
A program can use up to 64 Programmed Operators at
anyone time; however, since Programmed Operators are
programmer-specified, the programmer can select alter-
nate sets or subsets of the 64 Programmed Operators from
program to program,
or from section to section of the
same program. The total number of Programmed Opera-
tors is without limit, but it is inconvenient to use more
than 64 in one program. Other computers in the XDS
900 Series maintain compatibil ity among symbolic in-
structions through use of Programmed Operators. Mne-
monic designations are identical in all computers. For
example, whi Ie the designation "FLA" (for FLOATIN G
ADD) refers to a
built-in machine instruction in one
computer, it may refer to a Programmed Operator sub-
routine in another. This technique preserves the one-
to-one instruction relationship; programs written for one
900 Series Computer can be executed on any other com-
puter in the series.
A more detailed discussion and a list of standard XDS
Programmed Operator subroutines are in Appendix E.
OVERFLOW
An overflow detector in the computer makes it possible
to recognize erroneous arithmetic operations that occur
during the execution of a program. The OVERFLOW
indicator on the control panel is set whenever any of
the following conditions occur:
1. The result of an addition or subtraction cannot be
contained within the A register.
2. A left-shift operation changes the contents of bit
position 0 of the A register.
3. The MULTIPLY STEP instruction is executed with
-1 in the effective memory location, 100 in bit
positions 21 through 23 of the B register, and the
contents of the A reg ister divided by 2 is zero.
If the OVERFLOW indicator is set, it remains set untii
the appropriate reset instruction is executed. Section 2
contains instructions to reset or test and reset the state
of the OVERFLOW indicator.
The only instruction affected by the state of the OVER-
FLOW
indicator is OVERFLOW TEST (OVT), which
skips if OVERFLOW is reset. Thus, if desired, the state
of the OVERFLOW indicator can be ignored.
To determine whether a particular program instruction
causes overflow, reset the OVERFLOW indicator before
executing the instruction; then test the OVERFLOW i n-
dicator. An instruction that may be used to set overflow
is RETURN BRANCH (BRR). The instruction BRR $, 4
(where $ is the location of the BRR) "branches" to the
next location and sets the OVERFLOW indicator.

The execution of Programmed Operator, closed, and
interrupt subroutines automatically preserves the status
of the OVERFLOW indicator. In executing a Program-
med Operator instruction, the computer automatically
places the status of the OVERFLOW indicator in bit
position a of location 00000 and resets the OVERFLOW
indicator. The instruction MARK PLACE AND BRANCH
(BRM) places the status of the OVERFLOW indicator in
bit position a of the effective memory location and does
not disturb the OVERFLOW indicator.
The instruction RETURN BRANCH (BRR) automatically
merges the contents of the OVERFLOW indicator with
the contents of bit position a of the effective memory
location and places the result in the OVERFLOW indi-
cator. Section 2 contains a description of the branch
instructions.
SUBROUTI·NE EXECUTION
The XDS 910 Computer makes it possible to execute
three kinds of subroutines:
1. Normal closed subroutine where the input param-
eters are specified in appropriate registers such as
the A register
2. Interrupt subroutine that is entered as the result of
an interrupt
3. Programmed Operator subroutine
A program enters a normal closed subroutine via a
MARK PLACE AND BRANCH (BRM) instruction; BRM
automatically stores the contents of the program counter
(P register) and the status of the OVERFLOW indicator
in the branch-to location. The P register value is nor-
mally the location of the BRM instruction. A RETURN
BRANCH (BRR) instruction accompl ishes the return to
the main program; the BRR adds one to the stored P reg-
ister value and transfers control to that location. See
Section 2, Branch Group, for a description of the branch
i nstruc ti ons.
Interrupt subroutines are closed subroutines, initiated
by the detection of program-controlling interrupts, that
automatically cause the appropriate interrupt subroutine
to be entered. An interrupt causes normal program ex-
ecution to be suspended and control to be transferred to
a fixed location corresponding to that interrupt. The
location normally contains a BRM instruction with the
address of the interrupt servicing subroutine. When the
BRM is executed, it automatically stores the current con-
tents of the P register and the OVERFLOW indicator, in
the branch-to location. The BRM then transfers control
to the branch-to location + 1. (When an interrupt occurs,
the instruction process is completed, and control is trans-
ferred to the appropriate BRM without disturbing P. The
value stored from P, therefore, is the address of the in-
struction to which program control should return after
the interrupt is serviced by the interrupt subroutine). A
BRANCH UNCONDITIONALLY (BRU) instruction with
indirect addressing (through the branch-to location of
the subroutine) returns control to the main program at
the completion of the subroutine. BRU indirect also
clears the interrupt from the active state. Note that
this differs from the normaI closed subroutine return that
uses the BRR (stored P value + 1 ---.. P).
7

2. MACHINE INSTRUCTIONS
INTRODUCTION
This section describes XDS 910 instructions in functional
groups. Lists of instructions in functional, numerical,
and alphabetical order are given in Appendix F, pages
A-21, A-26, and A-29 respectively.
A diagram representing the format of the instruction ac-
companies the description of each instruction. Preced-
ing each diagram is the mnemonic code and name that
identifies the instruction. Within the diagram, the let-
ter X in bit position 1 indicates that indexing can be
used with the instruction, the letter I in bit position 9
indicates that indirect addressing can be used with the
instruction, and the letter M in the address field indi-
cates that the instruction obtains an operand from mem-
ory.
If bit position 1 of the instruction diagram contains a 0,
indexing cannot be used with the instruction; if bit posi-
tion 9 of the instruction diagram contains a 0, indirect
addressing cannot be used with the instruction. Some
instructions are shown with octal numbers in the address
field; these instructions do not require an operand from
memory,
but use the address field to extend the opera-
tion code of the instruction.
The following statements apply to the instruction de-
criptions:
Parentheses denote "contents of". For example,
"(A)" means "contents of the A register."
Subscripted characters identify inclusive bit posi-
tions. For example, "(Bh8-23" means "the con-
tents of bit positions 18 through 23 of the B regis-
ter.
The contents of computer words and registers are
expressed as octal-coded binary numbers; all other
octal numbers used in this manual contain a lead-
ing zero, but decimal numbers do not. Thus, 0200 =
200
8
and 200 = 200
10,
The term "effective memory location" refers to the lo-
cation in memory from which the operand is taken at the
conclusion of all indirect addressing and indexing. This
term is sometimes
shortened to "effective location." It
is the location whose address is the effective address.
The term "effective operand
ll
means the contents of the
effective memory location.
The term "set" means "place a l-bit in the contents of"
a computer word, or "turn on" an indicator. II Reset"
means "place a z.ero in the contents of" a computer word,
or IIturn off" an indicator, or "clear to zeroll.
8
The interrupt system can interrupt the program at the end
of any instruction, except INCREMENT INDEX AND
BRANCH (BRX) and ENERGIZE OUTPUT M (EOM).
Instruction timing is given in terms of memory cycles,
where each cycle is 8 microseconds, including the time
required for fetching the instruction and all operands.
Indexing does not change the timing of any instruction,
but each level of indi rect addressing used adds one ad-
ditional memory cycle to the instruction timing given.
LOA
o 1 2 3
LOAD/STORE INSTRUCTIONS
LOAD A
76
I M
23
LOA loads the contents of the effective memory location
into the A register; the contents of the effective memory
location are not affected.
Affected: (A) Timing: 2
STA STORE A
M
o 1 2 3 8 9
10
23
STA stores the contents of the A register in the effective
memory location; the contents of the A register are not
affected.
Affected: (M)
LOB
o 1 2 3
LOAD B
75
, 8 9
10
Timing: 3
M
23
LOB loads the contents of the effective memory location
into the B register; the contents of the effective memory
location are not affected.
Affected: (B)
STB
o 1 2 3
STORE B
36
I
8910
Timing: 2
M
23
STB stores the contents of the B register in the effective
memory location; the contents of the B register are not
affected:
Affected: (M) Timing: 3

LOX
o 1 2 3
LOAD INDEX
71
I 8 9 10
M
23
L DX loads the entire 24-bit contents of the effective
memory location into the index register; the contents of
the effective memory location are not affected.
Affected: (X)
STX
o 1 2 3
STORE INDEX
37
I
8910
Timing: 2
M
23
STX stores the entire 24-bit contents of the index regis-
ter in the effective memory location; the contents of the
index register are not affected.
Affected: (M) Timing: 3
EAX
o 1 2 3
COpy EFFECTIVE ADDRESS INTO INDEX
REGISTER
77
I 8 9
10
M
23
EAX copies the address of the effective memory location
into bit positions 10 -23 of the index (X) register; the
ten most significant bits of the X register and the con-
tents of the effective memory location are not affected.
The addressing process for this instruction operates as in
a load instruction, except that instead of obtaining the
contents of the effective .memory location, the effective
memory address is the operand. For exampl e, if EAX is
executed with zeros in bit positions 1 and 9, the actual
bit configuration in the address field of EAX is copied
into bit positions 10 -23 of the X register.
Affected:
(X) 10-23
Timing: 2
ARITHMETIC INSTRUCTIONS
ADD
ADD MEMORY TO A
101+1
55
1I I M
I
o 1 2 3 8910
23
This instruction adds the contents of the effective mem-
ory location to the contents of the A register and places
the result in A. If both numbers are of the same sign but
the sign of the result in the A register is opposite, over-
flow has occurred and the computer has set the OVER-
FLOW indicator.
Affected: (A), Of
Timing: 2
MIN
o 1 2 3
61
I
MEMORY INCREMENT
M
8 9 10
23
MIN increases the contents of the effective memory lo-
cation by one, and places the resulting sum in the same
location. The contents of the A register do not change.
Overflow occurs only when the contents of Mare
37777777 before execution. In this case, 40000000 is
the result in M.
Affected: (M), Of
MOE MEMORY DECREMENT
o 1 2 3
60
I
8910
Timing: 3
M
23
MDE decreases the contents of the effective memory lo-
cation by one and places the resulting difference in the
same location. The contents of the A register do not
change.
An overflow occurs if the initial contents of memory are
40000000. The result inmemoryinthiscaseis37777777.
Affected: (M), Of
Timing: 3
SUB
SUBTRACT MEMORY FROM A
54
I M
o 1 2 3 8 9 10
23
SUB subtracts the contents of the effective memory loca-
tion from the A register and places the result in the A
regi ster.
If both numbers are of the same sign after the contents
of the effective address have been compl emented for
addition but the sign of the result in the A register is
opposite, an overflow has occurred and the computer
has set the OVERFLOW indicator.
Affected: (A), Of
Timing: 2
MUS
1 2 3
MUL TIPL Y STEP
64
I
8910
M
23
The sign of A temporarily extends two bit positions to
the left if the OVERFLOW indicator is reset. If the
OVERFLOW indicator is set, the two bits extended are
zeros. Then the contents of the memory location
9

determined by the effective address are added to or sub-
tracted from the A register, based on the contents of the
three low-order bits of the B register. The arithmetic
operation performed takes place according to the follow-
ing table:
B21
B22
B
23
Arithmetic Operation
0 0 0
None
0 0 1 (A) + 2(M)
---. A
0 1 0 (A) + 2(M)
----. A
0 1 1 (A) +
4(M) ----. A
1 0 0 (A) -4(M)
---. A
1 0 1 (A) -2(M)
---. A
1 1 0 (A) -2(M)
---. A
1 1 1
None
The computer then shifts the result in the double-length
AB register two bit positions to the right.
The OVERFLOW indicator is set if (M) is -1, the con-
tents of B21-23 were 100, and (A)/2 was originally
zero. Otherwise, the OVERFLOW indicator is reset.
Various multiply subroutines (such as Programmed Op-
erators) use this instruction. Twelve MUS instructions
can be repeated to provide a complete multiplication of
the form (M) x (B) --+- AB. Prior to execution of the
first step, the multipl ier must be in the B register, the
A register cleared, the double-length AB register shifted
left one, and the OVERFLOW indicator turned off.
Affected: (AB), Of Timing: 2
The Programmed
Operator subroutine MULTIPLY (MUL)
requires 248 fJsec for a full multiplication.
DIS DIVIDE STEP
65 M
o 1 2 3 8 9
10
23
DIS shifts the contents of the double-length AB register
left one bit position and copies the complement of AO
into B23. If (AO) = (MO), the contents of the memory
location determ ined by the effective address are sub-
tracted from the A register. If (AO) -I (MO), the con-
tents of the memory location determined by the effective
address are added to the A register.
The Programmed Operator divide subroutines use this
instruc
tion.
Affected: (AB)
Timing: 2
The Programmed
Operator subroutine DIVIDE (DIV) re-
quires 888 fJsec for a full division. The subroutine pro-
vides a corrected remainder of the same sign as the
original A register.
10
LOGICAL INSTRUCTIONS
ETR EXTRACT
14 M
012 3
23
ETR performs a logical "AND" between corresponding
bits of the A register and the effective memory location
and places the result in A. This instruction performs the
operation bit by corresponding bit according to the fol-
lowing:
(A)
o
o
1
1
Affected: (A)
Example: ETR M
(M)
o
1
o
1
Before
Execution
(A) 64231567
(M) 00777600
MRG MERGE
o 1 2 3
16
I
89 10
Result
in A
o
o
o
1
After
Execution
00231400
00777600
M
Timing: 2
23
MRG performs a logical "Inclusive OR" between corres-
ponding bits of the A register and the effective memory
iocation and piaces the result in A. This instruction
performs the operation, bit by corresponding bit, as
follows:
Result
(A) (M) in A
0 0 0
0 1 1
1 0 1
1 1
Affected: (A) Timing: 2
Example:
MRGM
Before
After
Execution
Execution
(A)
06446254
06746756
(M)
02340712
02340712

EOR
EXCLUSIVE OR
I IOIXIOI
17 II I M
o 1 2 3 8 9 10 23
EOR performs a logical II Exc lusive OR" between corre-
sponding bits of the A register and the effective memory
location and places the result in A. This instruction
performs the operation bit by corresponding bit, as
follows:
(A)
0
0
1
1
(M)
0
1
0
Result
in A
o
1
1
o
Affected:
(A)
Timing: 2
Example:
EORM
(A)
(M)
Before
Execution
34165031
70077021
After
Execution
44112010
70077021
The proper memory word configuration logically inverts
selected bit positions of the A register. If all "ones"
appear in the memory word, a one's complement of A
resu Its.
Example: EOR M
(A)
(M)
Before
Execution
10357211
77777777
After
Execution
67420566
77777777
REGISTER CHANGE INSTRUCTIONS
RCH REGISTER CHANGE
023
46
I
89101112
0000
I
23
RCH performs the following operations upon the contents
of the A and B registers, depending on the va lues of bit
positions 10 and 11 of the instruction word:
10 11 Function
o 0 Exchange A and B (XAB)
o 1 Copy B into A, clear B (BAC)
1 0
Copy A into B, c lear A (ABC)
1 1 C
lear A and B (CLR)
Indirect addressing and indexing do not apply to register
change instructions.
Affected: (A), (B)
XAB
RCH 0
EXCHANGE A AND B
o 2 3
46
I 8 9
00000
I
Timing: 1
23
XAB copies the contents of the A register into the B reg-
ister and si mul taneously copies the contents of the B reg-
ister into the A register.
Affected: (A), (B)
BAC COpy B INTO A, CLEAR B
RCH 010000
o 2 3
46
I 8 9
10000
I
Timing: 1
23
BAC copies the contents of the B register into the A
register and simultaneously clears the B register to
zero.
Affected: (A), (B)
ABC COpy A INTO B, CLEAR A
RCH 020000
023
46
I 8 9
20000
I
Timing: 1
23
ABC copies the contents of the A register into the B
register and simultaneously clears the A register to
zero.
Affected: (A), (B)
CLR CLEAR AB
RCH 030000
o 2 3
46
I
Timing: 1
30000
23
CLR clears the contents of both the A and B registers to
zero.
Affected: (A), (B)
Timing:
11

BRANCH INSTRUCTIONS
Branch instructions conditionally or unconditionally
change the course of the program by a Itering the con-
tents of the program counter (P reg ister). The program-
mer should note that these instructions branch to loca-
tions determined by the effective address; this means
that the branch can operate with all levels of indirect
and indexed addressing.
BRU
BRANCH UNCONDITIONALLY
01 M
o 1 2 3
8910
23
BRU takes the next instruction from the location deter-
mined by the effective address. A BRU instruction with
an indirect address bit equal to 1 clears the highest pri-
ority interrupt level then active, in addition to branch-
ing to the effective location.
Affected: (P) Timing:
BRX INCREMENT INDEX AND BRANCH
o 1 2 3
41
I 8 9
10 I M ,
23
BRX increments the contents of the entire X register
by 1. If the resultant X register value contains a 1-bit
in bit position 9, the computer transfers control to the
effective location; if not, it takes the next instruction
in sequence.
If a BRX instruction is indexed, any transfer of control
is to the effective address determined by the value of
the index before it is incremented. However, the test
for transfer is based on the incremented value of the
X register; just as if the BRX instruction were not
indexed.
The 9 most significant bits of the X regi ster (bits 0
through 8) have no effect on the execution of the
instruction, but may be affected by it.
If a branch occurs, an interrupt cannot occur following
the execution of this instruction.
Affected: (X), (P)
Timing: 1 if branch
2 if no branch
Example:
Location Contents
Instruction (X register)
00777
2 35 01500
STA 01500,2
77777776
01000 041 01006 BRX 01006 77777777
01001 2 76 02000
LDA 02000,2
77777777
01006 041 01001
BRX 01001 00000000
01007 2 76 02100
LDA 02100/2
00000000
12
The
execution of these instructions is in the following
order, as given by their locations:
00777
01000
01006
01007
BRM MARK PLACE AND BRANCH
o 1 2 3
43
I M
23
BRM is normally used to enter subroutines where a re-
turn to the main program is desired after the subroutine
has been completed.
BRM stores the contents of the P register (normally the
address of the BRM instruction itself) in the effective
memory location (subroutine entry location) and trans-
fers control to that location plus one (first instruction of
subroutine). BRM also stores the status of the OVERFLOW
indicator in bit 0 of the effective location. The con-
tents of bits 1-9 of the effective location are cleared
to zeros.
When a BRM stored in an interrupt location is executed
(as the result of an interrupt) P contains the location of
the next program instruction that would have been exe-
cuted if the interrupt had not intervened. It is this
II re turn location
ll
instead of the BRM's own location that
is stored in this instance. Information about the inter-
rupt system is given in Section 3.
Affected: (M), (P)
Exampl e: BRM 0522
Location
01517
OVERFLOW
Indicator
Before execution:
1 (on)
After execution:
1 (on)
BRR RETURN BRANCH
o 1 2 3
51
I 8
910
Timing: 2
Contents
o 43 00522
Location
P
0522
Register
01517
40001517
00523
M
23
BRR is normally used to return to the main program after
completion of a subroutine in conjunction with MARK
PLACE AND BRANCH (BRM) except in interrupt subrou-
tines (see Section 3).

BRR copies the contents of the effective memory location
(subroutine entry location) into an internal register and
increments the contents by one. The instruction then
stores the least significant 14 bits of the result in the P
register. (The P register contains the address of the next
instruction to be executed.) It also performs a logical
OR between bit 0 of the effective memory location and
the OVERFLOW indicator and places the result in the
OVERFLOW indicator. There is no change in the con-
tents of the effective memory location.
Affected: Of, (P)
Exampl
e: BRR 02000
Location
02100
02000
Timing: 2
Contents
o 51 02000
o 00 03220
If the computer executes the instruction in location
02100, it takes the next instruction from location 03221.
Location 02000 sti II contains 0 00 03220.
TEST AND SKIP INSTRUCTIONS
SKG SKIP IF A GREATER THAN MEMORY
o 1 2 3
73
I M
8 9 10 23
SKG algebraically compares the contents of the A re-
gister with the contents of the effective memory loca-
tion. If the contents of A are greater than the contents
of the effective location, the computer skips the next
instruction in sequence and executes the following in-
struction. If the contents of A are less than or equal to
the contents of the effective location, the computer exe-
cutes the next instruction in sequence. SKG alters
neither A nor memory.
Affected: (P) Timing: 2 if no skip
3 if skip
SKM SKIPIFAEQUALSMEMORYON BMASK
o 1 2 3
70
I M
23
SKM compares designated bit positions of the A register
with corresponding bit positions in the effective memory
location. If the specified bits in A are identical to those
in
the effective memory location, the computer skips
the next instruction in sequence after SKM and executes
the following instruction. If the specified bits are not
identical, the computer executes the next instruction in
sequence after S KM.
The programmer selects the bit positions to be compared
by placing 1-bits in the corresponding bit positions of
the B register and O-bits in the remaining bit posi-
tions of B.
SKM considers the contents of A, B, and the effective
location to be unsigned, 24-bit, nonnumeric quantities,
and does not al ter them.
Affected: (P)
Example: SKM M
(A)
00043007
(B)
00177000
Tim ing: 2 if no skip
3 if skip
(M)
57643240
Since SKM compares bit positions 8-14 only (as deter-
mined by (B), and (A) = (M) in these positions, a skip
occurs. Note that if (B) = 0, a skip occurs regardless
of (A) and (M).
SKA
SKIP IF A AND MEMORY DO NOT
COMPARE ONES
o 1 2 3
72
I M
23
SKA compares the contents of the A register, bit by bit,
with the contents of the effective memory location. If
the A register and the effective location do not both
have 1-bits in any corresponding bit positions, the com-
puter skips the next instruction in sequence after SKA
and executes the following instruction. If the A register
and the effective location do have at least one pair of
1-bits in corresponding bit positions, the computer exe-
cutes the next instruction in sequence after SKA.
The instruction logically ANDs corresponding bits in A
and memory, based on the following table:
(A) (M) Result
0 0 0
0 1 0
1 0 0
1 1 1
If the result produces a 1-bit in any bit position, a skip
does not occur.
Affected: (P) Timing: 2
if no skip
3 if skip
Different configurations of the memory word result in a
wide variety of conditional skip instructions for use by
the programmer. Some examples are:
Memory
Configuration
40000000
77777777
00000001
Effect
Skip if A is Positive
Skip
if A =0
Skip if A is Even
13

Contents of
A Register
40000000
77777777
00000001
Effect
Skip if Memory is Positive
Skip if Memory = 0
Skip if Memory is Even
SKN SKIP
IF MEMORY NEGATIVE
o 1 2 3
53
I 8 9 10
M
23
If the contents of the effective memory location are
negative, i.e., if (MO) = 1, the computer skips the next
instruction in sequence after SKN and executes the fol-
lowing instruction. If the contents of the effective lo-
cation are positive or zero, the computer executes the
next instruction in sequence after SKN.
Affected: (P) Timing: 2 if no skip
3 if skip
SHIFT INSTRUCTIONS
The shift instructions operate on the contents of the A
and B registers and offer a complete faci I ity for right
and left shifting, cyc ling, and normal izing the contents
of these two registers. The A and B registers, in com-
bination, form a double-length register whose double-
length contents can be shifted, cycled, or normalized.
This double-length register is named "AB".
When the contents of the AB register shift right, bits
from
bit position 23 of the A register shift into bit posi-
tion 0 of the B register. When the AB register shifts left,
bits from bit position 0 of the B register shift into bit po-
sition 23 of the A register.
Two shift instructions allow the 48-bit contents of the
AB register to be "cycled" right or left. When the con-
tents of the AB register cycle, the bits that shift from
one end of the one regi ster copy into the other end of
the other register.
Shift instructions use the instruction code to determine
the direction of shift (66 = right; 67= left); bits 10 and
11 of the effective address determine the method of
shifting as follows:
Octal Octal
Position (Bits 10, 11)
Value
Function
00 0
AB Shift
3 10 2 AB Cycle
01
1
Normalize (left only)
Indexing of a direct address shift instruction affects only
bits 18-23 of the address field. It is thus possible to
index the number of shifts without affecting bits 10 and
14
11, which control the method of shifting. During in-
direct addressing, the full 14 bits of the address field
are used in the address computation; thus, only the
shift instructions RSH and LSH should be indirectly
addressed, with bits 10 and 11 of the effective address
determining the method of shifti ng.
When the computer interprets a shift instruction, bit po-
sitions 18 through 23 of the effective address of the in-
struction determine the amount of the shift. The
computer treats these six bits as an unsigned count. If
the initial count is equal to zero, no shifting occurs.
Once the shift begins, the count is reduced by one for
each position shifted untiI it reaches zero. The count
C in the following instructions indicates the number of
places to be shifted.
Shift timing is calculated as follows, where N is the num-
ber of places shifted.
Timing in Cycles Number of Places Shifted
2+N
RSH
o 1 2 3
N =0, 0, 1, 2, 3, ... 48
RIGHT SHIFT AB
66
I
89101112
o
I C
I
23
RSH shifts the contents of the AB register right the num-
ber of places specified in bits 18 through 23 of the ef-
fective address. The bit in the sign position of A does
not shift; its value is copied into the vacated bit posi-
tions of the shifted number. The bit in the sign position
of B shifts. Bits shifted out of A23 shift into BO' Bits
shifting past position B23 are lost.
This
instruction may be used to perform scaling of floating-
point numbers by use of indexing, where the difference
of exponents is in the X register as a positive quantity.
Affected:
(AB)
Timing:
2+N
Example: RS H 18 (0 66 00022)
Before
After
Execution
Execution
(A)
45261237
77777745
(B)
27651260 26123727
RCY RIGHT eye LE AB
lolxlo I
66
1011 10 I 0
17
1
18
C 1
o 1 2 3 I
89 10 1112
, I
23
RCY shifts the contents of the AB register right the num-
ber of places specified in bits 18 through 23 of the