XDS
910
BASIC
INSTRUCTIONS
ICentral
Processorsj
Vlnemonic Code Name Page Mnemonic Code Name Page
LOAD/STORE TEST/SKIP
LDA
A,
T 76 Load A
from
Memory SKG
A,
T 73 Skip if A
Greater
Than Memory
13
STA
A,
T
35
Store A
in
Memory
SKM
A, T 70 Skip if A = Memory on B Mask
13
LDB
A,
T
75
Load B
from
Memory
SKA
A, T 72 Skip if A and M
Do
Not
STB
A,
T 36 Store B in Memory Compare
Ones
13
LDX
A, T
71
Load Index
from
Memory
SKN
A,
T 53 Skip if Memory
Negative
14
STX
A,
T 37 Store Index
in
Memory
EAX
A, T 77 Copy Effective Address into Index
SHIFT
ARITHMETIC
RSH
N, T
066
OOOXX
Right Shift
AB
14
RCY
N, T
066
200XX Right
Cycle
AB
14
ADD
A,
T 55
Add
Memory to A
LSH
N, T
067
OOOXX
Left Shift
AB
15
MIN
A,
T
61
Memory Increment
LCY
N, T
067200XX
Left
Cycle
AB
15
MDE
A,
T 60 Memory Decrement
NOD
N, T
067
100XX Normalize, Decrement X
15
SUB
A,
T
54
Subtract Memory
from
A
MUS
A,
T 64 Multiply Step CONTROL
DIS
A,
T 65 Divide Step
10
HLT
00 Halt
15
NOP
20 No
Operation
16
LOGICAL
EXU
A, T 23 Execute Instruction
in
Memory
16
ETR
A,
T
14
Extract
10
BREA
KPOINT
TESTS
MRG A, T
16
Merge
10
EOR
A,
T
17
Exclusive
OR
11
BPT
1
04020400
Breakpoint No. 1 Test
16
BPT
2
04020200
Breakpoint
No.2
Test
16
BPT
3
04020100
Breakpoint
No.3
Test
16
REGISTER
CHANGE
BPT
4
04020040
Breakpoint
No.4
Test
16
RCH
46 Register
Change
11
XAB
04600000
Exchange A and B
11
OVERFLOW
BAC
046
10000 Copy Binto
A,
Clear
B
11
OVT o40 20001 Overflow Test; Reset
16
ABC
046
20000 Copy A into
B,
Clear
A
11
ROV
o0220001 Reset Overflow
16
CLR
046
30000
Clear
AB
11
BRANCH
INTERRUPT
EIR
002
20002 Enable Interrupts 20
BRU
A,
T
01
Branch Unconditionally
12
DIR
00220004
Di
sabl e Interrupts 20
BRX
A,
T
41
Increment Index and Branch
12
lET
04020004
Interrupt Enabled Test
20
BRM
A, T 43 Mark Place and Branch
12
!DT
040
20002 Interrupt Disabled Test
20
BRR
A,
T
51
Retu
rn
Bronc
h
12
AIR
002
20020
Arm
Interrupts
21
Legend: A = address,
*A
=
indirect
address; T = tag field; N = number
of
shifts
