Digital Equipment BM873 User manual

BM873
restart/loader
DEC-II-H873A-B-D
digital equipment. corporation · maynard,massachusetts

Copyright © 1974 by Digital Equipment Corporation
The material in this manual is for informational
purposes and
is subject to change without notice.
Digital Equipment Corporation assumes no respon-
sibility for any errors which may appear in this
manual.
Printed in U.S.A.
The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC
FLIP CHIP
DIGITAL
UNIBUS
PDP
FOCAL
COMPUTER LAB
First Edition, January 1974
2nd Printing (Rev), April 1974

CHAPTER 1
1.1
1.2
1.3
CHAPTER 2
2.l
2.l.1
2.1.2
2.1.3
2.2
CHAPTER 3
3.l
3.2
CHAPTER 4
4.1
CHAPTERS
CHAPTER 6
Figure No.
1·1
1·2
2·1
4·1
Table No.
1-1
2-1
DESCRIPTION
INTRODUCTION
...... .
GENERAL DESCRIPTION
FUNCTIONAL DESCRIPTION
CONTENTS
INST
ALLATION AND CHECKOUT
INSTALLATION
Start Address Selection
Jumper Selection ...
CPU Addressing with Volatile Memory
CHECKOUT ............... .
PROGRAMMING
POWER
FAIL PROGRAMMING
REGISTER DESCRIPTION
OPTIONS
Page
1-1
1-1
1-2
2-1
2-1
2-3
2-3
2-3
3-1
3-1
USER CUSTOM PROGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-1
INTERFACE
ENGINEER1NG DRAWINGS
ILLUSTRATIONS
Title
Remote Start Timing ...... .
Memory Read Timing
..... .
External Interface Circuit Diode Matrix
Sample ROM Program Data Sheet
TABLES
Tide
BM873 Specifications ..... .
BM873-YA
Option Starting Addresses
iii
Page
1-3
14
2-2
4-2
Page
1-2
2-2

1.1 INTRODUCTION
CHAPTER 1
DESCRIPTION
This manual describes the operation and theory of the BM873 Restart/Loader. This option is intended for use with
the PDP-II family
of processors. The BM873
• serves as general purpose loader for processors of the 11 family,
• contains bootstran loaders for alI common devices,
• provides the capability ofloading with a "hidden console",
• permits starting from several sources e.g., pushbutton, Watchdog Timer,
MODEM control, power fail,
etc.,
• gives PDP-II systems an initial program load capability,
• contains at least four starting addresses, and
• permits the calling of a special user ROM program.
It is assumed that the reader is thoroughly familiar with the operation ofthe PDP-ll processor with which this
option
is used.
1.2 GENERAL DESCRIPTION
The BM873 option is mounted on a single quad-sized module which plugs into a small peripheral controller (SPC)
slot. In its basic version, it contains several bootstrap loader programs within a 128-word Read-Only Memory
(ROM). These programs may be loaded either from the console (Load Address and Start), by a JMP instruction in
the program,
or by an external contact closure or voltage level. The external interface is made via an 8-pin
Mate-N-Lok connector. Specifications are listed in Table
I-I.
I-I

Table 1-1
BM873 Specifications
Capacity
Word length
ROM cycle time
Voltage requirements
Current requirements
Operating temperature
Humidity
1.3
FUNCTIONAL DESCRIPTION
128 words, read-only
(256 words optional)
16 bits
500 ns
+5 V ±5%
-15 V ±5%
1.0 A max @ +5 V
2.0 rnA max @ -15 V
20% to 95%
The BM873 consists
of two basic sections: the Restart Sequencer and the ROM.
Figure 1-1 shows the remote start timing. The Restart Sequencer takes contact closures or voltage levels and, after
filtering and delaying, sets one of four Start Address Select flip-flops. The setting of one of the flip-flops causes the
Begin Load Sequence flip-flop to set; this, in turn, initiates two one-shots' to create a BUS AC LO/BUS DC LO
sequence. The processor responds to the sequence by performing its normal power-down and power-up trap
routines. Prior to the power-up sequence, however, the BM873 option asserts 773000 on the Unibus Address Lines.
As a result, when the Program Counter (PC) and Processor Status Word (PSW) are restored, the data is taken from
locations 773024/26 (nonvolatile memory systems) or fpJm locations 773224/26 (volatile memory systems). Both
of these addresses are locations within the BM873 option. The data from 773*24 is 173000; the data from 773*26
is 340, establishing a priority level of 7.
The data read from 773*24 (173000) will have an offset address ORed onto Offset Address bits 8 through 1, giving
a range of 173000 to 173776. The offset address bits are enabled by one of the four Start Address Select flip-flops
via a diode matrix (paragraph 2.1.1). Each bootstrap loader program has its own starting address, and it is this
address that
is selected via the offset address bits.
The following sequence
of operations would be typical:
• Close external switch and wait for switch filter delay.
• Assert AC LO; wait 6 ms.
• Assert DC LO for 6 ms; then wait 8 ms.
• Drop AC LO and assert address 773000.
• Wait for INIT to finish.
• The processor enters power-up routine.
1-2

SWITCH ~. ,/___ ,,,,u,
: "V\\._ ---------------I111,-~ _ ......... ,:........ __ -',,-
I
i ~-----------~\~~----_T:----~I
REC 1 _...;..;.1::.;5m~s:..........J L ________ l
CLR DLY ----..,
~-------~\~\-----------
20m.
START ADR S:::E:: ___________ ~~I~".:...S -------1\ (j
BEGIN LOAD SEQ --------....1- ~i -------~ \----1--------
I
BUS ACLO L ---------. I
\\-...J..i_--,I
I
BUS DCLO L ------------:1
BUS INIT L ---------+__,
ASSERT ADR 773000 -------------1
CPUDLY __________________________ -J
FETCH 77 3024/26 ----+I
PWRUPTRAP------------------- _____ --J
CPU-BEGIN EXECUTION _______________________ .....J
OF ROM PROGRAM
11-2408
Figure I-I Remote Start Timing
• The BM873 option recognizes the fetch of address 773024 or 773224 and asserts 173XXX plus the 8-bit
offset address to the data lines.
• The processor reads location 773026 or 773226 which is always 000340 (priority level 7).
• The processor fetches. the next instruction from the ROM in address range 773000-773776. From this
point, the bootstrap loader program contained in the
ROM has control. (In the PDP-ll/35 and
PDP-I 1/40 systems, the PSW is fetched before the PC.)
If an actual power fail occurs in a nonvolatile memory system, the BM873 option does nothing, and the power-down
and power-up traps work in the normal manner. If
an actual power fail occurs in a volatile memory system, the
power-up jumpers in the processor
are set for 173224. During power-up the processor will fetch from 173224; the
combination
of address 773224 and no external lines asserted will cause the BM873 option to assert line I as a
default case. Thus, in this case, the offset address selected for line 1becomes the bootstrap loader call for power fail.
Data is read from the ROM in two bytes. Address bits 7 through 1 are present at all times via the bus receivers.
Address bit 0
is generated on the module. AO is always clear prior to a read cycle. The setting of AO clocks the first
byte into a holding register and simultaneously changes the address to gate the second byte to the output drivers.
After a delay
of about 200 ns, the output gates are enabled and the ROM data is placed on the Unibus. SSYN is
asserted about 150 ns later, completing the read cycle. Figure 1-2 illustrates memory read timing.
1-3

ADR 8 CONTROL J
MSYN (READ)
AID (1) H ----'
RD DLY (0) H ----,1'.
DATA TO BUS (I) H ------1
BUS SSYNL -------.
500 ns
OR LESS
L
200ns
l.DEPENDENT ON
BUS LENGTH
11- 2407
Figure 1-2 Memory Read Timing
1-4

2.1 INSTALLATlON
CHAPTER 2
INSTALLATION AND CHECKOUT
Normally the BM873 Restart/Loader is installed at the factory and no further installation is required. However, if
this option is added to an existing system, it may be necessary to add wiring to make the AC LO and DC LO signals
available. These signals are provided on the PDP-II/OS and PDP-ll/4S processors, and on the
DDll-B. On the
PDP-ll/lS, PDP-ll/20, PDP-ll/3S, PDP-ll/40, and the DDII-A it is necessary to ensure that the SPC slot
containing the
BM873 has BUS AC LO and BUS DC LO wiring available as follows:
Pin CVl to B01Fl or B04Fl
(BUS AC LO)
Pin CNI to BOI F2 or B04F2 (BUS DC LO)
If the wiring is not present, it must be added by hand-wiring, using a wire color different from that of the existing
backplane wiring.
NOTE
The BM873 option must be on the CPU side of any bus buffer.
2.1.1 Start Address Selection
Each
of the four external interface circuits has an associated address which must be specified for that circuit to be
addressed. Each address consists of a fixed high-order portion (773XXX) and a low-order portion (bits 8 through 1)
that
is selected by adding or cutting diodes (Figure 2-1). When adding diodes, a low.wattage iron should be used and
care should
be taken with the plated mounting holes, so that the plating is not lifted from the laminate by the heat.
The diodes (DEC type 664 or IN3606) should be positioned so that their cathodes point toward the gold fingers of
the module.
Table
2-1 lists starting addresses for various devices used with the BM873-YA Restart/Loader. The three rightmost
digits
of the address represent the low-order portion to be selected via diodes.
The diagnostic program for this option contains a listing
of the loader program in the comments portion of the Data
Compare section. That diagnostic will be updated to contain the starting addresses and listing
of future variations
(·YB, etc.).
2-1

BIT 8\ BIT '\
LINE 1 - ~1~1~1~1~1~1~loll4-----,
LINE 2 - ~i~l~t~t~t~t~t~t 1-------1
LINE 3- ~t~t~t~t~t~t~t~1
LINE 4- ~1~1~1~I~r~I~I~r
BM873 MODULE
Address
773000
773010
773020
773030
773050
773 100
773 144
773210
773230
773312
Figure 2·1 External Interface Circuit Diode Matrix
Table
2-1
BM873-YA Option Starting Addresses
Device Type
RFII
RKII
Transfer to Address contained in Switch Register
TCII
TMl1
RPll
RCl1
KL11 /DL11 -Console TTY Reader
TAll
PCII--Paper Tape Reader
2-2
11-2406

2.1.2 Jumper Selection
The BM873 module contains three jumpers
that are marked with the numerals I, 2, and 3. Jumpers I and 2 :J~e used
to compensate for differences between: the PDP-I 1/40 and 11/35 and
all other PDP-II family processors. Jumper I
should be installed when the option is used with either the PDP-I 1/40 or the PDP-l 1/35. Jumper 2 should be
installed for use with any other processor in the PDP-II family.
Jumper 3 controls access
to an extra 128 words of ROM. When this jumper is cut, additional addresses from 773400
to 773776 become available.
2.1.3
CPU Addressing with Volatile Memory
When this option
is used in computers with volatile memory, the power fail trap address must be jumpered to
773224
if automatic reloading is desired.
For a PDP-l 1/45 CPU, install jumpers
W6, W3, and WI on the M81 00 board. This will provide an address of 773224.
For a PDP-l 1/40 CPU, connect jumper
W7 on the M7235 board for a binary 1. This jumper will provide an address
of 7732XX. The last two digits are provided by jumpers 4 and 2.
2.2 CHECKOUT
The diagnostic program for the BM873 option is MAINDEC-II-DZBMX-A. This program starts with a dialogue and
is self-explanatory. As new ROM programs are implemented, this diagnostic may be modifiea. However, the basic
version may be used on
all option variations as long as the user visually checks the ROM data following the first pass.
The diagnostic contains the instructions for its own operation. The opening dialogue establishes which option
variation
(-Y A, -YB, etc.) is being tested.
2-3

CHAPTER 3
PROGR,AMMING
This device is a Read-Only Memory and requires no programming. However, certain factors must be considered in
system programming
as the following paragraphs explain.
3.1 POWER FAIL PROGRAMMING
With the BM873 option installed, the power-down/power-up routines may require modification, depending on the
bootstrap used.
Use of the external interface causes the power-fail sequence in the CPU when AC La is detected
going low; the power-up trap program
is not used, and, therefore, not restored.
This
is not a problem when a bootstrap loads into core and overwrites location 24, because the new program will set
up the power-fail routine. However, if the new program does not reload location 24, the next power-fail sequence
(may be real)
will find the power-up restore program instead of the power-down routine.
This condition can be resolved by the power-fail routine testing this option with any DATI instruction. The
combination
of this option and a real power-fail will cause the DATI to perform in a normal manner. The
combination
of this option and the external interface active (causing the AC La and trap) will cause a nonexistent
device trap (no SSYN)
to location 4.
MOV
#lS,@#4 ; TRAP CATCHER
CLR @#6
TST @#173000
;DEV BLIND?
NOP
2S:
MOV
#PWRUP ,@#24 ; REAL PWR FAIL
(SAVE ROUTINE)
IS: HALT
Example 1
The above program works because this option goes "blind" (will not return SSYN) when it has been activated by
an
external interface signal. This condition continues from the assertion of AC La until the release of DC La.
3.2 REGISTER DESCRIPTION
There are no registers in this device. There are four flip-flops that can be loaded for diagnostic purposes but they
cannot
be read.
3-1

4.1 USER CUSTOM PROGRAM
CHAPTER 4
OPTIONS
Two etched circuit positions on the board provide an extra 128 words of ROM. To add this extra memory capacity,
Jumper 3 must be cut, permitting address recognition of all 256 words.
Figure 4-1 is a sample ROM program data sheet that can be helpful in programming the ROMs. Columns 1 and 2
contain the PDP-II program listing. From the address data in column 1, the ROM starting address can be determined
and the offset diodes cut (diode = 1; no diode =0). The data in column 2 must be expressed in binary form as in
columns 3 and 4. (Note that byte 1 is moved to the line below that of the original entry.) The eight binary digits for
each byte are then shifted into columns 5 and 6 under the ROM B and ROM A headings, respectively. Columns 7
and 8 contain the resulting
ROM address in binary and decimal form, respectively. Column 8 consists of four
columns
of decimal addresses, distinguished by the configuration of the 2 MSB of the binary address. Each program
data sheet contains 64 ROM locations (32 words), hence four sheets are required to encode all 128 words.
Therefore, only one of the four subcolumns of decimal addresses actually applies for each sheet, and the other three
should be crossed out to avoid confusion. The 2-colurnn checklist between columns 7 and 8 can be used for checkoff
purposes, e.g., checking off ROMs as they are blasted.
A blank program data sheet is included in Chapter 6 to assist the user in programming the read-only memory of the
BM873.
Customers who wish to create their own programs can purchase PROMs from integrated circuit vendors or
distributors. Some distributors have programming capabilities so that programmed ROMs can be purchased. The
following PROMs have been found acceptable:
Intersil type 5603A
Monolithic Memories Inc. type 6300
The following PROMs have not been tested but according to the manufacturer's data should be acceptable. Any
PROM that is specified to be "pin compatible with the 74187" should work in this application.
National Semiconductor type DM8573
Signetics type 82S26
4-1

Program Listing Octal List
Addr. Data Byte
"1" Byte "0"
I I "III I I I I I I I
II I I II I II II I III
17.3000:0107
0
2,.
/I
000 010
0
001 000 I
173001..IOOO~.)S"
00 101 10I
I 0
000 000 I
113 OOif. : [7 7 4-" ~
00 I/O 010
I
ttl 1/1 I
173006 '000005
00 000 lot
o 000 ~oo 0
113010'ot010l.
1/ 000 010
o 001 O~o I
/130 I 'J.. 10004'51
00 10
1
001
o 000 000 I
.-t.:z.l. 0 lif : 171 if 0 fD
00 oot:) 110
I
--l..l...J It IJI I
I
'--
~
I
Ir
~
~
1730"(" 10004-1.3
vO 010 011
o 00000
0 I
17307011167/('
If 001
110
J 11/110/
I7J07J. 'OOOOOS
00 000 101
0000 oDe 0
11307q.. 10/070l
1/ 000 010
000/ 000 I
17307Ct1 00O~/7
00
001 III
! o
000 000 I
ROM Program Data Sheet - 32
10
Word Block
ROM "B" ROM "A"
ROM Addr.
3 2 1 0 3 2 1 0 5 4 3 2 1 0 A B
I I 0 0 00 10
o 0 0 0 0 0
II
V
00 0 /
0001
1 V V
00 I C>
I I o I o 0 0 0 1 0 v'
v
0000 00 0 I 1
V- II"
00
I I
00 I 0
000
1 o 0 v
I I I , I I I I 1 V'
o 0 o 0 o J 0 I
000
1 1 0 v'
00
o 0
0000
1 V
I J o 0 0010
o 0 1 o 0 0
./
00
01
0001
1 v
00
I 0 I
00 I o 0 1 o 1 0
v'
0000
000/
1
.,/
0000
o I I 0 o 0 1 1 0 0
./
II I ( I I I I 1
~
~
0000
_Q....D..J--'""
-.......c:,
o~
;.0....
0001
-
r-rTOII0
.,/
~
0000
000 I 1
tI
II 00
/II
0 1 1 1
000
vi'
II ( I I I 0 I 1
,/
0000
010 I 1 1 1
010
./
0000
0000
1 V
1/ {J ()
00/0
1 I 1 1 o 0
./
0001
() 0 0 I 1 II"
0000 I I ! I 1 1 1 1 1 0
v"':
0000 000/
1 -/
Figure 4-1 Sample ROM Program Data Sheet
Sheet
of 4
1
234
t t T T
Address Bits 7 & 6
76 76 76 76
00 01 10 11
0
64 128
192
1
65 129
193
2
66 130 194
3
67
131 195
4
68 132 196
5
69
133 197
6
70
134
198
7
71 135 199
8 72
136
200
9
73 137
201
10
74 138
202
11 75
139 203
12
76 140
204
13
77
141
205
14
~
-~
I
I
,
......-rT8
182
,
~,
55 119
183
247
56 120 184
248
57
121 185
249
58 122 186
250
59
123
187
251
60
124
188 252
61
125
189
253
62
126
190
254
63 127
191
255
Choose one
of four
sheets. Cross
out the
other three
address lists.

CHAPTER 5
INTERFACE
The external interface consists of four separate high-impedance receivers with 4.7·,kilohm resistors in series with each
one. A -15 V source is provided through 10 kilohms to facilitate the use of contact closures. The external interface
also accepts single-ended voltage inputs. A signal of 0.5 rnA at -4 V or greater will cause a Restart sequence. The
maximum permissible input
is ±25 V,
These inputs are filtered with RC networks and Schmitt triggers and have a time delay of approximately 10 to
15 ms. The signal must remain for at least 45 ms. Only one external line may be active at a time; two or more active
at the time of the sample will cause a race condition until one wins, but the result will be indeterminate.
The interface connector
is an 8-pin male Mate-N-Lok (DEC Part Number 12-09340-01). Five pins (DEC Part Number
12-09378) are required for connection--nl<tced as shown in Figure 2-1.
5-1