Xilinx KCU116 User manual

KCU116 Evaluation Board
User Guide
UG1239 (v1.2) September 28, 2018

KCU116 Board User Guide 2
UG1239 (v1.2) September 28, 2018 www.xilinx.com
Revision History
The following table shows the revision history for this document.
Date Version Revision
09/28/2018 1.2 Updated DDR4 Component Memory and Regulatory and Compliance
Information. Added Electrostatic Discharge Caution.
05/03/2018 1.1 Updated Figure 3-19 and Table 3-18.
06/08/2017 1.0.2 Typographical update.
05/15/2017 1.0.1 Typographical update.
05/12/2017 1.0 Initial Xilinx release.
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Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Chapter 1: Introduction
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Board Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Board Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Environmental . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Operating Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Chapter 2: Board Setup and Configuration
Electrostatic Discharge Caution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Board Component Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Default Switch and Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Installing the KCU116 Board in a PC Chassis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
FPGA Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Chapter 3: Board Component Descriptions
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Component Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Kintex UltraScale+ XCKU5P-2FFVB676E Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
DDR4 Component Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Dual Quad SPI Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Micro-SD Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
USB JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
FMC Connector JTAG Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Programmable MGT User Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
User SMA Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Jitter Attenuated Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Video Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
GTY Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
PCI Express Endpoint Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
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zSFP/zSFP+ Module Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
10/100/1000 Mb/s Tri-Speed Ethernet PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Ethernet PHY Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Dual USB-to-UART Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
HDMI Video Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Status and User LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
User I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
User GPIO LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
User Pushbuttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
User SMA GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
CPU Reset Pushbutton . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
GPIO DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
User Pmod GPIO Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Program_B Pushbutton Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
FPGA Mezzanine Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
FMC HPC Connector J5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
KCU116 Board Power System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
SYSMON Header J93 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
System Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Appendix A: VITA 57.1 FMC Connector Pinout
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Appendix B: Xilinx Constraints File
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Appendix C: Regulatory and Compliance Information
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
CE Directives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
CE Standards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Electromagnetic Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Appendix D: Additional Resources and Legal Notices
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Solution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Documentation Navigator and Design Hubs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
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Chapter 1
Introduction
Overview
The KCU116 evaluation board for the Xilinx®Kintex®UltraScale+™FPGA provides a
hardware environment for developing and evaluating designs targeting the UltraScale+
XCKU5P-2FFVB676E device. The KCU116 evaluation board provides features common to
many evaluation systems, including:
• DDR4 component memory
• High-definition multimedia interface (HDMI™)
• Four zSmall form-factor pluggable plus (zSFP+) connectors
• Eight-lane PCI Express®interface
• Ethernet PHY
• General purpose I/O
•TwoUARTinterfaces
Other features can be supported using VITA-57.1 FPGA mezzanine cards (FMC) attached to
the high pin count (HPC) FMC connector.
Additional Resources
See Appendix D, Additional Resources and Legal Notices for references to documents, files,
and resources relevant to the KCU116 evaluation board.
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Chapter1: Introduction
Block Diagram
A block diagram of the KCU116 evaluation board is shown in Figure 1-1.
Board Features
The KCU116 evaluation board features are listed in this section. Detailed information for
each feature is provided in Component Descriptions in Chapter 3.
• Kintex UltraScale+ XCKU5P-2FFVB676E FPGA
•Zynq
®SoC XC7Z010 based system controller with micro secure digital (SD) connector
X-Ref Target - Figure 1-1
Figure1‐1: KCU116 Evaluation Board Block Diagram
86
HD
87
HD
67
HP
X18245-120916
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Chapter1: Introduction
• 1 GB DDR4 component memory (two [256 Mb x 16] devices)
• Two 256 Mb quad serial peripheral interface (QSPI) flash memory (dual Quad SPI)
• USB JTAG interface via Digilent module with micro-B USB connector
• Clock sources:
°SI5335A quad clock generator
°SI5328A programmable clock multiplier and jitter attenuator
°Si570 I2C programmable LVDS clock generator
°Subminiature version A (SMA) connectors (differential)
• 16 GTY transceivers (four Quads)
°FMC HPC connector (four GTY transceivers)
°8-lane PCI Express (eight GTY transceivers)
°Four zSFP+ connectors (four GTY transceivers)
•PCIe
®endpoint connectivity
°Gen1 8-lane (x8)
°Gen2 8-lane (x8)
°Gen3 8-lane (x8)
• Four zSFP+ connectors in a 1 high x 4 wide form-factor cage
• Ethernet PHY SGMII interface with RJ-45 connector
• Dual USB-to-UART bridge with micro-B USB connector
• HDMI output codec with HDMI type-A connector
•I
2C bus
•StatusLEDs
•UserI/O
• Program_B pushbutton
•Pmodheaders
• VITA 57.1 FMC HPC connector J5
• Power on/off slide switch SW1
• Power management with PMBus voltage monitoring through Maxim power controllers
and GUI
• Single 10-bit 0.2 MSPS ADC system monitor (SYSMON) analog-to-digital front end
• Configuration options:
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Chapter1: Introduction
°Dual Quad SPI flash memory
°Micro-B USB J2 JTAG configuration port (Digilent module)
°Platform cable header J8 JTAG configuration port
Board Specifications
Dimensions
Height: 6.927 inch (17.59 cm)
Thickness (±5%): 0.061 inch (0.1549 cm)
Length: 9.5 inch (24.13 cm)
Note: A 3D model of this board is not available.
IMPORTANT: The KCU116 board height exceeds the standard 4.376 inch (11.15 cm) height of a PCI
Express card.
Environmental
Temperature
Operating: 0°C to +45°C
Storage: -25°C to +60°C
Humidity
10% to 90% non-condensing
Operating Voltage
+12 VDC
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Chapter 2
Board Setup and Configuration
Electrostatic Discharge Caution
CAUTION! ESD can damage electronic components when they are improperly handled, and can result
in total or intermittent failures. Always follow ESD-prevention procedures when removing and
replacing components.
To prevent ESD damage:
• Use an ESD wrist or ankle strap and ensure that it makes skin contact. Connect the
equipment end of the strap to an unpainted metal surface on the chassis.
• Avoid touching the adapter against your clothing. The wrist strap protects components
from ESD on the body only.
• Handle the adapter by its bracket or edges only. Avoid touching the printed circuit
board or the connectors.
• Put the adapter down only on an antistatic surface such as the bag supplied in your kit.
• If you are returning the adapter to Xilinx Product Support, place it back in its antistatic
bag immediately.
Board Component Location
Figure 2-1 shows the KCU116 board component locations. Each numbered component
shown in the figure is keyed to Table 2-1. Table 2-1 identifies the components, references
the respective schematic page numbers, and links to a detailed functional description of the
components and board features in Chapter 3.
IMPORTANT: Figure 2-1 is for visual reference only and might not reflect the current revision of the
board.
CAUTION! The KCU116 board can be damaged by electrostatic discharge (ESD). Follow standard ESD
prevention measures when handling the board.
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Chapter2: Board Setup and Configuration
X-Ref Target - Figure 2-1
Figure2‐1: KCU116 Evaluation Board Components
18
5
27
10 9
36
37
34
14
15
6
12
20 21
25
7
13
38
28 29 23
32
31
30
22
4
17
16
26
24
33
33
19
35
33
8
11
1
2
00 Round callout references a component
on the front side of the board
Square callout references a component
on the back side of the board
00
5
X18418-041717
Table2‐1: KCU116 Board Component Descriptions
Callout Feature Notes
Schematic
Page
Number
1Kintex UltraScale+ XCKU5P-2FFVB676E Device,
(with fan-sink on soldered FPGA)
XCKU5P-2FFVB676E
Radian XLX041A
2DDR4 Component Memory, 1 GB (2x512 MB)
(U150, U153) Micron MT40A256M16GE-075E 18-19
3Dual Quad SPI Flash Memory (2x256 Mb) (U2-U3) Micron MT25QU01GBBB8ESF-0SIT
U2 on top, U3 on bottom of board 4, 6
4Micro-SD Card Interface, connector (J177) Molex 5025700893 on bottom of
board 35
5USB JTAG Interface (U21), with micro-B connector
(J2)
Digilent USB JTAG module
Hirose ZX62D_AB_5P8 17
6Clock Generation, multi-output clock generator,
SYSCLK and other clocks, 1.8V LVDS (U170)
SI5335A-B02436-GM, four outputs:
300 MHz, 125 MHz, 90 MHz,
33.33 MHz
36
7Programmable MGT User Clock,
I2C programmable user clock 3.3V LVDS (U56)
Silicon Labs SI570BAB0000544DG
(default 156.250 MHz) 37
8Jitter Attenuated Clock, (U20) Silicon Labs SI5328C-C-GM 28
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Chapter2: Board Setup and Configuration
9User SMA Clock, user differential SMA clock P/N
(J168/J169) Rosenberger 32K10K-400L5 37
10 User SMA GPIO, user SMA GPIO connectors P/N
(J178/J179) Rosenberger 32K10K-400L5 37
11 GTY Transceivers 224 and 225 Embedded within FPGA U1 10
12 GTY Transceivers 226 and 227 Embedded within FPGA U1 11
13 PCI Express Endpoint Connectivity, PCI Express®
connector (P1) 8-lane PCIe®card edge connector 20
14 zSFP/zSFP+ Module Connectors, connector SFP0
(J1), SFP3 (J6) top to bottom Molex 170382-0001 26
15 zSFP/zSFP+ Module Connectors, connector SFP2
(J4), SFP1 (J3) top to bottom Molex 170382-0001 27
16 10/100/1000 Mb/s Tri-Speed Ethernet PHY w/RJ45,
SGMII mode only, (U12, P3)
TI DP83867ISRGZ
Wurth 7499111221A 39
17 Ethernet PHY Status LEDs, LEDs are integrated into
P3 bezel
Wurth 7499111221A
with integrated status LEDs 39
18 Dual USB-to-UART Bridge, bridge (U166, adjacent
to SW21 item 27) with micro-B connector (J164)
Silicon Labs CP2105-F01-GM bridge,
Hirose ZX62D-AB-5P8 connector 38
19 HDMI Video Output, HDMI™codec (U5),
HDMI connector (P2)
Analog Devices ADV7511KSTZ-P
Molex 47151-0011 29, 30
20 I2C Bus, MUX (U34, U135) TI TCA9548APWR 42
21 I2C Bus, GPIO peripheral (U147) TI TCA6416APWR 42
22 User GPIO LEDs, (DS37-DS44) GPIO LEDs, GREEN 0603
Lumex SML-LX0603GW-TR 40
23 User Pushbuttons, active-High (SW14-SW16, SW18,
SW22)
E-Switch TL3301EF100QG in north,
south, east, west, center pattern 40
24 CPU Reset Pushbutton, user CPU RESET,
active-High (SW17) E-Switch TL3301EF100QG 40
25 GPIO DIP Switch, 4-pole, active-High (SW13) C&K SDA04H1SBD 40
26 Program_B Pushbutton Switch,
FPGA PROG pushbutton, active-Low (SW5) E-Switch TL3301EF100QG 3
27 Switches, system controller MODE DIP switch,
6-pole, active-High (SW21) C&K SDA06H1SBD 34
28 User Pmod GPIO Headers, female right-angle
receptacle, 2X6 (J55) Sullins PPPC062LJBN-RC 41
29 User Pmod GPIO Headers, vertical male header,
2x6 0.1 inch (J87) Sullins PBC36DAAN 41
30 Power On/Off Slide Switch SW1 C&K 1201M2S3AQE2 44
31 Switches, 12V power input 2x6 connector (J52) MOLEX-39-30-1060 44
Table2‐1: KCU116 Board Component Descriptions (Cont’d)
Callout Feature Notes
Schematic
Page
Number
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Chapter2: Board Setup and Configuration
Default Switch and Jumper Settings
Switches
Default switch settings are listed in Table 2-2. Switch locations are shown in Figure 2-1.
Table 2-2 also references the respective schematic page numbers.
32 Monitoring Voltage and Current, 2x8 shrouded
PMBus connector (J84) ASSMAN AWHW16G-0202 43
33 KCU116 Board Power System, power management
system (top and bottom)
Maxim MAX15301, MAX15303 and
MAX20751 Digital P.O.L. controllers 44-58
34 FMC HPC Connector J5 Samtec ASP_134486_01 21-24
35 SYSMON Header J93, 2X6 shrouded (J93) Molex 70246-1201 4
36 System Controller
Zynq®-7000 AP SoC XC7Z010CLG225 (U161) XC7Z010CLG225 on bottom of board 31-34
37 USB JTAG Interface, 2x7 2 mm shrouded JTAG cable
connector (J8) Molex 87832-1420 17
38 Encryption Key Battery Backup Circuit (B1) Seiko TS518FE-FL35E 3
Table2‐1: KCU116 Board Component Descriptions (Cont’d)
Callout Feature Notes
Schematic
Page
Number
Table2‐2: Default Switch Settings
Switch Function Default Comments Figure 2‐1
Callout
Schematic
Page
SW1 SPST slide switch OFF Board shipped with power switch off 1 44
SW13 4-pole GPIO DIP 0,0,0,0 Positions 1-4, GPIO 2 40
SW21 6-pole configuration DIP 0,0,0,0,0 Positions 1-5, Zynq-7000 AP SoC System
Controller U161 334
SW21 6-pole configuration DIP 0 Position 6 FPGA U1 mode M2 3 34
Notes:
1. DIP switches are active-High (connected net is pulled High when DIP switch is closed=1).
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Chapter2: Board Setup and Configuration
Jumpers
Figure 2-2 shows the KCU116 board jumper header locations. Each numbered component
shown in the figure is keyed to Table 2-3, which identifies the default jumper settings and
references the respective schematic page numbers.
X-Ref Target - Figure 2-2
Figure2‐2: KCU116 Board Header Jumper Locations
94
8
5
611
12
2
710
14
3
13
1
X18420-120916
Table2‐3: Default Jumper Settings
Jumper Function Default Comments Figure 2‐2
Callout
Schematic
Page
J7 PCIe lane size select 5-6 8-lane configuration 4 20
J12 SYSMON_VP 1-2 U1 VP pin P13 pull down 20.5K to GND 5 3
J13 SYSMON_VN 1-2 U1 VN pin R14 pull down 20.5K to GND 6 3
J16 zSFP0 TX enable Off Disable zSFP0 TX, allow FPGA control 7 26
J17 zSFP1 TX enable Off Disable zSFP1 TX, allow FPGA control 8 26
J42 zSFP2 TX enable Off Disable zSFP2 TX, allow FPGA control 9 27
J54 zSFP3 TX enable Off Disable zSFP3 TX, allow FPGA control 10 27
J85 POR override 2-3 U1 POR_OVERRIDE pin Y12 to GND 11 3
J90 SYSMON_VREFP select 1-2 SYSMON_VREFP = U64 1.25V VREF 12 3
J153 Maxim regulator inhibit Off Used only when programming power
system 13 44
J165 System controller boot Off On = force Zynq-7000 AP SoC to boot in
JTAG mode on power-up or reset 14 32
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Chapter2: Board Setup and Configuration
Installing the KCU116 Board in a PC Chassis
Installation of the KCU116 board inside an ATX-type computer chassis is required when
developing or testing PCI Express functionality. When the KCU116 board is installed in the
PCIe slot, power is provided from the ATX power supply 4-pin peripheral connector through
the ATX adapter cable (Figure 2-3), which is plugged into J52 on the KCU116 board. The
Xilinx®part number for this cable is 2600304. See [Ref 35] for ordering information.
To install the KCU116 board in a PC chassis:
1. On the KCU116 board, remove the six screws retaining the six rubber feet with their
standoffs, and the PCIe bracket. Reinstall the PCIe bracket using two of the previously
removed screws.
2. Power down the host computer and remove the power cord from the PC.
3. Open the PC chassis following the instructions provided with the PC.
4. Select a vacant PCIe expansion slot and remove the expansion cover (at the back of the
chassis) by removing the screws on the top and bottom of the cover.
5. Plug the KCU116 board into the PCIe connector at this slot.
6. Install the top mounting bracket screw into the PC expansion cover retainer bracket to
secure the KCU116 board in its slot.
IMPORTANT: The KCU116 board is taller than standard PCIe cards. Ensure that the height of the card
is free of obstructions.
7. Connect the ATX power supply to the KCU116 board using the ATX power supply
adapter cable as shown in Figure 2-3.
a. Plug the 6-pin 2 x 3 Molex connector on the adapter cable into J52 on the KCU116
board.
b. Plug the 4-pin 1 x 4 peripheral power connector from the ATX power supply into the
4-pin adapter cable connector.
X-Ref Target - Figure 2-3
Figure2‐3: ATX Power Supply Adapter Cable
To ATX 4-Pin Peripheral
Power Connector
To J52 on KCU116 Board
X18419-120916
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Chapter2: Board Setup and Configuration
CAUTION! Do NOT plug a PC ATX power supply 6-pin connector into J52 on the KCU116 evaluation
board. The ATX 6-pin connector has a different pin out than J52. Connecting an ATX 6-pin connector
into J52 damages the KCU116 evaluation board and voids the board warranty.
8. Slide the KCU116 board power switch SW1 to the ON position. The PC can now be
powered on.
FPGA Configuration
The KCU116 board supports two of the five UltraScale™FPGA configuration modes:
• Quad SPI flash memory
•JTAGusing:
°USB JTAG configuration port (Digilent module U21)
°Platform cable header J8
Each configuration interface corresponds to one or more configuration modes and bus
widths, as listed in Table 2-4. The FPGA mode pins M1 and M0 are hard wired to logic 0 and
1, respectively. The FPGA mode pin M2 is wired to SW21 pin 6 (switch position 6), which has
the default setting OPEN, enabling the M2 net to be pulled down to logic 0 (e.g., the FPGA
default mode setting M[2:0] = 001), selecting the Quad SPI configuration mode.
For complete details on configuring the FPGA, see UltraScale Architecture Configuration
User Guide (UG570) [Ref 3].
Table2‐4: Configuration Modes
Configuration Mode M[2:0] Bus Width CCLK Direction
Master SPI 001 x1, x2, x4 FPGA output
JTAG 101 x1 Not applicable
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Chapter 3
Board Component Descriptions
Overview
This chapter provides a detailed functional description of the board’s components and
features. Table 2-1, page 10 identifies the components, references the respective schematic
page numbers, and links to the corresponding detailed functional description in this
chapter. Component locations are shown in Table 2-1, page 10.
Component Descriptions
Kintex UltraScale+ XCKU5P‐2FFVB676E Device
[Figure 2-1, callout 1]
The KCU116 board is populated with the Kintex®UltraScale+™XCKU5P-2FFVB676E device.
For more information on Kintex UltraScale+ FPGAs, see Kintex UltraScale+ FPGAs Data
Sheet: DC and AC Switching Characteristics (DS922) [Ref 1].
Encryption Key Battery Backup Circuit
The XCKU5P device U1 implements bitstream encryption key technology. The KCU116
board provides the encryption key backup battery circuit shown in Figure 3-1. The Seiko
TS518FE rechargeable 1.5V lithium button-type battery B1 is soldered to the board with the
positive output connected to the XCKU5P device U1 VCCBATT pin Y9. The battery supply
current IBATT specification is 150 nA maximum when the board power is off. B1 is charged
from the SYS_1V8 1.8V rail through a series diode with a typical forward voltage drop of
0.38V and 4.7 Kcurrent limit resistor. The nominal charging voltage is 1.42V.
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Chapter3: Board Component Descriptions
X-Ref Target - Figure 3-1
Figure3‐1: Encryption Key Backup Circuit
X18285-120916
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Chapter3: Board Component Descriptions
I/O Voltage Rails
There are seven I/O banks available on the XCKU5P device and the KCU116 board. The
voltages applied to the FPGA I/O banks (shown in Figure 3-2) used by the KCU116 board are
listed in Table 3-1.
X-Ref Target - Figure 3-2
Figure3‐2: UltraScale+ XCKU5P Bank Locations
Table3‐1: I/O Bank Voltage Rails
FPGA (U1) Bank Power Supply Rail Net Name Voltage
Bank 0 VCC1V8 1.8V
HP Bank 64 VADJ_FMC 1.8V (default)
HP Bank 65 VCC1V8 1.8V
HP Bank 66 VCC1V2 1.2V
HP Bank 67 VCC1V2 1.2V
HP Bank 84 VCC3V3 3.3V
HR Bank 86 VCC3V3 3.3V
HR Bank 87 VCC3V3 3.3V
X18286-120916
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Chapter3: Board Component Descriptions
DDR4 Component Memory
[Figure 2-1, callout 2]
The 1 GB DDR4 component memory system is comprised of two 512 MB DDR4 SDRAM
devices located at U150 and U153.
• Manufacturer: Micron
• Part Number: MT40A256M16GE-075E
•Description:
°4 Gb (256 Mb x 16)
°1.2V 96-ball TFBGA
°DDR4-2666
The KCU116 XCKU5P FPGA DDR memory interface performance is documented in the
Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics (DS922) [Ref 1].
This memory system is connected to the XCKU5P device HP banks 66 and 67.
The DDR4 0.6V VTT termination voltage (net DDR4_VTT) is sourced from the TI TPS51200DR
linear regulator U35. The connections between the DDR4 component memories and
XCKU5P device banks 66 and 67 are listed in Table 3-2.
The 1 GB DDR4 component memory system comprises two 512 MB DDR4 SDRAM devices
(Micron MT40A256M16GE-075E) located at U150 and U153. This memory system is
connected to the XCKU5P device HP banks 66 and 67. The DDR4 0.6V VTT termination
voltage (net DDR4_VTT) is sourced from the TI TPS51200DR linear regulator U35. The
connections between the DDR4 component memories and XCKU5P device banks 66 and 67
are listed in Table 3-2.
Table3‐2: DDR4 Memory Connections to the FPGA
FPGA (U1)
Pin
Schematic Net
Name I/O Standard Component Memory
Pin # Pin Name Ref. Des.
C22 DDR4_DQ0 POD12_DCI G2 DQL0 U150
B24 DDR4_DQ1 POD12_DCI F7 DQL1 U150
C23 DDR4_DQ2 POD12_DCI H3 DQL2 U150
A24 DDR4_DQ3 POD12_DCI H7 DQL3 U150
D21 DDR4_DQ4 POD12_DCI H2 DQL4 U150
B22 DDR4_DQ5 POD12_DCI H8 DQL5 U150
E21 DDR4_DQ6 POD12_DCI J3 DQL6 U150
A25 DDR4_DQ7 POD12_DCI J7 DQL7 U150
A19 DDR4_DQ8 POD12_DCI A3 DQU0 U150
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Chapter3: Board Component Descriptions
C17 DDR4_DQ9 POD12_DCI B8 DQU1 U150
A20 DDR4_DQ10 POD12_DCI C3 DQU2 U150
B17 DDR4_DQ11 POD12_DCI C7 DQU3 U150
B20 DDR4_DQ12 POD12_DCI C2 DQU4 U150
A15 DDR4_DQ13 POD12_DCI C8 DQU5 U150
B19 DDR4_DQ14 POD12_DCI D3 DQU6 U150
B15 DDR4_DQ15 POD12_DCI D7 DQU7 U150
C21 DDR4_DQS0_T DIFF_POD12_DCI G3 DQSL_T U150
B21 DDR4_DQS0_C DIFF_POD12_DCI F3 DQSL_C U150
A17 DDR4_DQS1_T DIFF_POD12_DCI B7 DQSU_T U150
A18 DDR4_DQS1_C DIFF_POD12_DCI A7 DQSU_C U150
A22 DDR4_DM0 POD12_DCI E7 DML_B/DBIL_B U150
C18 DDR4_DM1 POD12_DCI E2 DMU_B/DBIU_B U150
F18 DDR4_DQ16 POD12_DCI G2 DQL0 U153
G21 DDR4_DQ17 POD12_DCI F7 DQL1 U153
F19 DDR4_DQ18 POD12_DCI H3 DQL2 U153
D20 DDR4_DQ19 POD12_DCI H7 DQL3 U153
E18 DDR4_DQ20 POD12_DCI H2 DQL4 U153
D19 DDR4_DQ21 POD12_DCI H8 DQL5 U153
G20 DDR4_DQ22 POD12_DCI J3 DQL6 U153
D18 DDR4_DQ23 POD12_DCI J7 DQL7 U153
H17 DDR4_DQ24 POD12_DCI A3 DQU0 U153
D16 DDR4_DQ25 POD12_DCI B8 DQU1 U153
G16 DDR4_DQ26 POD12_DCI C3 DQU2 U153
D15 DDR4_DQ27 POD12_DCI C7 DQU3 U153
E15 DDR4_DQ28 POD12_DCI C2 DQU4 U153
C16 DDR4_DQ29 POD12_DCI C8 DQU5 U153
H16 DDR4_DQ30 POD12_DCI D3 DQU6 U153
G17 DDR4_DQ31 POD12_DCI D7 DQU7 U153
F20 DDR4_DQS2_T DIFF_POD12_DCI G3 DQSL_T U153
E20 DDR4_DQS2_C DIFF_POD12_DCI F3 DQSL_C U153
E16 DDR4_DQS3_T DIFF_POD12_DCI B7 DQSU_T U153
E17 DDR4_DQS3_C DIFF_POD12_DCI A7 DQSU_C U153
Table3‐2: DDR4 Memory Connections to the FPGA (Cont’d)
FPGA (U1)
Pin
Schematic Net
Name I/O Standard Component Memory
Pin # Pin Name Ref. Des.
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