Xilinx KC724 IBERT User manual

KC724 IBERT
Getting Started Guide
(ISE Design Suite 14.3)
UG930 (v1.0) October 23, 2012
This document applies to the following software versions: ISE Design Suite 14.3 and 14.4This document applies to the following software versions: ISE Design Suite 14.3 and 14.4This document applies to the following software versions: ISE Design Suite 14.3 and 14.4This document applies to the following software versions: ISE Design Suite 14.3 and 14.4

KC724 IBERT Getting Started Guide www.xilinx.com UG930 (v1.0) October 23, 2012
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Revision History
The following table shows the revision history for this document.
Date Version Revision
10/23/12 1.0 Initial Xilinx release.

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Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Chapter 1: KC724 IBERT Getting Started Guide
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Setting Up the KC724 Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Extracting the Project Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Running the GTX IBERT Demonstration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Connecting the GTX Transceivers and Reference Clocks . . . . . . . . . . . . . . . . . . . . . . . . 7
Attach the GTX Quad Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
GTX Transceiver Clock Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
GTX TX/RX Loopback Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Configuring the FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Setting Up the ChipScope Pro Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Starting the SuperClock-2 Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Viewing GTX Transceiver Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
In Case of RX Bit Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Closing the IBERT Demonstration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
SuperClock-2 Frequency Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Creating the GTX IBERT Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Appendix A: Warranty
Table of Contents

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Overview
Chapter 1
KC724 IBERT Getting Started Guide
Overview
This document provides a procedure for setting up the KC724 Kintex™-7 FPGA
GTX Transceiver Characterization Board to run the Integrated Bit Error Ratio Test (IBERT)
demonstration using the ISE Design Suite. The designs that are required to run the IBERT
demonstration are stored in a Secure Digital (SD) memory card that is provided with the
KC724 board. The demonstration shows the capabilities of the Kintex-7 XC7K325T FPGA
GTX transceiver.
The KC724 board is described in detail in UG932, KC724 Kintex-7 FPGA GTX Transceiver
Characterization Board User Guide.
The IBERT demonstrations operate one GTX Quad at a time. The procedure consists of:
1. Setting Up the KC724 Board.
2. Extracting the Project Files.
3. Connecting the GTX Transceivers and Reference Clocks.
4. Configuring the FPGA.
5. Setting Up the ChipScope Pro Software.
6. Viewing GTX Transceiver Operation.
7. Closing the IBERT Demonstration.

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Chapter 1: KC724 IBERT Getting Started Guide
Requirements
The hardware and software required to run the GTX IBERT demonstrations are:
• KC724 Kintex-7 FPGA GTX Transceiver Characterization Board including:
• One SD card containing the IBERT demonstration designs
•OneSamtecBullsEyecable
• Eight SMA female-to-female (F-F) adapters
•Six50ΩSMA terminators
• GTX transceiver power supply module (installed on board)
• SuperClock-2 module, Rev 1.0 (installed on board)
•ActiveBGAHeatsink(installed on FPGA)
• 12V DC power adapter
• USB cable, standard-A plug to micro-B plug
• Host PC with:
• SD card reader
•USBports
• Xilinx® ChipScope™ Pro software, version 14.3 or higher.
Software is available at: http://www.xilinx.com/chipscopepro
The hardware and software required to rebuild the IBERT demonstration designs are:
• Xilinx ISE® Design Suite version 14.3 or higher
• PC with a version of the Windows operating system supported by Xilinx ISE Design
Suite
Setting Up the KC724 Board
This section describes how to set up the KC724 board.
Caution! The KC724 board can be damaged by electrostatic discharge (ESD). Follow standard
ESD prevention measures when handling the board.
When the KC724 board ships from the factory, it is configured for the GTX IBERT
demonstrations described in this document. If the board has been re-configured it must be
returned to the default set-up before running the IBERT demonstrations.
1. Move all jumpers and switches to their default positions. The default jumper and
switch positions are listed in UG932, KC724 Kintex-7 FPGA GTX Transceiver
Characterization Board User Guide.
2. Install the GTX transceiver power module by plugging it into connectors J66 and J97.
3. Install the SuperClock-2 module:
a. Align the three metal standoffs on the bottom side of the module with the three
mounting holes in the SUPERCLOCK-2 MODULE interface of the KC724 board.
b. Using three 4-40 x 0.25 inch screws, firmly screw down the module from the
bottom of the KC724 board.
c. On the SuperClock-2 module, place a jumper across pins 2–3 (2V5) of the
CONTROL VOLTAGE header, J18, and place another jumper across Si570 INH
header J11.

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Extracting the Project Files
d. Screw down a 50ΩSMA terminator onto each of the six unused Si5368 clock
output SMA connectors: J7, J8, J12, J15, J16 and J17.
Extracting the Project Files
The ChipScope Pro Software .cpj project files for the IBERT demonstrations are located in
kc724_cpj.zip on the SD card provided with the KC724 board. They are also available
online along with .bit files for all four designs (as collection rdf0183_<ISE
version>.zip) at:
http://www.xilinx.com/kc724
kc724_cpj.zip contains four project files: kc724_q115.cpj,kc724_q116.cpj,
kc724_q117.cpj, and kc724_q118.cpj. These files are used to load pre-saved
MGT/IBERT and SuperClock-2 module control settings for the GTX demonstrations.
To copy the files from the Secure Digital memory card:
1. Connect the Secure Digital memory card to the host computer.
2. Locate the file kc724_cpj.zip on the Secure Digital memory card.
3. Unzip the files to a working directory on the host computer.
Running the GTX IBERT Demonstration
The GTX IBERT demonstration operates one GTX Quad at a time. This section describes
how to test GTX Quad 115. The remaining GTX Quads are tested following a similar series
of steps.
Connecting the GTX Transceivers and Reference Clocks
Figure 1-1 shows the locations for GTX transceiver Quads 115, 116, 117, and 118 on the
KC724 board.
Note: Figure 1-1 is for reference only and might not reflect the current revision of the board.

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All GTX transceiver pins and reference clock pins are routed from the FPGA to a connector
pad which interfaces with Samtec BullsEye connectors. Figure 1-2 Ashows the connector
pad. Figure 1-2 Bshows the connector pinout.
X-Ref Target - Figure 1-1
Figure 1-1: GTX Quad Locations
UG930_c1_01_061412
QUAD_116
QUAD_115 QUAD_118
QUAD_117

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Running the GTX IBERT Demonstration
The SuperClock-2 module provides LVDS clock outputs for the GTX transceiver reference
clocks in the IBERT demonstrations. Figure 1-3 shows the locations of the differential clock
SMA connectors on the clock module which can be connected to the reference clock cables.
Note: The image in Figure 1-3 is for reference only and might not reflect the current revision of the
board.
The four SMA pairs labeled CLKOUT provide LVDS clock outputs from the Si5368 clock
multiplier/jitter attenuator device on the clock module. The SMA pair labeled Si570_CLK
provides LVDS clock output from the Si570 programmable oscillator on the clock module.
Note: The Si570 oscillator does not support LVDS output on the Rev B and earlier revisions of the
SuperClock-2 module.
For the GTX IBERT demonstration, the output clock frequencies are preset to 125.000 MHz.
For more information regarding the SuperClock-2 module, refer to UG770,
HW-CLK-101-SCLK2 SuperClock-2 Module User Guide.
Attach the GTX Quad Connector
Before connecting the BullsEye cable assembly to the board, firmly secure the blue
elastomer seal provided with the cable assembly to the bottom of the connector housing if
X-Ref Target - Figure 1-2
Figure 1-2: A – GTX Connector Pad. B – GTX Connector Pinout
UG930_c1_02_101612
BGTX
GTX Connector Pinout
P
P
P
P
P
P
P
P
P
P
N
N
N
N
N
N
N
N
N
N
RX1
TX1
TX2
RX2
TX0
CLK1
RX3
TX3
CLK0
RX0
A
GTX Connector Pad
X-Ref Target - Figure 1-3
Figure 1-3: SuperClock-2 Module Output Clock SMA Locations
UG930_c1_03_061412
CLKOUT3_N
CLKOUT1_N
SI570_CLK_N
SI570_CLK_P CLKOUT1_P
CLKOUT2_N CLKOUT4_N
CLKOUT2_P CLKOUT3_P CLKOUT4_P

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it isn't already inserted (see Figure 1-4).
Note: Figure 1-4 is for reference only and might not reflect the current version of the connector.
Attach the Samtec BullsEye connector to GTX Quad 115 (Figure 1-5), aligning the two
indexing pins on the bottom of the connector with the guide holes on the board. Hold the
connector flush with the board and fasten it by tightening the two captive screws.
GTX Transceiver Clock Connections
Refer to Figure 1-2, page 9 to identify the P and N coax cables that are connected to the
CLK1 reference clock inputs. Connect these cables to the SuperClock-2 Module as follows:
• CLK1_P coax cable → SMA connector J5 (CLKOUT1_P) on the SuperClock-2 Module
• CLK1_N coax cable → SMA connector J6 (CLKOUT1_N) on the SuperClock-2 Module
Note: Any one of the five differential outputs from the SuperClock-2 Module can be used to source
the GTX reference clock. CLKOUT1_P and CLKOUT1_N are used here as an example.
X-Ref Target - Figure 1-4
Figure 1-4: BullsEye Connector with Elastomer Seal
X-Ref Target - Figure 1-5
Figure 1-5: BullsEye Connector Attached to Quad 115
UG930_c1_04_101112
UG930_c1_05_101112

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Running the GTX IBERT Demonstration
GTX TX/RX Loopback Connections
Refer to Figure 1-2, page 9 to identify the P and N coax cables that are connected to the four
receivers (RX0, RX1, RX2 and RX3) and the four transmitters (TX0, TX1, TX2 and TX3). Use
eight SMA female-to-female (F-F) adapters (Figure 1-6), to connect the transmit and
receive cables as shown in Figure 1-7 and detailed below:
•TX0_P→ SMA F-F Adapter → RX0_P
•TX0_N→ SMA F-F Adapter → RX0_N
•TX1_P→ SMA F-F Adapter → RX1_P
•TX1_N→ SMA F-F Adapter → RX1_N
•TX2_P→ SMA F-F Adapter → RX2_P
•TX2_N→ SMA F-F Adapter → RX2_N
•TX3_P→ SMA F-F Adapter → RX3_P
•TX3_N→ SMA F-F Adapter → RX3_N
X-Ref Target - Figure 1-6
Figure 1-6: SMA F-F Adapter
X-Ref Target - Figure 1-7
Figure 1-7: TX-To-RX Loopback Connection Example
UG930_c1_06_101112
RX Coax
TX Coax
SMA F-F Adapter
UG930_c1_07_101112

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Figure 1-8 shows the KC724 board with the cable connections required for the Quad 115
GTX IBERT demonstration.
Configuring the FPGA
This section describes how to configure the FPGA using the SD card included with the
board. The FPGA can also be configured through ChipScope Pro or iMPACT software
using the .bit files which are available online (as collection rdf0183_<ISE
version>.zip) at:
http://www.xilinx.com/kc724
To configure from the SD card:
1. Insert the SD card provided with the KC724 board into the SD card reader slot located
on the bottom-side (upper-right corner) of the board.
2. Plug the 12V output from the power adapter into connector J2.
3. Connect the host computer to the KC724 board using a standard-A plug to micro-B
plug USB cable. The standard-A plug connects to a USB port on the host computer and
the micro-B plug connects to U8, the Digilent USB JTAG configuration port on the
KC724 board.
X-Ref Target - Figure 1-8
Figure 1-8: Cable Connections for Quad 115 GTX IBERT Demonstration
UG930_c1_08_081412
TX/RX Loopback Connections
QUAD_115
CKOUT1_P
CKOUT1_N

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Running the GTX IBERT Demonstration
4. Select the GTX IBERT demonstration with the System ACE SD controller SASD CFG
switch, SW8. The setting on this 4-bit DIP switch (Figure 1-9) selects the file used to
configure the FPGA. A switch is in the ON position if set to the far right and in the OFF
position if set to the far left. For the Quad 115 GTX IBERT demonstration, set
ADR2 = ON, ADR1 = ON, and ADR0 = ON. The MODE bit (switch position 4) is not
used and can be set either ON or OFF.
There is one IBERT demonstration design for each GTX Quad on the KC724 board, for a
total of four IBERT designs. Four other demonstration designs are included that show
other board features (the use of these designs are described in the README file within the
SD card). All eight designs are organized and stored on the SD card as shown in Table 1-1.
5. Place the main power switch SW1 to the ON position.
Setting Up the ChipScope Pro Software
1. Start the ChipScope Pro analyzer tools on the host computer and select
File → Open Project.
2. When the Project window opens, navigate to the directory where the ChipScope
software project files (.cpj) were extracted. Select kc724_q115.cpj and click Open.
Note: The .cpj file loads pre-saved project settings for the demonstration including MGT/IBERT
and clock module control parameters. For more information regarding MGT/IBERT settings, refer
to UG029, ChipScope Pro Software Cores.
X-Ref Target - Figure 1-9
Figure 1-9: Configuration Address DIP Switch (SW8)
Table 1-1: SD Card Contents and Configuration Addresses
Demonstration
Design ADR2 ADR1 ADR0
GTXQuad115 ONONON
GTX Quad 116 ON ON OFF
GTX Quad 117 ON OFF ON
GTX Quad 118 ON OFF OFF
LED Scroll OFF ON ON
DIP Switches OFF ON OFF
Push Buttons OFF OFF ON
USB/UART OFF OFF OFF
UG930_c1_09_101112
ADR0
ADR1
ADR2
SASD CFG
234
SW8
1
MODE (Not Used)
ON

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3. Click the Open Cable button (Figure 1-10).
4. When the dialog appears asking to set up the core with the settings from the current
project, click Yes (Figure 1-11).
Starting the SuperClock-2 Module
The IBERT demonstration designs use an integrated ChipScope Pro software VIO core to
control the clocks on the SuperClock-2 module. The SuperClock-2 module features two
clock-source components: 1) An always-on Si570 crystal oscillator and, 2) an Si5368
jitter-attenuating clock multiplier. Outputs from either device can be used to drive the
transceiver reference clocks. To start the SuperClock-2 Module:
X-Ref Target - Figure 1-10
Figure 1-10: Open Cable Button
UG930_c1_10_101112
Open Cable Button
X-Ref Target - Figure 1-11
Figure 1-11: IBERT K7GTX Project Settings
ug930_c1_11_101112

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Running the GTX IBERT Demonstration
1. In the Project Panel, click VIO Console below UNIT 1: SCLK2 Control (VIO)
(Figure 1-12).
2. The clock sources on the SuperClock-2 module are controlled from the VIO Console.
Click on the Si5368 Start button (Figure 1-13) to enable the clock output.
Note: The ROM address values for the Si5368 and Si570 devices (i.e., Si5368 ROM Addr and
Si570 ROM Addr) are preset to 19 to produce an output frequency of 125.000 MHz. Entering a
different ROM address changes the reference clock(s) frequency. The complete list of
pre-programmed SuperClock-2 frequencies and their associated ROM addresses is provided in
Table 1-2, page 19.
X-Ref Target - Figure 1-12
Figure 1-12: Project Panel - VIO Console (GTX)
X-Ref Target - Figure 1-13
Figure 1-13: Si5368 Address, Frequency and Start Button
UG930_c1_12_101112
UG930_c1_13_101112
Si5368start button
The ROM address value for the
Si5368clock multiplier ispreset to 19
(125.000 MHz)

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3. In the project panel, click IBERT Console (Figure 1-14) to view GTX transceiver
operation.
Viewing GTX Transceiver Operation
After completing step 3 in Starting the SuperClock-2 Module, the IBERT demonstration is
configured and running. The status and test settings are displayed on the MGT/IBERT
Settings tab in the IBERT Console shown in Figure 1-15.
Note the line rate, TX differential output swing, and RX bit error count:
• The line rate for all four GTX transceivers is 12.5 Gbps (see MGT Link Status in
Figure 1-15).
• The GTX transmitter differential output swing is preset to 850 mV.
• Verify that there are no bit errors.
X-Ref Target - Figure 1-14
Figure 1-14: Project Panel - IBERT Console (GTX)
UG930_c1_14_101112

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Running the GTX IBERT Demonstration
In Case of RX Bit Errors
If the RX Bit Error Count for any transceiver displays a non-zero value, or to simply reset
the counter, click the respective BERT Reset button (Figure 1-16) to zero the count.
If the MGT Link Status shows No Link for one or more transceivers click the respective TX
Reset button followed by BERT Reset (Figure 1-17).
X-Ref Target - Figure 1-15
Figure 1-15: GTX IBERT Console
ug930_c1_15_061412
X-Ref Target - Figure 1-16
Figure 1-16: Click BERT Reset Button to Zero a Non-Zero RX Error Count
ug930_c1_16_101512

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Closing the IBERT Demonstration
To stop the IBERT demonstration:
1. Close the ChipScope application by selecting File → Exit.
Note: Do not save changes to the project.
2. Place the main power switch SW1 in the off position.
Additional information on the ChipScope Pro software and IBERT core can be found in:
•UG029, ChipScope Pro Software Cores.
•DS855, ChipScope Integrated Bit Error Ratio Test (IBERT) for Kintex-7 GTX (v2.00.a)
X-Ref Target - Figure 1-17
Figure 1-17: Click TX Reset then BERT Reset If MGT Link Status = No Link
ug930_c1_17_101512

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SuperClock-2 Frequency Table
SuperClock-2 Frequency Table
Table 1-2 lists the addresses for the frequencies that are programmed into the SuperClock-2
read-only-memory (ROM).
Table 1-2: Si570 and Si5368 Frequency Table
Address Protocol Frequency
(MHz) Address Protocol Frequency (MHz) Address Protocol Frequency (MHz)
0100GE/40GE/10
GE 161.130 30 OBSAI 307.200 60 XAUI 156.250
1 Aurora 81.250 31 OBSAI 614.400 61 XAUI 312.500
2 Aurora 162.500 32 OC-48 19.440 62 XAUI 625.000
3 Aurora 325.000 33 OC-48 77.760 63 Generic 66.667
4 Aurora 650.000 34 OC-48 155.520 64 Generic 133.333
5 CE111 173.370 35 OC-48 311.040 65 Generic 166.667
6 CPRI 61.440 36 OC-48 622.080 66 Generic 266.667
7 CPRI 122.880 37 OTU-1 166.629 67 Generic 333.333
8 CPRI 153.630 38 OTU-1 333.257 68 Generic 533.333
9 CPRI 245.760 39 OTU-1 666.514 69 Generic 644.000
10 CPRI 491.520 40 OTU-1 666.750 70 Generic 666.667
11 Display Port 67.500 41 OTU-2 167.330 71 Generic 205.000
12 Display Port 81.000 42 OTU-2 669.310 72 Generic 210.000
13 Display Port 135.000 43 OTU-3 168.050 73 Generic 215.000
14 Display Port 162.000 44 OTU-4 174.690 74 Generic 220.000
15 Fibrechannel 106.250 45 PCIe 100.000 75 Generic 225.000
16 Fibrechannel 212.500 46 PCIe 125.000 76 Generic 230.000
17 Fibrechannel 425.000 47 PCIe 250.000 77 Generic 235.000
18 GigE 62.500 48 SATA 75.000 78 Generic 240.000
19 GigE 125.000 49 SATA 150.000 79 Generic 245.000
20 GigE 250.000 50 SATA 300.000 80 Generic 250.000
21 GigE 500.000 51 SATA 600.000 81 Generic 255.000
22 GPON 187.500 52 SDI 74.250 82 Generic 260.000
23 Interlaken 132.813 53 SDI 148.500 83 Generic 265.000
24 Interlaken 195.313 54 SDI 297.000 84 Generic 270.000
25 Interlaken 265.625 55 SDI 594.000 85 Generic 275.000
26 Interlaken 390.625 56 SMPTE435M 167.063 86 Generic 280.000
27 Interlaken 531.250 57 SMPTE435M 334.125 87 Generic 285.000
28 OBSAI 76.800 58 SMPTE435M 668.250 88 Generic 290.000
29 OBSAI 153.600 59 XAUI 78.125 89 Generic 295.000

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Creating the GTX IBERT Core
To rebuild the designs shown here, you must have an installation of ISE Design Suite.
This section provides a procedure to create a single Quad GTX IBERT core using
CORE Generator software. The procedure assumes Quad 115 and 12.5 Gb/s line rate, but
cores for any of the GTX Quads with any supported line rate can be created following the
same series of steps.
For more details on generating IBERT cores, refer to UG029, ChipScope Pro Software Cores.
1. Start the CORE Generator tool from either the ISE Project Navigator window or a
command line:
• From the Project Navigator window, select: Tools → Core Generator…
• From a command line, enter: coregen
2. In the Core Generator window, click the New Project icon (highlighted in Figure.
Figure 1-18).
90 Generic 300.000 103 Generic 365.000 116 Generic 430.000
91 Generic 305.000 104 Generic 370.000 117 Generic 435.000
92 Generic 310.000 105 Generic 375.000 118 Generic 440.000
93 Generic 315.000 106 Generic 380.000 119 Generic 445.000
94 Generic 320.000 107 Generic 385.000 120 Generic 450.000
95 Generic 325.000 108 Generic 390.000 121 Generic 455.000
96 Generic 330.000 109 Generic 395.000 122 Generic 460.000
97 Generic 335.000 110 Generic 400.000 123 Generic 465.000
98 Generic 340.000 111 Generic 405.000 124 Generic 470.000
99 Generic 345.000 112 Generic 410.000 125 Generic 475.000
100 Generic 350.000 113 Generic 415.000 126 Generic 480.000
101 Generic 355.000 114 Generic 420.000 127 Generic 485.000
102 Generic 360.000 115 Generic 425.000
Table 1-2: Si570 and Si5368 Frequency Table (Cont’d)
Address Protocol Frequency
(MHz) Address Protocol Frequency (MHz) Address Protocol Frequency (MHz)