Xilinx Virtex-7 FPGA VC7222 IBERT User manual

Virtex-7 FPGA VC7215
Characterization Kit IBERT
Getting Started Guide
UG970 (Vivado Design Suite v2015.1) April 27, 2015

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UG970 (Vivado Design Suite v2015.1) April 27, 2015
Revision History
The following table shows the revision history for this document.
Date Version Revision
07/10/2013 1.0 Initial Xilinx release.
10/31/2013 2.0 Updated for Vivado® Design Suite 2013.3. Updated most figures in Chapter 1,
VC7215 IBERT Getting Started Guide. Figure 1-30 was renamed Design Sources
File Hierarchy. Figure 1-31, Synthesize Out-Of-Context Module was deleted. The
name of the project files ZIP file changed to
rdf0294-vc7215-ibert-2013-3.zip. Updated Appendix A, Additional
Resources and Legal Notices links.
12/18/2013 3.0 Updated for Vivado Design Suite 2013.4. Updated Figure 1-10 through
Figure 1-15. Updated Figure 1-19, Figure 1-20, Figure 1-23, Figure 1-27, and
Figure 1-28.
04/16/2014 4.0 Updated for Vivado Design Suite 2014.1. Updated most graphics in Chapter 1
from Figure 1-10 on. File lists changed under Extracting the Project Files. The ZIP
project file name changed to rdf0294-vc7215-ibert-2014-1.zip. The
section Launching Vivado Design Suite was changed to Setting Up Vivado Design
Suite. The section In Case of RX Bit Errors was added.
06/12/2014 5.0 Updated for Vivado Design Suite 2014.2. Updated Figure 1-10, Figure 1-11,
Figure 1-19, Figure 1-20, Figure 1-23, Figure 1-27, Figure 1-30, Figure 1-32,
Figure 1-33, and Figure 1-35. Updated Viewing GTH Transceiver Operation.
10/08/2014 6.0 Updated for Vivado Design Suite 2014.3. Updated Figure 1-10, Figure 1-11,
Figure 1-19, Figure 1-21, Figure 1-23, Figure 1-27, and Figure 1-33. Added device
programming information to Starting the SuperClock-2 Module. Updated In Case
of RX Bit Errors. C_USER_SCAN_CHAIN* was changed to 3 in Figure 1-33.
11/24/2014 7.0 Updated for Vivado Design Suite 2014.4. The name of the project files ZIP file
changed to rdf0294-vc7215-ibert-2014-4.zip. Updated Figure 1-10,
Figure 1-19, and Figure 1-23.
04/27/2015 2015.1 Updated for Vivado Design Suite 2015.1. The ZIP project file name changed to
rdf0294-vc7215-ibert-2015-1.zip. Updated Figure 1-4, Figure 1-10,
Figure 1-15, Figure 1-17, Figure 1-18, Figure 1-20, Figure 1-23, and Figure 1-27.
Version changed to match the software release.

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Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Chapter 1: VC7215 IBERT Getting Started Guide
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Setting Up the VC7215 Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Extracting the Project Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Running the GTH IBERT Demonstration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SuperClock-2 Frequency Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Creating the GTH IBERT Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Appendix A: Additional Resources and Legal Notices
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Solution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Appendix B: Warranty
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Chapter 1
VC7215 IBERT Getting Started Guide
Overview
This document provides a procedure for setting up the Virtex®-7 FPGA VC7215 GTH
Transceiver Characterization Board to run the Integrated Bit Error Ratio Test (IBERT)
demonstration using the Vivado® Design Suite. The designs required to run the IBERT
demonstrations are stored in three Secure Digital (SD) memory cards that are provided with
the VC7215 board. The demonstration shows the capabilities of the Virtex-7 XC7VX690T
FPGA GTH transceiver.
The VC7215 board is described in detail in VC7215 Virtex-7 FPGA GTH Transceiver
Characterization Board User Guide (UG972) [Ref 1].
The IBERT demonstrations operate one GTH Quad at a time. The procedure consists of:
1. Setting Up the VC7215 Board, page 6
2. Extracting the Project Files, page 7
3. Connecting the GTH Transceivers and Reference Clocks, page 8
4. Configuring the FPGA, page 14
5. Setting Up Vivado Design Suite, page 16
6. Starting the SuperClock-2 Module, page 19
7. Viewing GTH Transceiver Operation, page 25
8. Closing the IBERT Demonstration, page 26
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Chapter 1: VC7215 IBERT Getting Started Guide
Requirements
The hardware and software required to run the GTH IBERT demonstrations are:
• VC7215 Virtex-7 FPGA GTH Transceiver Characterization Board. Includes:
°Three SD cards labeled IBERT #1, IBERT #2, and IBERT#3 containing the IBERT
demonstration designs
°One Samtec BullsEye cable
°Eight SMA female-to-female (F-F) adapters
°Six 50ΩSMA terminators
°Two GTH transceiver power supply modules (installed on board)
°SuperClock-2 module, Rev 1.0 (installed on board)
°12V DC power adapter
°USB cable, standard-A plug to Micro-B plug
•HostPCwith:
°SD card reader
°USB ports
• Vivado Design Suite 2015.1
The hardware and software required to rebuild the IBERT demonstration designs are:
• Vivado Design Suite 2015.1
• PC with a version of the Windows operating system supported by Vivado Design Suite
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Chapter 1: VC7215 IBERT Getting Started Guide
Setting Up the VC7215 Board
This section describes how to set up the VC7215 board.
CAUTION! The VC7215 board can be damaged by electrostatic discharge (ESD). Follow standard ESD
prevention measures when handling the board.
When the VC7215 board ships from the factory, it is configured for the GTH IBERT
demonstrations described in this document. If the board has been re-configured it must be
returned to the default setup before running the IBERT demonstrations.
1. Move all jumpers and switches to their default positions. The default jumper and switch
positions are listed in VC7215 Virtex-7 FPGA GTH Transceiver Characterization Board
User Guide (UG972) [Ref 1].
2. Install the two GTH transceiver power modules by plugging them into connectors J66
and J97, and connectors J10 and J72.
3. Install the SuperClock-2 module:
a. Align the three metal standoffs on the bottom side of the module with the three
mounting holes in the SUPERCLOCK-2 MODULE interface of the VC7215 board.
b. Using three 4-40 x 0.25 inch screws, firmly screw down the module from the bottom
of the VC7215 board.
c. On the SuperClock-2 module, place a jumper across pins 2–3 (2V5) of the CONTROL
VOLTAGE header, J18, and place another jumper across Si570 INH header J11.
d. Screw down a 50ΩSMA terminator onto each of the six unused Si5368 clock output
SMA connectors: J7, J8, J12, J15, J16 and J17.
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Chapter 1: VC7215 IBERT Getting Started Guide
Extracting the Project Files
The Vivado project files required to run the IBERT demonstrations are located in
rdf0294-vc7215-ibert-2015-1.zip on the SD card provided with the VC7215 board.
They are also available online at the Virtex-7 FPGA VC7215 Characterization Kit website.
The ZIP file contains these files:
•BITfiles
°20 BIT files, one for each of the board’s 20 Quads
(vc7215_ibert_qxxx_325.bit)
•Probefiles
°20 probe files, one for each of the board’s 20 QuadS (vc7215_qxxx_325.ltx)
• The complete project files
•TCLscripts
°add_scm2.tcl
°setup_scm2_325_00.tcl
The Tcl scripts are used to help merge the IBERT and SuperClock-2 source code (described
in Creating the GTH IBERT Core, page 29) and to set up the SuperClock-2 module to run at
325.00 MHz (described in Setting Up Vivado Design Suite, page 16).
To copy the files from the Secure Digital memory card:
1. Connect the Secure Digital memory card labeled IBERT #1 to the host computer.
2. Locate the file rdf0294-vc7215-ibert-2015-1.zip on the Secure Digital memory
card.
3. Unzip the files to a working directory on the host computer.
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Chapter 1: VC7215 IBERT Getting Started Guide
Running the GTH IBERT Demonstration
The GTH IBERT demonstration operates one GTH Quad at a time. This section describes how
to test GTH Quad 115. The remaining GTH Quads are tested following a similar series of
steps.
Connecting the GTH Transceivers and Reference Clocks
Figure 1-1 shows the locations for all GTH transceiver Quads on the VC7215 board.
Note: Figure 1-1 is for reference only and might not reflect the current revision of the board.
X-Ref Target - Figu re 1-1
Figure 1-1: GTH Quad Locations
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Chapter 1: VC7215 IBERT Getting Started Guide
All GTH transceiver pins and reference clock pins are routed from the FPGA to a connector
pad which interfaces with Samtec BullsEye connectors. Figure 1-2 Ashows the connector
pad. Figure 1-2 Bshows the connector pinout.
The SuperClock-2 module provides LVDS clock outputs for the GTH transceiver reference
clocks in the IBERT demonstrations. Figure 1-3 shows the locations of the differential clock
SMA connectors on the clock module which can be connected to the reference clock cables.
Note: The image in Figure 1-3 is for reference only and might not reflect the current revision of the
board.
X-Ref Target - Figure 1-2
Figure 1-2: A – GTH Connector Pad. B – GTH Connector Pinout
X-Ref Target - Figure 1-3
Figure 1-3: SuperClock-2 Module Output Clock SMA Locations
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Chapter 1: VC7215 IBERT Getting Started Guide
The four SMA pairs labeled CLKOUT provide LVDS clock outputs from the Si5368 clock
multiplier/jitter attenuator device on the clock module. The SMA pair labeled Si570_CLK
provides LVDS clock output from the Si570 programmable oscillator on the clock module.
Note: The Si570 oscillator does not support LVDS output on the Rev B and earlier revisions of the
SuperClock-2 module.
For the GTH IBERT demonstration, the output clock frequencies are preset to 325.00 MHz.
For more information regarding the SuperClock-2 module, refer to HW-CLK-101-SCLK2
SuperClock-2 Module User Guide (UG770) [Ref 2].
Attach the GTH Quad Connector
Before connecting the BullsEye cable assembly to the board, firmly secure the blue
elastomer seal provided with the cable assembly to the bottom of the connector housing if
it is not already inserted (see Figure 1-4).
Note: Figure 1-4 is for reference only and might not reflect the current version of the connector.
X-Ref Target - Figure 1-4
Figure 1-4: BullsEye Connector with Elastomer Seal
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Chapter 1: VC7215 IBERT Getting Started Guide
Attach the Samtec BullsEye connector to GTH Quad 115 (Figure 1-5), aligning the two
indexing pins on the bottom of the connector with the guide holes on the board. Hold the
connector flush with the board and fasten it by tightening the two captive screws.
GTH Transceiver Clock Connections
Refer to Figure 1-2, page 9 to identify the P and N coax cables that are connected to the
CLK0 reference clock inputs. Connect these cables to the SuperClock-2 module as follows:
• CLK0_P coax cable → SMA connector J5 (CLKOUT1_P) on the SuperClock-2 module
• CLK0_N coax cable → SMA connector J6 (CLKOUT1_N) on the SuperClock-2 module
Note: Any one of the five differential outputs from the SuperClock-2 module can be used to source
the GTH reference clock. CLKOUT1_P and CLKOUT1_N are used here as an example.
X-Ref Target - Figure 1-5
Figure 1-5: BullsEye Connector Attached to Quad 115
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Chapter 1: VC7215 IBERT Getting Started Guide
GTH TX/RX Loopback Connections
Refer to Figure 1-2, page 9 to identify the P and N coax cables that are connected to the
four receivers (RX0, RX1, RX2 and RX3) and the four transmitters (TX0, TX1, TX2 and TX3).
Use eight SMA female-to-female (F-F) adapters (Figure 1-6), to connect the transmit and
receive cables as shown in Figure 1-7 and detailed below:
•TX0_P→ SMA F-F Adapter → RX0_P
•TX0_N→ SMA F-F Adapter → RX0_N
•TX1_P→ SMA F-F Adapter → RX1_P
•TX1_N→ SMA F-F Adapter → RX1_N
•TX2_P→ SMA F-F Adapter → RX2_P
•TX2_N→ SMA F-F Adapter → RX2_N
•TX3_P→ SMA F-F Adapter → RX3_P
•TX3_N→ SMA F-F Adapter → RX3_N
Note: To ensure good connectivity, it is recommended that the adapters be secured with a wrench;
however, do not over tighten the SMAs.
X-Ref Target - Figure 1-6
Figure 1-6: SMA F-F Adapter
X-Ref Target - Figure 1-7
Figure 1-7: TX-To-RX Loopback Connection Example
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Chapter 1: VC7215 IBERT Getting Started Guide
Figure 1-8 shows the VC7215 board with the cable connections required for the Quad 115
GTH IBERT demonstration.
X-Ref Target - Figu re 1-8
Figure 1-8: Cable Connections for Quad 115 GTH IBERT Demonstration
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Chapter 1: VC7215 IBERT Getting Started Guide
Configuring the FPGA
This section describes how to configure the FPGA using an SD card included with the board.
The FPGA can also be configured through Vivado Design Suite using the .bit files available
on the SC card or online (as collection rdf0294-vc7215-ibert-2015-1.zip) at the
Virtex-7 FPGA VC7215 Characterization Kit website.
To configure from the SD card:
1. Insert the SD card labeled IBERT #1 provided with the VC7215 board into the SD card
reader slot located on the bottom side (upper right corner) of the VC7215 board.
2. Plug the 12V output from the power adapter into connector J2 on the VC7215 board.
3. Connect the host computer to the VC7215 board using a standard-A plug to Micro-B
plug USB cable. The standard-A plug connects to a USB port on the host computer and
the Micro-B plug connects to U17, the Digilent USB JTAG configuration port on the
VC7215 board.
4. Select the GTH IBERT demonstration with the System ACE™ SD controller SYSACE-2 CFG
switch, SW28. The setting on this 4-bit DIP switch (Figure 1-9) selects the file used to
configure the FPGA. A switch is in the ON position if set to the far right and in the OFF
position if set to the far left. For the Quad 115 GTH IBERT demonstration, set
ADR2 = ON, ADR1 = OFF, and ADR0 = ON. The MODE bit (switch position 4) is not used
and can be set either ON or OFF.
X-Ref Target - Figure 1-9
Figure 1-9: Configuration Address DIP Switch (SW28)
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Chapter 1: VC7215 IBERT Getting Started Guide
There is one IBERT demonstration design for each GTH Quad on the VC7215 board, for a
total of twenty IBERT designs. An additional design is provided to demonstrate the
USB/UART interface (details of this demonstration are described in the README file on the
SD card). All twenty designs are organized and stored on three SD cards as shown in
Tabl e 1-1.
5. Place the main power switch SW1 to the ON position.
Table 1-1: SD Card Contents and Configuration Addresses
SD Card Demonstration Design ADR2 ADR1 ADR0
IBERT #1
GTH Quad 110 OFF OFF OFF
GTH Quad 111 OFF OFF ON
GTH Quad 112 OFF ON OFF
GTH Quad 113 OFF ON ON
GTH Quad 114 ON OFF OFF
GTH Quad 115 ON OFF ON
GTH Quad 116 ON ON OFF
GTH Quad 117 ON ON ON
IBERT #2
GTH Quad 118 OFF OFF OFF
GTH Quad 119 OFF OFF ON
GTH Quad 210 OFF ON OFF
GTH Quad 211 OFF ON ON
GTH Quad 212 ON OFF OFF
GTH Quad 213 ON OFF ON
GTH Quad 214 ON ON OFF
GTH Quad 215 ON ON ON
IBERT #3
GTH Quad 216 OFF OFF OFF
GTH Quad 217 OFF OFF ON
GTH Quad 218 OFF ON OFF
GTH Quad 219 OFF ON ON
USB/UART ON OFF OFF
LED Scroll ON OFF ON
Pushbuttons ON ON OFF
DIP Switches ON ON ON
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Chapter 1: VC7215 IBERT Getting Started Guide
Setting Up Vivado Design Suite
1. Start Vivado Design Suite on the host computer and click Flow > Open Hardware
Manager (shown in Figure 1-10).
X-Ref Targ et - Figure 1-10
Figure 1-10: Vivado Design Suite, Open Hardware Manager
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Chapter 1: VC7215 IBERT Getting Started Guide
2. In the Hardware Manager window, click Open New Target (highlighted in Figure 1-11).
3. An Open Hardware Target wizard pops up. Click Next on the first window.
4. In the Hardware Server Settings window, select Local server (target is on local
machine). Click Next to open the server and connect to the Xilinx TCF JTAG cable.
X-Ref Targ et - Figure 1-11
Figure 1-11: Open a New Hardware Target
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Chapter 1: VC7215 IBERT Getting Started Guide
5. In the Select Hardware Target window, the xilinx_tcf cable appears under
Hardware Targets. The JTAG chain contents of the selected cable appear under the
Hardware Devices window (Figure 1-12). Select the xilinx_tcf target and keep the JTAG
Clock Frequency at the default value (15 MHz). Cick Next.
6. In the Open Hardware Target Summary window, click Finish. The wizard closes and the
Vivado Design Suite opens the hardware target.
X-Ref Targ et - Figure 1-12
Figure 1-12: Select Hardware Target
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Chapter 1: VC7215 IBERT Getting Started Guide
Starting the SuperClock-2 Module
The IBERT demonstration designs use an integrated VIO core to control the clocks on the
SuperClock-2 module. The SuperClock-2 module features two clock-source components:
• An always-on Si570 crystal oscillator
• An Si5368 jitter-attenuating clock multiplier.
Outputs from either device can be used to drive the transceiver reference clocks.
To start the SuperClock-2 module:
1. The Vivado Design Suite Hardware Manager window shows the System ACE™ SD
Controller and the XC7VX690T device. The XC7VX690T_1 device is reported as
programmed. In the Hardware Device Properties window, enter the file path to the Q115
probes file (vc7215_ibert_q115_debug_nets.ltx) in the extracted IBERT files
from the SD card (Figure 1-13).
X-Ref Targ et - Figure 1-13
Figure 1-13: Adding the Probes File
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Chapter 1: VC7215 IBERT Getting Started Guide
2. In the Hardware window, right-click XC7VX690T_1 and select Refresh Device
(Figure 1-14).
Note: If the FPGA was not programmed using the SD card, provide both the programming and
the probes files, and select Program Device.
X-Ref Target - Figure 1-14
Figure 1-14: Refresh/Program Device
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